| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | generic: MIPS: Add barriers between dcache & icache flushes | David Bauer | 2023-03-04 | 1 | -0/+71 |
| This fixes spurious boot-errors with some ath79 MIPS 74Kc boards such as the AC Lite as well as Archer C7 v2. The missing barrier leads to the icache flush being executed before the dcache writeback, which results in the CPU executing the dummy infinite loop in tlbmiss_handler_setup_pgd. Applying this patch from upstream ensures the dcache is written back before flushing the icache. Signed-off-by: David Bauer <mail@david-bauer.net> | |||||
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index : openwrt/upstream | |
| upstream openwrt | James |
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path: root/target/linux/generic/pending-5.15/301-MIPS-Add-barriers-between-dcache-icache-flushes.patch