openwrt/upstream - upstream openwrt

	Commit message (Collapse)	Author	Age	Files	Lines
*	b53: update header register difinitions	Jonas Gorski	2016-01-18	1	-1/+2
\| \| \| \| \| \| \| \| \|	BCM531x5 has two pontential cpu ports, and header mode can be enabled independently on both. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 48302
*	b53: widen stp state mask to 3 bits (instead of 2)	Jonas Gorski	2015-06-10	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	At least on my b53 chip, the mask is 3 bits wide, and because of this some STP states are not set properly and discarded when read. Maybe for some other chips it makes sense to have just 2 bits width, but I don't have other versions around to test/validate. If that's the case then maybe we could add another STP state mask. Signed-off-by: Alexandru Ardelean <ardeleanalex@gmail.com> Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 45937
*	b53: improve overriding CPU port state on BCM5301X	Rafał Miłecki	2015-04-12	1	-0/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	On BCM5301X there are two different cases to handle: CPU port 8 vs. any other one. Support for CPU port 8 was already partially implemented but it lacked setting some extra bit for 2G speed. It also will need to be extended to implement "SMP dual core 3 GMAC setup". That's the reason for handling it in separated code block. This patch also adds overriding CPU port state for port other than 8. It requires using recently defined GMII_PORT registers. It was tested for regressions on BCM53011 revs 2 & 3. It was also confirmed to fix switch on some internal Broadcom board. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 45402
*	b53: clean up code to match kernel style better	Jonas Gorski	2015-04-10	1	-4/+4
\| \| \| \| \| \| \| \| \| \| \| \| \|	* properly enclose macro arguments in paranthesis on use * remove trailing white space * convert C99 // comments * add missing blank lines after declaration * remove braces from single statement blocks * split lines > 80 chars (except for one) Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 45356
*	b53: define registers available and needed on BCM5301X	Jonas Gorski	2015-04-10	1	-0/+33
\| \| \| \| \| \| \| \|	They are also present on some BCM63xx switches. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> SVN-Revision: 45355
*	b53: reverse duplex bit meaning for IMP state override register	Jonas Gorski	2015-03-18	1	-1/+1
\| \| \| \| \| \| \|	Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 44875
*	kernel: b53: fix untagged shift for BCM5365	Hauke Mehrtens	2013-11-13	1	-2/+4
\| \| \| \| \| \| \| \| \| \| \|	The BCM5365 needs a shift of 7 bits and not 6 bits like the BCM5325 for the untagged ports. Thank you Russell for reporting this and testing the patch. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 38793
*	kernel: b53: detect revision of BCM5325	Hauke Mehrtens	2013-09-15	1	-0/+3
\| \| \| \| \| \| \| \| \|	The revision is stored in a different register than it is in other Broadcom switches. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 37995
*	generic: add b53 swconfig switch driver	Jonas Gorski	2013-01-23	1	-0/+308
	Add swconfig switch driver for Broadcom BCM53XX switch chips. Supports switches connected through MDIO, SPI or memory mapped registers, and supports BCM5325, BCM539x, BCM531x5 and the BCM63XX internal switch chips. Tested are BCM5325 trough MDIO, BCM53115 through SPI, and BCM6328. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 35305