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* ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344Christian Lamparter2018-08-131-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some AR9344 boards do very poorly with the default settings and need custom rxdv-delay, rxd-delay, txd-delay, txen-delay flags to perform reasonably. In this case the WD My Net Wi-Fi Range Extender can not even manage 10Mbps on a 1Gbit link: root@AR9344:~# iperf3 -s ----------------------------------------------------------- Server listening on 5201 ----------------------------------------------------------- Accepted connection from client [...] [ 5] local [...] connected to client [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 1.09 MBytes 9.16 Mbits/sec [ 5] 1.00-2.00 sec 895 KBytes 7.33 Mbits/sec [ 5] 2.00-3.00 sec 762 KBytes 6.25 Mbits/sec [...] [ 5] 10.00-10.03 sec 17.0 KBytes 4.74 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.03 sec 9.00 MBytes 7.52 Mbits/sec with but with the correct settings in place, it does much better: root@AR9344:~# iperf3 -s ----------------------------------------------------------- Server listening on 5201 ----------------------------------------------------------- Accepted connection from client [...] [ 5] local [...] connected to client [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 23.1 MBytes 193 Mbits/sec [ 5] 1.00-2.00 sec 23.1 MBytes 194 Mbits/sec [ 5] 2.00-3.00 sec 23.2 MBytes 195 Mbits/sec [...] [ 5] 10.00-10.04 sec 710 KBytes 180 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.04 sec 237 MBytes 198 Mbits/sec The tx data and enable delay bits definitions are taken from Atheros' AR9344 Data Sheet Section "8.6.1 Ethernet Configuration (ETH_CFG)" on page 153. Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ath79: add QCA956x GMAC configDavid Bauer2018-08-131-0/+13
| | | | | | This commit adds the ability to configure the GMAC of the QCA956x. Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: ag71xx: fix speed applied to MII0/1_CTRL on ar71xx/ar913xChuanhong Guo2018-08-131-2/+2
| | | | | | Currently speed value is applied to interface mode field. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: remove PHY resetChuanhong Guo2018-08-092-10/+0
| | | | | | | | | | | | Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET in datasheets will trigger either a reset for builtin switch or assert an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected to external PHY/switch. None of them should be triggered every time an interface is brought up in ethernet driver. Remove PHY reset support from ag71xx and definition for them in dtsi. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: assert a switch reset if defined in dts.Chuanhong Guo2018-07-301-0/+9
| | | | Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Explicitly register mdio bus after ag71xx_hw_init() for ar7240Chuanhong Guo2018-07-301-0/+8
| | | | | | | | | | mdio bus isn't a standalone device on ar7240. (and maybe older SoCs?) Use simple-mfd for ar7241 and later SoCs to get mdio1 ready before gmac0 For ar7240 and older chips, manually create platform device after ag71xx_hw_init() in ag71xx_probe()to get mdio0 ready between ag71xx_hw_init() and ag71xx_phy_connect(). Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Rework mdio clock settingsChuanhong Guo2018-07-301-26/+62
| | | | | | | Allow specifying desired mdio clock frequency in dts. Use default frequency around 5MHz for builtin switch and 2MHz for other mdio bus. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Make builtin switch driver a separated moduleChuanhong Guo2018-07-302-68/+84
| | | | | | | | | This patch did several things: 1. Probe the builtin switch as a separated mdio device. 2. Register a separated mdio bus for builtin switch. 3. Use generic mdio read/write function instead of calling ag71xx_mdio_mii_read/write directly. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Split mdio driver into an independent platform device.Chuanhong Guo2018-07-304-84/+78
| | | | | | | We need to have mdio1 belonging to gmac1 initialized before gmac0. Split it into a separated mdio device to get both mdios ready before probing gmac. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Remove ar7240_set_addr and ag71xx_ar7240_startChuanhong Guo2018-07-303-29/+1
| | | | | | | | The builtin switch has it's initial valid mac address(00:00:01:00:00:00). Since the builtin switch is an independent device, setting mac address of gmac1 to builtin switch isn't a good idea and this makes it impossilbe to split builtin switch apart as an independent platform device. Remove these functions and apply default VLAN during initialization as a preparation for further driver splitting. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Split gmac config into separated file and add support for ↵Chuanhong Guo2018-07-304-58/+116
| | | | | | ar934x/qca955x. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: drop mv88e6063 switch driverMathias Kresin2018-07-041-289/+0
| | | | | | | | Due do a missing KCONFIG isn't selectable nor enabled in the target kernel config. Drop it for now and enable/add the driver at the time it is required. Signed-off-by: Mathias Kresin <dev@kresin.me>
* ath79: fix rx ring buffer stall qca956xLucian Cristian2018-06-181-1/+2
| | | | | | when ported from ar71xx to ath79 the qca9560-eth was omitted Signed-off-by: Lucian Cristian <lucian.cristian@gmail.com>
* ath79: ag71xx: fix pll-data setting for ar7242/ar934x/qca955x/qca956xWeijie Gao2018-06-181-10/+7
| | | | | | | | | | | ar71xx/ar913x series use the old pll registers and settings. However started from ar7242, a new pll register is introduced and the pll setting is much simpler. This can be observed from dev-eth.c from the ar71xx target. Signed-off-by: Weijie Gao <hackpascal@gmail.com>
* ath79: fix adjust_link callback for ar9130John Crispin2018-05-241-0/+2
| | | | Signed-off-by: John Crispin <john@phrozen.org>
* ath79: preliminary support for TP-Link WDR3600 / WDR4300 (AR9344)Johann Neuhauser2018-05-221-0/+1
| | | | | | | | | | | | | | | | working: - leds - buttons - lan / wan - usb (hub port 1 + 2) - wifi 5g - sysupgrade - ... not working: - wifi 2g Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
* ath79: fix gmac compatible in ar9330.dtsi and ag71xx_setup_gmac_933xJohann Neuhauser2018-05-151-1/+1
| | | | | | | | | 1. compatible property in node gmac was wrong 2. ag71xx_setup_gmac_933x should use np of gmac-config and not the pointer to gmac. gmac is only used for the reg address. Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
* ath79: add new OF only target for QCA MIPS siliconJohn Crispin2018-05-0714-0/+4848
This target aims to replace ar71xx mid-term. The big part that is still missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik subtargets will follow. Signed-off-by: John Crispin <john@phrozen.org>
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