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* ath79: gmac: ar934x: Add parser for mii-gmac0-slavePetr Štetiar2019-03-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | While converting Nanostation M XW from current ar71xx code to ath79 I've hit one issue, where the ethernet networking wasn't working, so I was checking every bit in the networking setup path between ar71xx and ath79. I've came to the following code in ar71xx/mach-ubnt-xm.c: static void __init ubnt_xw_init(void) { ... ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0_SLAVE); ... } Where this code is setting AR934X_ETH_CFG_MII_GMAC0_SLAVE bit in AR934X_GMAC_REG_ETH_CFG register, but I couldn't find a way of setting this bit from DTS, so this patch adds `mii-gmac0-slave` DTS property which allows setting of this bit in `gmac-config`, which is then used in Nanostation M XW DTS. Tested-by: Joe Ayers <ae6xe@arrl.net> Signed-off-by: Petr Štetiar <ynezz@true.cz>
* ath79: ag71xx: add support for optional mdio resetChuanhong Guo2019-03-052-1/+8
| | | | | | | | | | | | | | | | | | | | | | On ar933x and later chips, there are separated mac/mdio resets, but resetting the entire gmac block with register values requires both mac_reset and mdio_reset to be asserted together. Add support for optional mdio reset so that we can do a full reset if needed. This patch also replaced deprecated devm_reset_control_get for mac reset. To use this feature, the following is needed: 1. drop "simple-mfd" compatible to register mdio0 after gmac init so that mdio registers aren't reset after initialization. 2. move mdio reset from mdio-bus to its parent eth node. NOTE: This can't be applied on gmac1 with builtin switch since we haven't add a feature to defer probe if phy connection failed. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: register mdio using of_platform_populateChuanhong Guo2019-03-051-5/+12
| | | | | | | remove the hacky checking of "simple-mfd" compatible also add some comments explaining that piece of code. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx-mdio: get reset control using devm apiChuanhong Guo2019-03-051-1/+1
| | | | Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: replace alloc_etherdev with devm_alloc_etherdevChuanhong Guo2019-03-051-22/+11
| | | | | | | | using the devm api makes the code simpler. also drop unneeded memory free from ag71xx_remove since they are allocated using devm apis. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: replace ag71xx_get_phy_if_mode_name() with phy_modes()Chuanhong Guo2019-03-051-22/+2
| | | | | | | | | phy_modes() in phy.h can convert PHY modes to string with supports for all available PHY modes. Also add a space in mode printing to make it look better. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Fix tx queue timeouts during ifupPetr Štetiar2019-02-071-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ath79 and UBNT Bullet M XW (ar9342) I was experiencing weird issues during network setup[1] which I was able to reproduce easily with following commands: uci set network.lan.ipaddr='192.168.1.20' uci commit network ifup lan Which resulted after some time in: ... WARNING: CPU: 0 PID: 0 at net/sched/sch_generic.c:461 dev_watchdog+0x16c/0x280 NETDEV WATCHDOG: eth0 (ag71xx): transmit queue 0 timed out ... Sometimes I wasn't able to use networking anymore, sometimes it was enough to just ifdown/ifup lan and network was backup. On ar71xx it was all working just fine. I've found out, that it was happening because ag71xx_poll() wasn't called, thus the TX queue wasn't emptied. The ag71xx_poll() is being called from napi hrtimer, which is enabled by napi_schedule() in ar71xx_interrupt(), but since no interrupts were ever fired again after ag71xx_stop() was called, it was always leading to tx queue timeouts: *** ag71xx_hard_start_xmit() eth0: packet injected into TX queue eth0: raw intr=00000001 TXPS POLL eth0: enable polling mode eth0: processing TX ring, flush=no eth0: disable polling mode, rx=1, tx=1,limit=32 ( `ifup lan done here` ) *** ag71xx_stop() *** ag71xx_open() *** ag71xx_hw_enable() IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready *** ag71xx_hard_start_xmit() eth0: packet injected into TX queue *** ag71xx_hard_start_xmit() eth0: packet injected into TX queue ... WARNING: CPU: 0 PID: 0 at net/sched/sch_generic.c:320 dev_watchdog+0x164/0x274 So I've looked at ag71xx_stop() in ar71xx, added the missing bits to ath79 and fixed this issue. 1. https://github.com/openwrt/openwrt/pull/1635#issuecomment-448638246 Signed-off-by: Petr Štetiar <ynezz@true.cz> [move ag->link before ag71xx_hw_disable to retain ordering as original] Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
* ath79: ag71xx: preserve port mirror flags during swconfig applyMilan Krstic2019-01-221-0/+4
| | | | | | | | The swconfig load operation always triggers 'apply' function which in this driver currently clears port mirroring flags effectively undoing port mirroring configuration. Signed-off-by: Milan Krstic <milan.krstic@gmail.com>
* ath79: ag71xx: Fix code formatting in ag71xx_probePetr Štetiar2018-12-171-2/+2
| | | | Signed-off-by: Petr Štetiar <ynezz@true.cz>
* ath79: ag71xx: Unify debug output with ar71xx and make debugging easierPetr Štetiar2018-12-171-16/+32
| | | | | | | | | Currently it's quite hard to diff debugging output between ar71xx and ath79, so this patch tries to improve it by adding the same ag71xx_dump_regs function and placing debugging output from the registers to relatively same places. Signed-off-by: Petr Štetiar <ynezz@true.cz>
* ath79: port cybertan_part from ar71xxChristian Lamparter2018-09-101-0/+163
| | | | | | | | | | | | | This patch ports the cybertan_part code from ar71xx and converts the driver to a DT-supported mtd parser. As a result, it will no longer add the u-boot, nvram and art partitions, which were never part of the special Cybertan header. Instead these partitions have to be specified in the DT, which has the upside of making it possible to add properties (i.e.: read-only), labels and references to these important partitions. Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ath79: fix unaligned access panic in ag71xx_mdio_probeMatt Merhar2018-09-061-2/+2
| | | | | | | | | | | Without "syscon" being present in an ag71xx ethernet DT node's compatible property, a panic occurs at boot during probe citing "Unhandled kernel unaligned access". With this modification, the panic no longer occurs and instead the probe simply fails, allowing the boot process to continue. Signed-off-by: Matt Merhar <mattmerhar@protonmail.com>
* ath79: ag71xx: apply interface mode to MII0/1_CTRL on ar71xx/ar913xChuanhong Guo2018-08-282-0/+70
| | | | | | | | | | | | | We currently don't have any code configuring interface mode in ath79, meaning that we relies on bootloader to set the correct interface mode. This patch added code to set interface correctly so that everything works even if bootloader configures it wrong.(e.g. on WNDR3800 u-boot set the second GMAC mode to RMII but it should be RGMII.) Introduced "qca,mac-idx" for the difference in MII_CTRL register value. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: gmac: add parsers for rxd(v)- and tx(d|en)-delay for AR9344Christian Lamparter2018-08-131-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some AR9344 boards do very poorly with the default settings and need custom rxdv-delay, rxd-delay, txd-delay, txen-delay flags to perform reasonably. In this case the WD My Net Wi-Fi Range Extender can not even manage 10Mbps on a 1Gbit link: root@AR9344:~# iperf3 -s ----------------------------------------------------------- Server listening on 5201 ----------------------------------------------------------- Accepted connection from client [...] [ 5] local [...] connected to client [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 1.09 MBytes 9.16 Mbits/sec [ 5] 1.00-2.00 sec 895 KBytes 7.33 Mbits/sec [ 5] 2.00-3.00 sec 762 KBytes 6.25 Mbits/sec [...] [ 5] 10.00-10.03 sec 17.0 KBytes 4.74 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.03 sec 9.00 MBytes 7.52 Mbits/sec with but with the correct settings in place, it does much better: root@AR9344:~# iperf3 -s ----------------------------------------------------------- Server listening on 5201 ----------------------------------------------------------- Accepted connection from client [...] [ 5] local [...] connected to client [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 23.1 MBytes 193 Mbits/sec [ 5] 1.00-2.00 sec 23.1 MBytes 194 Mbits/sec [ 5] 2.00-3.00 sec 23.2 MBytes 195 Mbits/sec [...] [ 5] 10.00-10.04 sec 710 KBytes 180 Mbits/sec - - - - - - - - - - - - - - - - - - - - - - - - - [ ID] Interval Transfer Bitrate [ 5] 0.00-10.04 sec 237 MBytes 198 Mbits/sec The tx data and enable delay bits definitions are taken from Atheros' AR9344 Data Sheet Section "8.6.1 Ethernet Configuration (ETH_CFG)" on page 153. Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
* ath79: add QCA956x GMAC configDavid Bauer2018-08-131-0/+13
| | | | | | This commit adds the ability to configure the GMAC of the QCA956x. Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: ag71xx: fix speed applied to MII0/1_CTRL on ar71xx/ar913xChuanhong Guo2018-08-131-2/+2
| | | | | | Currently speed value is applied to interface mode field. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: remove PHY resetChuanhong Guo2018-08-092-10/+0
| | | | | | | | | | | | Bit 8/12 of reset controller which is marked as PHY_RESET/SWITCH_RESET in datasheets will trigger either a reset for builtin switch or assert an external ETH0_RESET_L/ETH1_RESET_L pin, which are usually connected to external PHY/switch. None of them should be triggered every time an interface is brought up in ethernet driver. Remove PHY reset support from ag71xx and definition for them in dtsi. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: assert a switch reset if defined in dts.Chuanhong Guo2018-07-301-0/+9
| | | | Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Explicitly register mdio bus after ag71xx_hw_init() for ar7240Chuanhong Guo2018-07-301-0/+8
| | | | | | | | | | mdio bus isn't a standalone device on ar7240. (and maybe older SoCs?) Use simple-mfd for ar7241 and later SoCs to get mdio1 ready before gmac0 For ar7240 and older chips, manually create platform device after ag71xx_hw_init() in ag71xx_probe()to get mdio0 ready between ag71xx_hw_init() and ag71xx_phy_connect(). Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Rework mdio clock settingsChuanhong Guo2018-07-301-26/+62
| | | | | | | Allow specifying desired mdio clock frequency in dts. Use default frequency around 5MHz for builtin switch and 2MHz for other mdio bus. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Make builtin switch driver a separated moduleChuanhong Guo2018-07-302-68/+84
| | | | | | | | | This patch did several things: 1. Probe the builtin switch as a separated mdio device. 2. Register a separated mdio bus for builtin switch. 3. Use generic mdio read/write function instead of calling ag71xx_mdio_mii_read/write directly. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Split mdio driver into an independent platform device.Chuanhong Guo2018-07-304-84/+78
| | | | | | | We need to have mdio1 belonging to gmac1 initialized before gmac0. Split it into a separated mdio device to get both mdios ready before probing gmac. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Remove ar7240_set_addr and ag71xx_ar7240_startChuanhong Guo2018-07-303-29/+1
| | | | | | | | The builtin switch has it's initial valid mac address(00:00:01:00:00:00). Since the builtin switch is an independent device, setting mac address of gmac1 to builtin switch isn't a good idea and this makes it impossilbe to split builtin switch apart as an independent platform device. Remove these functions and apply default VLAN during initialization as a preparation for further driver splitting. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: ag71xx: Split gmac config into separated file and add support for ↵Chuanhong Guo2018-07-304-58/+116
| | | | | | ar934x/qca955x. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: drop mv88e6063 switch driverMathias Kresin2018-07-041-289/+0
| | | | | | | | Due do a missing KCONFIG isn't selectable nor enabled in the target kernel config. Drop it for now and enable/add the driver at the time it is required. Signed-off-by: Mathias Kresin <dev@kresin.me>
* ath79: fix rx ring buffer stall qca956xLucian Cristian2018-06-181-1/+2
| | | | | | when ported from ar71xx to ath79 the qca9560-eth was omitted Signed-off-by: Lucian Cristian <lucian.cristian@gmail.com>
* ath79: ag71xx: fix pll-data setting for ar7242/ar934x/qca955x/qca956xWeijie Gao2018-06-181-10/+7
| | | | | | | | | | | ar71xx/ar913x series use the old pll registers and settings. However started from ar7242, a new pll register is introduced and the pll setting is much simpler. This can be observed from dev-eth.c from the ar71xx target. Signed-off-by: Weijie Gao <hackpascal@gmail.com>
* ath79: fix adjust_link callback for ar9130John Crispin2018-05-241-0/+2
| | | | Signed-off-by: John Crispin <john@phrozen.org>
* ath79: preliminary support for TP-Link WDR3600 / WDR4300 (AR9344)Johann Neuhauser2018-05-221-0/+1
| | | | | | | | | | | | | | | | working: - leds - buttons - lan / wan - usb (hub port 1 + 2) - wifi 5g - sysupgrade - ... not working: - wifi 2g Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
* ath79: fix gmac compatible in ar9330.dtsi and ag71xx_setup_gmac_933xJohann Neuhauser2018-05-151-1/+1
| | | | | | | | | 1. compatible property in node gmac was wrong 2. ag71xx_setup_gmac_933x should use np of gmac-config and not the pointer to gmac. gmac is only used for the reg address. Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
* ath79: add new OF only target for QCA MIPS siliconJohn Crispin2018-05-0714-0/+4848
This target aims to replace ar71xx mid-term. The big part that is still missing is making the MMIO/AHB wifi work using OF. NAND and mikrotik subtargets will follow. Signed-off-by: John Crispin <john@phrozen.org>
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