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* ath79: enable UART in SoC DTSI filesAdrian Schmutzler2021-02-241-2/+0
| | | | | | | | | | | | | | | The uart node is enabled on all devices except one (GL-USB150 *). Thus, let's not have a few hundred nodes to enable it, but do not disable it in the first place. Where the majority of devices is using it, also move the serial0 alias to the DTSI. *) Since GL-USB150 even defines serial0 alias, the missing uart is probably just a mistake. Anyway, disable it for now so this patch stays cosmetic. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: specify device-type for PCI controllersDavid Bauer2021-02-201-0/+2
| | | | | | | | Specify the device_type property for PCI as well as PCIe controllers. Otherwise, the PCI range parser will not be selected when using kernel 5.10. Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: move ath79-clk.h include to ath79.dtsiAdrian Schmutzler2020-09-251-1/+1
| | | | | | | | | | ath79.dtsi uses ATH79_CLK_MDIO, so the include <dt-bindings/clock/ath79-clk.h> needs to be moved there. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: drop and consolidate redundant chosen/bootargsAdrian Schmutzler2020-06-251-0/+4
| | | | | | | | | | | | | | In ath79, for several SoCs the console bootargs are defined to the very same value in every device's DTS. Consolidate these definitions in the SoC dtsi files and drop further redundant definitions elsewhere. The only device without any bootargs set has been OpenMesh OM5P-AC V2. This will now inherit the setting from qca955x.dtsi Note that while this tidies up master a lot, it might develop into a frequent pitfall for backports. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: add QCA9550 reset sequenceDavid Bauer2020-04-171-0/+3
| | | | | | | | | | | | | | | | | The QCA9550 family of SoCs have a slightly different reset sequence compared to older chips. Normally the bootloader performs this sequence, however some bootloader implementation expect the operating system to clear the reset. Also get the PCIe resets from OF to support the second RC of the QCA9558. This is required for the AVM FRITZ!WLAN Repeater 1750E to work, as EVA leaves the PCIe bus in reset. Tested: AVM FRITZ!WLAN Repeater 1750E - OCEDO Koala Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: add new ar934x spi driverChuanhong Guo2020-02-061-3/+2
| | | | | | | | | | | A new shift mode was introduced since ar934x which has a way better performance than current bitbang driver and can handle higher spi clock properly. This commit adds a new driver to make use of this new feature. This new driver has chipselect properly configured and we don't need cs-gpios hack in dts anymore. Remove them. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: do not set inherited phy-mode/status properties againAdrian Schmutzler2020-01-311-2/+0
| | | | | | | | | There are several cases where phy-mode and status properties are set again in DTS(I) files although those were set to the same values in parent DTSI files already. Remove those cases (and thus also stop their proliferation by copy/paste). Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: ar93xx/qca95xx: move gmac/wmac/pcie node out of apb busChuanhong Guo2019-07-161-31/+31
| | | | | | | | according to functional block diagram in datasheet, these devices don't belong to apb bus. Move these nodes out to match datasheet description. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: dts: drop "simple-mfd" for gmacs in SoC dtsiChuanhong Guo2019-06-051-2/+2
| | | | | | | | | | | | With a proper probe deferring for ag71xx we don't need to explicitly probe mdio1 before gmac0. Drop all "simple-mfd" in SoC dtsi so that gmac orders can be the same as ar71xx. This makes eth0/eth1 order the same as those in ar71xx, which means we don't need a migration script for this anymore and we can merge incorrectly split gmac/mdio driver back together. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: use ar8216 for builtin switchChuanhong Guo2019-03-241-2/+3
| | | | Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: fix pinmux reg value for QCA956xINAGAKI Hiroshi2018-12-241-1/+1
| | | | | | | | | | | | | The range of pinmux reg property "<0x1804002c 0x40>" for QCA956x SoC does not includes GPIO_FUNCTION register. If the device uses "&jtag_disable_pins", this causes the following errors: [ 1.982937] pinctrl-single 1804002c.pinmux: mux offset out of range: 0x40 (0x40) [ 1.990622] pinctrl-single 1804002c.pinmux: could not add functions for pinmux_jtag_disable_pins 64x Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* ath79: fix dtc compiler warningsMathias Kresin2018-12-121-2/+1
| | | | | | | | | | | | The qca9557/qca956x reset-controller aren't a simple bus. A simple bus would require node unit addresses. Add the node unit addresses for the qca9557 usb phys. Add the regs for the USB_PWRCTL and USB_CONFIG registers even not yet used. Fix the wrong ar7100 pcie controller node unit address as well. Signed-off-by: Mathias Kresin <dev@kresin.me>
* ath79: add QCA956x GMAC configDavid Bauer2018-08-131-0/+5
| | | | | | This commit adds the ability to configure the GMAC of the QCA956x. Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: fix dts warningsMathias Kresin2018-08-081-4/+4
| | | | | | | Fix all issues found by the devicetree compiler like wrong address/size cells as well as wrong/missing/superfluous unit addresses. Signed-off-by: Mathias Kresin <dev@kresin.me>
* ath79: Add switch reset definition in dtsChuanhong Guo2018-07-301-0/+2
| | | | Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: qca956x: Update dts for current ag71xx driverChuanhong Guo2018-07-301-4/+30
| | | | | | | | enable mdio1 by default because mdio1 node is a subnode of eth1 and eth1 node is a "simple-mfd", which makes mdio1 disabled when eth1 isn't enabled. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: qca95xx: add new intc2, correct intc3 and add second pcie on qca9557Johann Neuhauser2018-06-201-2/+4
| | | | Signed-off-by: Johann Neuhauser <johann@it-neuhauser.de>
* ath79: add support for Phicomm K2TWeijie Gao2018-06-181-0/+281
This patch adds dts for qca956x and also support for Phicomm K2T The qca965x.dtsi adds nearly all the necessary components. Both ath9k AHB and PCIe worked well. The Phicomm K2T uses MTD partition 'config' to store the mac addresses in JSON format. To extract these fields correctly, a script is introduced: /lib/functions/k2t.sh This script provides a helper function to extract mac addresses, and is used in three places. Hardware spec of Phicomm K2T: CPU: QCA9563 DRAM: 64MB DDR2 Flash: 16MB SPI-NOR Switch: QCA8337 WiFi 5.8GHz: QCA9886 Flash instruction: Apply sysupgrade.bin via serial console: tftp 0x80000000 sysupgrade.bin && erase 0x9f090000 +$filesize && cp.b $fileaddr 0x9f090000 $filesize Signed-off-by: Weijie Gao <hackpascal@gmail.com>
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