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* ath79: enable UART in SoC DTSI filesAdrian Schmutzler2021-02-241-2/+0
| | | | | | | | | | | | | | | The uart node is enabled on all devices except one (GL-USB150 *). Thus, let's not have a few hundred nodes to enable it, but do not disable it in the first place. Where the majority of devices is using it, also move the serial0 alias to the DTSI. *) Since GL-USB150 even defines serial0 alias, the missing uart is probably just a mistake. Anyway, disable it for now so this patch stays cosmetic. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: specify device-type for PCI controllersDavid Bauer2021-02-201-0/+2
| | | | | | | | Specify the device_type property for PCI as well as PCIe controllers. Otherwise, the PCI range parser will not be selected when using kernel 5.10. Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: move ath79-clk.h include to ath79.dtsiAdrian Schmutzler2020-09-251-1/+1
| | | | | | | | | | ath79.dtsi uses ATH79_CLK_MDIO, so the include <dt-bindings/clock/ath79-clk.h> needs to be moved there. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: fix QCA953x DDR and GPIO compatible bindingsDavid Bauer2020-04-241-2/+2
| | | | | | | The memory as well as GPIO controller had the wrong SoC name used for their compatible binding. Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: add QCA9550 reset sequenceDavid Bauer2020-04-171-0/+3
| | | | | | | | | | | | | | | | | The QCA9550 family of SoCs have a slightly different reset sequence compared to older chips. Normally the bootloader performs this sequence, however some bootloader implementation expect the operating system to clear the reset. Also get the PCIe resets from OF to support the second RC of the QCA9558. This is required for the AVM FRITZ!WLAN Repeater 1750E to work, as EVA leaves the PCIe bus in reset. Tested: AVM FRITZ!WLAN Repeater 1750E - OCEDO Koala Signed-off-by: David Bauer <mail@david-bauer.net>
* ath79: add new ar934x spi driverChuanhong Guo2020-02-061-3/+2
| | | | | | | | | | | A new shift mode was introduced since ar934x which has a way better performance than current bitbang driver and can handle higher spi clock properly. This commit adds a new driver to make use of this new feature. This new driver has chipselect properly configured and we don't need cs-gpios hack in dts anymore. Remove them. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: do not set inherited phy-mode/status properties againAdrian Schmutzler2020-01-311-2/+0
| | | | | | | | | There are several cases where phy-mode and status properties are set again in DTS(I) files although those were set to the same values in parent DTSI files already. Remove those cases (and thus also stop their proliferation by copy/paste). Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: fix whitespace issues in DTS filesAdrian Schmutzler2019-10-061-3/+0
| | | | | | | | | This is the result of grepping/searching for several common whitespace issues like double empty lines, leading spaces, etc. This patch fixes them for the ath79 target. Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
* ath79: ar93xx/qca95xx: move gmac/wmac/pcie node out of apb busChuanhong Guo2019-07-161-32/+32
| | | | | | | | according to functional block diagram in datasheet, these devices don't belong to apb bus. Move these nodes out to match datasheet description. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: dts: drop "simple-mfd" for gmacs in SoC dtsiChuanhong Guo2019-06-051-1/+1
| | | | | | | | | | | | With a proper probe deferring for ag71xx we don't need to explicitly probe mdio1 before gmac0. Drop all "simple-mfd" in SoC dtsi so that gmac orders can be the same as ar71xx. This makes eth0/eth1 order the same as those in ar71xx, which means we don't need a migration script for this anymore and we can merge incorrectly split gmac/mdio driver back together. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: use ar8216 for builtin switchChuanhong Guo2019-03-241-2/+3
| | | | Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: fix wmac memory region for qca953xChuanhong Guo2019-02-201-1/+1
| | | | | | | According to /arch/mips/include/asm/mach-ath79/ar71xx_regs.h the size of wmac register range for qca953x is only 0x20000. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
* ath79: rename qca9533.dtsi to qca953x.dtsiChuanhong Guo2018-12-061-0/+286
qca9533 is a costdown version of qca9531 which doesn't have USB and PCIE. Rename the misleading dtsi names and fix the SoC type of gl-ar300m. Signed-off-by: Chuanhong Guo <gch981213@gmail.com> [apply the changes for the gl-x750 as well] Signed-off-by: Mathias Kresin <dev@kresin.me>