| Commit message (Collapse) | Author | Age | Files | Lines |
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Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
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The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms"
datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a
40 Mhz reference clock. The register description for "Bootstrap Options"
(page 31) defines following states for the bit 4 (REF_CLK):
* 0 - CLK25 (default)
* 1 - (reserved)
Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25
Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and
then break the bootup of the system due to this incorrect interpretation.
Signed-off-by: Sven Eckelmann <sven@narfation.org>
[refreshed patches]
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
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Refresh patches.
Compile-tested on ar71xx.
Runtime-tested on ar71xx.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
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it fixes
Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 48563
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