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path: root/target/linux/ar71xx/patches-2.6.39
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* ar71xx: add mtd partition parser for the TP-Link boardsGabor Juhos2011-12-031-0/+25
* ar71xx: run the RedBoot parser only on the RedBoot based boardsGabor Juhos2011-12-031-18/+0
* ar71xx: run the MyLoader parser only on the WP543 boardGabor Juhos2011-12-032-22/+3
* ar71xx: run the wrt160nl parser only on the WRT160NL boardGabor Juhos2011-12-031-19/+0
* ar71xx: allow to pass part_probe types to the m25p80 driverGabor Juhos2011-12-034-5/+28
* ar71xx: merge nand scan patchGabor Juhos2011-11-141-22/+0
* ar71xx: fix occasional kernel hangs during boot on AR934xGabor Juhos2011-11-131-0/+104
* ar71xx: refresh kernel patchesGabor Juhos2011-11-132-4/+4
* ar71xx: add a workaround for ar8316 not always driving the TA bit to lowJonas Gorski2011-10-111-0/+20
* ar71xx: make ehci patch apply againJonas Gorski2011-08-101-2/+2
* ar71xx: add some hacks to work around the misalignment in IP packets received...Felix Fietkau2011-08-021-0/+117
* ar71xx: merge 2.6.39 patchesGabor Juhos2011-06-291-259/+0
* ar71xx: add 2.6.39 supportGabor Juhos2011-06-2935-0/+1253
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/dts-v1/;

#include "mt7620a.dtsi"

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	compatible = "tplink,c20-v1", "ralink,mt7620a-soc";
	model = "TP-Link Archer C20 v1";

	aliases {
		led-boot = &led_power;
		led-failsafe = &led_power;
		led-running = &led_power;
		led-upgrade = &led_power;
	};

	chosen {
		bootargs = "console=ttyS0,115200";
	};

	gpio-leds {
		compatible = "gpio-leds";

		lan {
			label = "c20-v1:blue:lan";
			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
		};

		led_power: power {
			label = "c20-v1:blue:power";
			gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
			default-state = "keep";
		};

		usb {
			label = "c20-v1:blue:usb";
			gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
			trigger-sources = <&ohci_port1>, <&ehci_port1>;
			linux,default-trigger = "usbport";
		};

		wan {
			label = "c20-v1:blue:wan";
			gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
		};

		wan_orange {
			label = "c20-v1:orange:wan";
			gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
		};

		wlan5g {
			label = "c20-v1:blue:wlan5g";
			gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
		};

		wlan2g {
			label = "c20-v1:blue:wlan2g";
			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
		};

		wps {
			label = "c20-v1:blue:wps";
			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
		};
	};

	gpio-keys-polled {
		compatible = "gpio-keys-polled";
		poll-interval = <20>;

		reset {
			label = "reset";
			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RESTART>;
		};

		rfkill {
			label = "rfkill";
			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
			linux,code = <KEY_RFKILL>;
		};
	};
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&gpio3 {
	status = "okay";
};

&spi0 {
	status = "okay";

	m25p80@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x20000>;
				read-only;
			};

			partition@20000 {
				label = "firmware";
				reg = <0x20000 0x7a0000>;
			};

			partition@7c0000 {
				label = "config";
				reg = <0x7c0000 0x10000>;
				read-only;
			};

			rom: partition@7d0000 {
				label = "rom";
				reg = <0x7d0000 0x10000>;
				read-only;
			};

			partition@7e0000 {
				label = "romfile";
				reg = <0x7e0000 0x10000>;
				read-only;
			};

			radio: partition@7f0000 {
				label = "radio";
				reg = <0x7f0000 0x10000>;
				read-only;
			};
		};
	};
};

&pinctrl {
	state_default: pinctrl0 {
		gpio {
			ralink,group = "i2c", "uartf", "wled", "ephy", "spi refclk", "wdt";
			ralink,function = "gpio";
		};
	};
};

&ethernet {
		pinctrl-names = "default";
		mtd-mac-address = <&rom 0xf100>;
		mediatek,portmap = "wllll";
	};

&ehci {
	status = "okay";
};

&ohci {
	status = "okay";
};

&gsw {
	mediatek,port4 = "ephy";
};

&wmac {
	ralink,mtd-eeprom = <&radio 0>;
	mtd-mac-address = <&rom 0xf100>;
	mtd-mac-address-increment = <(-2)>;
	pinctrl-names = "default";
	pinctrl-0 = <&pa_pins>;
};

&pcie {
	status = "okay";
};

&pcie0 {
	mt76@0,0 {
		reg = <0x0000 0 0 0 0>;
		mediatek,mtd-eeprom = <&radio 0x8000>;
		ieee80211-freq-limit = <5000000 6000000>;
		mtd-mac-address = <&rom 0xf100>;
		mtd-mac-address-increment = <(-1)>;
	};
};