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* ar71xx: fix qca956x ethernet initializationFelix Fietkau2016-03-071-3/+18
| | | | | | | | | Complete internal switch initialization for QCA956X. Set default mdio device if the interface mode of GE0 is not SGMII (fix ticket #21520). Signed-off-by: Weijie Gao <hackpascal@gmail.com> SVN-Revision: 48937
* ar71xx: fix MDIO bus probe on QCA956xFelix Fietkau2016-02-071-1/+2
| | | | | | Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 48651
* ar71xx: fold patch 622-MIPS-ath79-add-support-for-QCA956x-ethernet.patch ↵Felix Fietkau2016-02-071-11/+56
| | | | | | | | into files/ Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 48650
* ath79: dev-eth: fix QCA9561 set phy interface mode and maskJohn Crispin2015-09-161-2/+7
| | | | | | | | | | QCA9563 and QCA9561 are two series of Qualcomm SoC Dragonfly. The only different is QCA9563 w/o internal switch. It has one GMAC with SGMII interface. But they have the same device ID(0x1150). So they share the same codes. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> SVN-Revision: 46971
* ar71xx: rework patch for qca953x/956xFelix Fietkau2015-07-071-2/+16
| | | | | | | | | | | | | | | | | | | Patch cherry-picked from the following location: https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e Changelist, - add more register defines - add EHCI support - fix GPIO pin count to 18 - fix chained irq disabled - fix GMAC0/GMAC1 initial - fix WMAC irq number to 47 - merge the changes of dev-eth.c from the patch to file. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> SVN-Revision: 46207
* ar71xx: add a helper function to set RXDV/RXD of ETH_CFG on AR934xFelix Fietkau2015-04-201-0/+26
| | | | | | | | | | | | | | | The ETH_RXDV_DELAY (17:16) and ETH_RXD_DELAY (15:14) are currently not cleared by the function ath79_setup_ar934x_eth_cfg. Clearing these in the ath79_setup_ar934x_eth_cfg may cause problems on some hardware because they rely on the preset value by the bootloader. Instead another function is introduced which also works on ETH_CFG on AR934x. It can be used to safely clear and set ETH_RXDV_DELAY and ETH_RXD_DELAY on machines which require special settings. Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 45523
* ar71xx: dev-eth: replace mdelay callsJohn Crispin2014-12-071-2/+2
| | | | | | | | Similar to patch 2. Replace further mdelay calls. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> SVN-Revision: 43540
* ath79: dev-eth: Don't advertise 1gbit in link code word on ar9331Felix Fietkau2014-09-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | While the AR9331 has a gigabit MAC towards the internal switch, the integrated PHYs however are only 100-base-tx capable. The existing code however advertieses gigabit capability in the link status word. If you attach such a PHY to a gigabit capable switch on the remote end, with some probability it attempts to negotiate gigabit and fails, falling baco to the AR9331 assuming a 10mbit half-duplex link. This has been observed quite frequently with the Carambola2 and gigabit capable switches. In ath79_register_eth(), "pdata->has_gbit = 1;" is set unconditionally for both AR9331 ethernet ports. This is most likely wrong. Despite the two MAC IP cores being gigabit MACs, the MAC for eth1 is connected to a 100base-T PHY via MII. The has_gbit attribute is used in the ethernet driver to determine the supported link modes. So either pdata->has_gbit is not set to 1 anymore, or the ethernet driver needs to be modified to determine the advertised link code word on another criteria than pdata->has_gbit. This patch implements the former solution. Signed-off-by: Harald Welte <laforge@gnumonks.org> SVN-Revision: 42432
* ar71xx: add a helper function for setting up ETH_CFG register on QCA955xGabor Juhos2014-07-131-0/+18
| | | | | | | | | Signed-off-by: Jon Suphammer <jon@suphammer.net> Patchwork: http://patchwork.openwrt.org/patch/5839/ [juhosg: fix coding style] Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 41623
* ar71xx: add support for QCA953x SoCFelix Fietkau2014-04-071-0/+40
| | | | | | | | | | | | | | | | | I don't have access to the specs, so I'm not sure about every detail, but I haven't seen any problems with my test system, a TL-WR841N v9. It looks pretty much like a QCA955x without PCI, a little twist in the clock calculation and a AR9331-compatible switch. Features not yet supported: * EHCI (my test system doesn't have USB) * ? (I have no idea if the QCA953x has any other features I don't know about that aren't used by the TL-WR841N v9) Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> SVN-Revision: 40399
* ar71xx: fix max frame length of the QCA955x SoCsGabor Juhos2013-12-231-0/+11
| | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 39161
* ar71xx: don't set builtin_switch flag for QCA9558Gabor Juhos2013-12-231-6/+1
| | | | | | | | It makes no sense, the SoC has no built-in switch. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 39160
* ar71xx: allow to use large ethernet frames on AR934x SoCsGabor Juhos2013-12-201-0/+4
| | | | | | | | | | | | | | | The hardware supports large ethernet frames. Override the maximum frame length and packet lenght mask in the platform data to allow to use large MTU on the ethernet interfaces. Limit the feature to AR934x SoCs for now. It should work on some other SoCs as well, but those has not been tested yet. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 39149
* ar71xx: ag71xx: get max_frame_len and desc_pktlen_mask from platform dataGabor Juhos2013-12-201-0/+3
| | | | | | | | This will allow to use SoC specific values for both. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 39145
* ar71xx: make ag71xx_mdio_platform_data visibleGabor Juhos2013-12-171-2/+2
| | | | | | | | | | | This enables us to modify the ag71xx_mdio_platform_data from within the board support files. Signed-off-by: Felix Kaechele <heffer@fedoraproject.org> Patchwork: http://patchwork.openwrt.org/patch/4613/ Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 39126
* ar71xx: rename ath79_parse_mac_addr to ath79_parse_ascii_macGabor Juhos2013-09-201-11/+18
| | | | | | | | | Rename the function and extend it in order to make it usable from board setup code. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 38085
* ar71xx: use backported QCA955x patchesGabor Juhos2013-03-041-4/+4
| | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 35878
* ar71xx: fix ethernet device registration for the QCA9556 SoCGabor Juhos2013-01-291-0/+12
| | | | | | | | | Based on http://patchwork.openwrt.org/patch/3162/ Signed-off-by: Embedded Wireless GmbH <info at embeddedwireless.de> Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 35394
* ar71xx: fix ethernet device registration for QCA9558Gabor Juhos2012-12-221-1/+43
| | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34853
* ar71xx: fixup allowed PHY interface types for QCA9558Gabor Juhos2012-12-221-2/+23
| | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34851
* ar71xx: don't assign any MII bus device on QCA9558 by defaultGabor Juhos2012-12-221-1/+4
| | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 34850
* ar71xx: add a helper function for setting up ETH_CFG register on AR934xGabor Juhos2012-10-171-0/+24
| | | | | | Signed-off-by: Gabor Juhos <juhosg@openwrt.org> SVN-Revision: 33817
* ar71xx: avoid possible NULL pointer dereference in ath79_init_{,local}_macGabor Juhos2012-09-271-2/+8
| | | | SVN-Revision: 33575
* ar71xx: use dynamic clock dividers on the 2nd MDIO of AR934xGabor Juhos2012-09-091-0/+33
| | | | SVN-Revision: 33343
* Revert "ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240"Gabor Juhos2012-08-291-8/+1
| | | | | | That was based on assumptions. SVN-Revision: 33310
* ar71xx: only allow RGMII mode on the 2nd ethernet MAC of the AR7240Gabor Juhos2012-08-271-1/+8
| | | | | | Signed-off-by: Daniel Golle <dgolle@allnet.de> SVN-Revision: 33280
* ar71xx: add initial support for the QCA955X SoCsGabor Juhos2012-07-051-1/+9
| | | | SVN-Revision: 32606
* ar71xx: add a helper function for setting up PHY4 swapping on ar933xFelix Fietkau2012-06-061-0/+18
| | | | SVN-Revision: 32092
* ar71xx: fix MII clock settings for various chips, improves ethernet ↵Felix Fietkau2012-05-271-2/+10
| | | | | | stability on AR934x SVN-Revision: 31925
* ar71xx: allow to disable link polling on unused PHYsGabor Juhos2012-04-291-0/+4
| | | | SVN-Revision: 31533
* ar71xx: add AR934x specific interface speed setup for ge0Gabor Juhos2012-03-191-4/+9
| | | | SVN-Revision: 31017
* ar71xx: reset the switch on AR934x before ethernet device registrationGabor Juhos2012-03-131-0/+4
| | | | SVN-Revision: 30922
* ar71xx: use a dummy callback for interfaces with fixed speedGabor Juhos2012-03-121-28/+7
| | | | SVN-Revision: 30913
* ar71xx: merge ar934x_bo_ddr_flush patchGabor Juhos2012-03-121-12/+5
| | | | SVN-Revision: 30912
* ar71xx: merge files-3.2 to filesGabor Juhos2012-02-101-0/+971
SVN-Revision: 30405
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