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* netfilter: package required kmods for nftablesJo-Philipp Wich2020-01-141-13/+15
* netfilter: add back nft_hashDavid Bauer2020-01-121-0/+1
* kernel: remove obsolete kernel version switchesAdrian Schmutzler2020-01-121-14/+12
* netfilter: fix NAT packaging with kernels 5.2+Rafał Miłecki2019-10-281-1/+2
* netfilter: Add fib support for nftablesBrett Mastbergen2018-12-161-0/+5
* kernel: netfilter: chain filters merged into nf_tables.koHauke Mehrtens2018-12-151-5/+5
* kernel: netfilter: Adapt merge ipv4/ipv6 masquerade codeHauke Mehrtens2018-12-151-2/+2
* kernel: netfilter: Add nf_conncount.koHauke Mehrtens2018-12-151-0/+1
* kernel: netfilter: Add nf_tproxy_ipv{4,6} and nf_socket_ipv{4,6}Hauke Mehrtens2018-12-151-0/+4
* kernel: netfilter: Add nf_defrag_ipv6.ko to NF_CONNTRACK on 4.19Hauke Mehrtens2018-12-151-1/+2
* Revert "netfilter: separate IPv6 relevant kernel modules from IPv4"Jo-Philipp Wich2018-08-061-9/+5
* netfilter: separate IPv6 relevant kernel modules from IPv4Rosy Song2018-08-061-5/+9
* netfilter: add bpf match supportAlin Nastac2018-06-261-0/+1
* iptables: split physdev match out as a separate packageMatthias Schiffer2018-04-091-1/+4
* netfilter: add a xt_FLOWOFFLOAD target for NAT/routing offload supportFelix Fietkau2018-02-211-0/+3
* iptables: Support building connlabel moduleKristian Evensen2018-02-131-0/+4
* netfilter: add packages for arp and bridge tables of nftablesMatthias Schiffer2018-01-311-2/+10
* netfilter: clean up dependencies of kernel modulesMatthias Schiffer2018-01-311-3/+5
* netfilter, iptables: add optional CHECKSUM moduleDenis Osvald2017-11-061-0/+4
* iptables: Fix target TRACE issueMartin Wetterwald2017-10-271-1/+0
* netfilter: add iptables-mod-rpfilter packageAlin Nastac2017-07-111-0/+2
* netfilter.mk: prepare for linux 4.9 supportFelix Fietkau2017-01-271-2/+6
* kernel: netfilter: split out iptable_raw into a separate packageFelix Fietkau2016-12-141-2/+0
* netfilter: drop proprietary xt_id matchJo-Philipp Wich2016-12-141-2/+1
* netfilter: fix file conflicts between kmod-ipt- and kmod-nft- packagesMatthias Schiffer2016-09-301-8/+5
* include/netfilter.mk: fix kmod-ipt-tee build with 4.3/4.4Felix Fietkau2015-12-131-0/+2
* netfilter.mk: fix redirect module locations for 3.19+Jonas Gorski2015-06-221-3/+3
* netfilter.mk: remove obsolete ip_nat_ftp related lineFelix Fietkau2015-04-201-1/+0
* netfilter.mk: move IRC conntrack/nat helpers to kmod-nf-nathelper-extraFelix Fietkau2015-04-201-2/+2
* kernel: finally remove layer7 filter supportFelix Fietkau2015-04-131-1/+0
* netfilter.mk: remove bogus NAT related kernel module entries (#19451)Felix Fietkau2015-04-111-3/+0
* netfilter.mk: drop obsolete kernel version dependenciesFelix Fietkau2015-04-111-36/+36
* include: remove trailing whitespacesLuka Perkov2015-03-291-2/+2
* netfilter: add missing module/symbolFelix Fietkau2015-03-291-0/+1
* netfilter: clean up compatibility code for old kernelsFelix Fietkau2015-03-201-32/+16
* netfilter: fix nf_nat_redirect dependencies for 3.19 and 4.0John Crispin2015-03-051-0/+1
* include: netfilter: fix packaging of LOG target for Linux >= 3.16 (#19031)Jo-Philipp Wich2015-02-181-0/+3
* netfilter: add missing symbols and modules for Linux 3.18+Jo-Philipp Wich2015-01-291-1/+7
* generic: add preliminary 3.19 supportImre Kaloz2015-01-251-0/+2
* netfilter: handle NFT_MASQ_IPV6Imre Kaloz2015-01-141-0/+1
* netfilter: handle nft_masq and nft_masq_ipv4Imre Kaloz2015-01-121-0/+2
* kernel: add a patch to make netfilter conntrack cache routing informationFelix Fietkau2014-12-091-0/+1
* keernel: Fixed dependencies in netfilter modules introduced with 3.18 kernelJohn Crispin2014-11-191-0/+3
* kernel: 3.18: Fix kmod-ipt-natSteven Barth2014-11-081-0/+2
* netfilter: Enable compiling iptables match clusterFelix Fietkau2014-11-031-0/+7
* netfilter: unbreak kmod-ipt-nat for <3.7Steven Barth2014-09-291-0/+1
* netfilter: fix a typo in TTL-match moduleSteven Barth2014-09-181-1/+1
* netfilter: remove redundant CONFIG_IP_NF_IPTABLESSteven Barth2014-09-171-1/+0
* Reorganize netfilter kernel modules and package nftables kernel supportSteven Barth2014-09-171-40/+75
* iptables: NFLOG and NFQUEUE targets' full supportSteven Barth2014-08-071-0/+27
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 01:16:51 +0000
;< 10) /* PM1_CNT */ #define SCI_EN (1 << 0) #define GBL_RLS (1 << 2) #define SLP_EN (1 << 13) typedef struct AcpiDeviceState AcpiDeviceState; AcpiDeviceState *acpi_device_table; /* Bits of PM1a register define here */ typedef struct PM1Event_BLK { uint16_t pm1_status; /* pm1a_EVT_BLK */ uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */ }PM1Event_BLK; typedef struct PCIAcpiState { PCIDevice dev; uint16_t irq; uint16_t pm1_status; /* pm1a_EVT_BLK */ uint16_t pm1_enable; /* pm1a_EVT_BLK+2 */ uint16_t pm1_control; /* pm1a_ECNT_BLK */ uint32_t pm1_timer; /* pmtmr_BLK */ } PCIAcpiState; static PCIAcpiState *acpi_state; static inline void acpi_set_irq(PCIAcpiState *s) { /* no real SCI event need for now, so comment the following line out */ /* pic_set_irq(s->irq, 1); */ printf("acpi_set_irq: s->irq %x \n",s->irq); } static void acpi_reset(PCIAcpiState *s) { uint8_t *pci_conf; pci_conf = s->dev.config; pci_conf[0x42] = 0x00; pci_conf[0x43] = 0x00; s->irq = 9; s->pm1_status = 0; s->pm1_enable = 0x00; /*TMROF_EN should cleared */ s->pm1_control = SCI_EN;/*SCI_EN */ s->pm1_timer = 0; } /*byte access */ static void acpiPm1Status_writeb(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; if ((val&TMROF_STS)==TMROF_STS) s->pm1_status = s->pm1_status&!TMROF_STS; if ((val&GBL_STS)==GBL_STS) s->pm1_status = s->pm1_status&!GBL_STS; /* printf("acpiPm1Status_writeb \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */ } static uint32_t acpiPm1Status_readb(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = s->pm1_status; /* printf("acpiPm1Status_readb \n addr %x val:%x\n", addr, val); */ return val; } static void acpiPm1StatusP1_writeb(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_status = (val<<8)||(s->pm1_status); /* printf("acpiPm1StatusP1_writeb \n addr %x val:%x\n", addr, val); */ } static uint32_t acpiPm1StatusP1_readb(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = (s->pm1_status)>>8; printf("acpiPm1StatusP1_readb \n addr %x val:%x\n", addr, val); return val; } static void acpiPm1Enable_writeb(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_enable = val; /* printf("acpiPm1Enable_writeb \n addr %x val:%x\n", addr, val); */ } static uint32_t acpiPm1Enable_readb(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = (s->pm1_enable)||0x1; /* printf("acpiPm1Enable_readb \n addr %x val:%x\n", addr, val); */ return val; } static void acpiPm1EnableP1_writeb(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_enable = (val<<8)||(s->pm1_enable); /* printf("acpiPm1EnableP1_writeb \n addr %x val:%x\n", addr, val); */ } static uint32_t acpiPm1EnableP1_readb(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = (s->pm1_enable)>>8; /* printf("acpiPm1EnableP1_readb \n addr %x val:%x\n", addr, val); */ return val; } static void acpiPm1Control_writeb(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_control = val; /* printf("acpiPm1Control_writeb \n addr %x val:%x\n", addr, val); */ } static uint32_t acpiPm1Control_readb(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = s->pm1_control; /* printf("acpiPm1Control_readb \n addr %x val:%x\n", addr, val); */ return val; } static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_control = (val<<8)||(s->pm1_control); /* printf("acpiPm1ControlP1_writeb \n addr %x val:%x\n", addr, val); */ } static uint32_t acpiPm1ControlP1_readb(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = (s->pm1_control)>>8; /* printf("acpiPm1ControlP1_readb \n addr %x val:%x\n", addr, val); */ return val; } /* word access */ static void acpiPm1Status_writew(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; if ((val&TMROF_STS)==TMROF_STS) s->pm1_status = s->pm1_status&!TMROF_STS; if ((val&GBL_STS)==GBL_STS) s->pm1_status = s->pm1_status&!GBL_STS; /* printf("acpiPm1Status_writew \n addr %x val:%x pm1_status:%x \n", addr, val,s->pm1_status); */ } static uint32_t acpiPm1Status_readw(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = s->pm1_status; /* printf("acpiPm1Status_readw \n addr %x val:%x\n", addr, val); */ return val; } static void acpiPm1Enable_writew(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_enable = val; /* printf("acpiPm1Enable_writew \n addr %x val:%x\n", addr, val); */ } static uint32_t acpiPm1Enable_readw(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = s->pm1_enable; /* printf("acpiPm1Enable_readw \n addr %x val:%x\n", addr, val); */ return val; } static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_control = val; /* printf("acpiPm1Control_writew \n addr %x val:%x\n", addr, val); */ } static uint32_t acpiPm1Control_readw(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = s->pm1_control; /* printf("acpiPm1Control_readw \n addr %x val:%x\n", addr, val); */ return val; } /* dword access */ static void acpiPm1Event_writel(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_status = val; s->pm1_enable = val>>16; /* printf("acpiPm1Event_writel \n addr %x val:%x \n", addr, val); */ } static void acpiPm1Event_readl(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val=s->pm1_status|(s->pm1_enable<<16); /* printf("acpiPm1Event_readl \n addr %x val:%x\n", addr, val); */ } static void acpiPm1Timer_writel(void *opaque, uint32_t addr, uint32_t val) { PCIAcpiState *s = opaque; s->pm1_timer = val; /* printf("acpiPm1Timer_writel \n addr %x val:%x\n", addr, val); */ } static uint32_t acpiPm1Timer_readl(void *opaque, uint32_t addr) { PCIAcpiState *s = opaque; uint32_t val; val = s->pm1_timer; /* printf("acpiPm1Timer_readl \n addr %x val:%x\n", addr, val); */ return val; } static void acpi_map(PCIDevice *pci_dev, int region_num, uint32_t addr, uint32_t size, int type) { PCIAcpiState *d = (PCIAcpiState *)pci_dev; printf("register acpi io \n "); /*Byte access */ register_ioport_write(addr, 1, 1, acpiPm1Status_writeb, d); register_ioport_read(addr, 1, 1, acpiPm1Status_readb, d); register_ioport_write(addr+1, 1, 1, acpiPm1StatusP1_writeb, d); register_ioport_read(addr+1, 1, 1, acpiPm1StatusP1_readb, d); register_ioport_write(addr + 2, 1, 1, acpiPm1Enable_writeb, d); register_ioport_read(addr + 2, 1, 1, acpiPm1Enable_readb, d); register_ioport_write(addr + 2 +1, 1, 1, acpiPm1EnableP1_writeb, d); register_ioport_read(addr + 2 +1, 1, 1, acpiPm1EnableP1_readb, d); register_ioport_write(addr + 4, 1, 1, acpiPm1Control_writeb, d); register_ioport_read(addr + 4, 1, 1, acpiPm1Control_readb, d); register_ioport_write(addr + 4 + 1, 1, 1, acpiPm1ControlP1_writeb, d); register_ioport_read(addr + 4 +1, 1, 1, acpiPm1ControlP1_readb, d); /* word access */ register_ioport_write(addr, 2, 2, acpiPm1Status_writew, d); register_ioport_read(addr, 2, 2, acpiPm1Status_readw, d); register_ioport_write(addr + 2, 2, 2, acpiPm1Enable_writew, d); register_ioport_read(addr + 2, 2, 2, acpiPm1Enable_readw, d); register_ioport_write(addr + 4, 2, 2, acpiPm1Control_writew, d); register_ioport_read(addr + 4, 2, 2, acpiPm1Control_readw, d); /* dword access */ register_ioport_write(addr, 4, 4, acpiPm1Event_writel, d); register_ioport_read(addr, 4, 4, acpiPm1Event_readl, d); register_ioport_write(addr + 8, 4, 4, acpiPm1Timer_writel, d); register_ioport_read(addr + 8, 4, 4, acpiPm1Timer_readl, d); } /* PIIX4 acpi pci configuration space, func 3 */ void pci_piix4_acpi_init(PCIBus *bus) { PCIAcpiState *d;//,*s; uint8_t *pci_conf;//,*pci_conf_usb; /* register a function 3 of PIIX4 */ d = (PCIAcpiState *)pci_register_device(bus, "PIIX4 ACPI", sizeof(PCIAcpiState), ((PCIDevice *)piix3_state)->devfn + 3, NULL, NULL); acpi_state = d; pci_conf = d->dev.config; pci_conf[0x00] = 0x86; // Intel pci_conf[0x01] = 0x80; pci_conf[0x02] = 0x13; pci_conf[0x03] = 0x71; pci_conf[0x08] = 0x01; //B0 stepping pci_conf[0x09] = 0x00; //base class pci_conf[0x0a] = 0x80; //Sub class pci_conf[0x0b] = 0x06; pci_conf[0x0e] = 0x00; pci_conf[0x3d] = 0x01; // Hardwired to PIRQA is used pci_register_io_region((PCIDevice *)d, 4, 0x10, PCI_ADDRESS_SPACE_IO, acpi_map); acpi_reset (d); }
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-19 01:16:50 +0000