| Commit message (Collapse) | Author | Age | Files | Lines |
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from interfaces
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45483
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45482
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45481
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45480
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Signed-off-by: Steven Barth <steven@midlink.org>
SVN-Revision: 45479
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Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 45478
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Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 45477
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Signed-off-by: Steven Barth <steven@midlink.org>
SVN-Revision: 45476
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45475
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45474
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45473
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45472
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45471
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45470
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The mips74k subtarget of brcm47xx configures gcc to compile for mips32r2;
however, the generated kernel config for 3.14 and later kernels ends up
with CPU_MIPS32_R1 and CPU_MIPSR1 selected. The generated kernel config
for the 3.10 kernel (Barrier Breaker) properly selected CPU_MIPS32_R2 and
CPU_MIPSR2. Modify the default kernel config for mips74k to explicitly
select CPU_MIPS32_R2 and CPU_MIPSR2.
Signed-off-by: Nathan Hintz <nlhintz@hotmail.com>
Tested-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45469
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45468
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45467
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45466
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45465
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45464
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Depending on configuration, disable the LED before writing the trigger
and enable it after writing it. Fixes LEDs where the value defaults to 1
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45463
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device-tree
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45462
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45461
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45460
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Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 45459
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45458
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45457
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Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
SVN-Revision: 45456
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Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 45455
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Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 45454
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Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 45453
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Signed-off-by: Luka Perkov <luka@openwrt.org>
SVN-Revision: 45452
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45451
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45450
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Signed-off-by: Steven Barth <steven@midlink.org>
SVN-Revision: 45449
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Signed-off-by: Steven Barth <steven@midlink.org>
SVN-Revision: 45448
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45447
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redirect/disconnect after headers
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45446
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45445
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45444
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This will allow adding more modes without options conflict.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45443
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adds support for reading md5 sums of files
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 45442
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fixes long writes when using polarssl
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 45441
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fixes issues with semi-initialized overlay partitions during firstboot
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 45440
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Open-Mesh OM5P-AN use a AT8035 (F1E) behind one of the ethernet ports. This PHY
requires special flags to work correctly. Otherwise massive packet loss happens
with active POE or when switching the link speed from gigabit ethernet to fast
ethernet. The generic PHY doesn't have support to change these settings.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45439
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The OM5P-AN boards are suffering from ethernet packet loss when booting with
some active POE setups or when switching to Fast Ethernet when previously
booted with Gigabit ethernet attached.
The cause of the problem is that the AR8035 PHYs requires special register
settings to work reliably on these boards. Enable the RGMII TX, RX delays and
disable SmartEE functionality of the AR8035 PHYs. Also enable the RXD and RDV
delay in the ETH_CFG register to fix the issue.
Signed-off-by: Sven Eckelmann <sven@open-mesh.com>
SVN-Revision: 45438
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Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 45437
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Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
SVN-Revision: 45436
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Signed-off-by: Steven Barth <steven@midlink.org>
SVN-Revision: 45435
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Signed-off-by: Felix Fietkau <nbd@openwrt.org>
SVN-Revision: 45434
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