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-rw-r--r--target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c119
1 files changed, 57 insertions, 62 deletions
diff --git a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
index 2a34e9417d..4b030f457b 100644
--- a/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
+++ b/target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c
@@ -98,12 +98,8 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
if (mdio_mode) {
- u32 val;
-
- /* turn off ephy and set phy base addr to 12 */
- mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
- (0x1f << 24) | (0xc << 16),
- GSW_REG_GPC1);
+ if (!gsw->ephy_base)
+ gsw->ephy_base = 12;
/* set MT7530 central align */
val = mt7530_mdio_r32(gsw, 0x7830);
@@ -116,64 +112,63 @@ static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
mt7530_mdio_w32(gsw, 0x7a40, val);
mt7530_mdio_w32(gsw, 0x7a78, 0x855);
- } else {
+ }
- if (gsw->ephy_base) {
- /* set phy base addr to ephy_base */
- mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
- (gsw->ephy_base << 16),
- GSW_REG_GPC1);
- fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
- }
+ if (gsw->ephy_base) {
+ /* set phy base addr to ephy_base */
+ mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
+ (gsw->ephy_base << 16),
+ GSW_REG_GPC1);
+ fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
+ }
- /* global page 4 */
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
-
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
- if (is_BGA)
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
- else
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
-
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
-
- /* global page 3 */
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
-
- /* global page 2 */
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
- if (is_BGA) {
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
- } else {
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
- }
- /* global page 1 */
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
- _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
-
- /* turn on all PHYs */
- for (i = 0; i <= 4; i++) {
- val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
- val &= ~BMCR_PDOWN;
- val |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;
- _mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
- }
+ /* global page 4 */
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
+
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
+ if (is_BGA)
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
+ else
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
+
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
+
+ /* global page 3 */
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
+
+ /* global page 2 */
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
+ if (is_BGA) {
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
+ } else {
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
+ }
+ /* global page 1 */
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
+ _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
+
+ /* turn on all PHYs */
+ for (i = 0; i <= 4; i++) {
+ val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
+ val &= ~BMCR_PDOWN;
+ val |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;
+ _mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
}
/* global page 0 */
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 13:47:28 +0000