diff options
Diffstat (limited to 'target')
7 files changed, 757 insertions, 2 deletions
diff --git a/target/linux/ramips/base-files/etc/uci-defaults/network b/target/linux/ramips/base-files/etc/uci-defaults/network new file mode 100755 index 0000000000..8d4c6d547d --- /dev/null +++ b/target/linux/ramips/base-files/etc/uci-defaults/network @@ -0,0 +1,13 @@ +#!/bin/sh +RT305X=`cat /proc/cpuinfo | grep RT305` +[ -z "${RT305X}" ] || { + uci batch <<EOF +set network.lan.ifname=eth0.1 +set network.wan=interface +set network.wan.ifname=eth0.2 +set network.wan.proto=dhcp +commit network +EOF +} + +uci commit network diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/eth.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/eth.h new file mode 100644 index 0000000000..d468967884 --- /dev/null +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/eth.h @@ -0,0 +1,204 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * based on Ralink SDK3.3 + * Copyright (C) 2009 John Crispin <blogic@openwrt.org> + */ + +#ifndef RAMIPS_ETH_H +#define RAMIPS_ETH_H + +#include <linux/mii.h> + +#define NUM_RX_DESC 256 +#define NUM_TX_DESC 256 + +#define RAMIPS_DELAY_EN_INT 0x80 +#define RAMIPS_DELAY_MAX_INT 0x04 +#define RAMIPS_DELAY_MAX_TOUT 0x04 +#define RAMIPS_DELAY_CHAN (((RAMIPS_DELAY_EN_INT | RAMIPS_DELAY_MAX_INT) << 8) | RAMIPS_DELAY_MAX_TOUT) +#define RAMIPS_DELAY_INIT ((RAMIPS_DELAY_CHAN << 16) | RAMIPS_DELAY_CHAN) +#define RAMIPS_PSE_FQFC_CFG_INIT 0x80504000 + +#define RAMIPS_FE_RESET 0x34 +#define RAMIPS_FE_RESET_BIT BIT(21) + + +/* interrupt bitd */ +#define RAMIPS_CNT_PPE_AF BIT(31) +#define RAMIPS_CNT_GDM_AF BIT(29) +#define RAMIPS_PSE_P2_FC BIT(26) +#define RAMIPS_PSE_BUF_DROP BIT(24) +#define RAMIPS_GDM_OTHER_DROP BIT(23) +#define RAMIPS_PSE_P1_FC BIT(22) +#define RAMIPS_PSE_P0_FC BIT(21) +#define RAMIPS_PSE_FQ_EMPTY BIT(20) +#define RAMIPS_GE1_STA_CHG BIT(18) +#define RAMIPS_TX_COHERENT BIT(17) +#define RAMIPS_RX_COHERENT BIT(16) +#define RAMIPS_TX_DONE_INT3 BIT(11) +#define RAMIPS_TX_DONE_INT2 BIT(10) +#define RAMIPS_TX_DONE_INT1 BIT(9) +#define RAMIPS_TX_DONE_INT0 BIT(8) +#define RAMIPS_RX_DONE_INT0 BIT(2) +#define RAMIPS_TX_DLY_INT BIT(1) +#define RAMIPS_RX_DLY_INT BIT(0) + +/* registers */ +#define RAMIPS_FE_OFFSET 0x0000 +#define RAMIPS_GDMA_OFFSET 0x0020 +#define RAMIPS_PSE_OFFSET 0x0040 +#define RAMIPS_GDMA2_OFFSET 0x0060 +#define RAMIPS_CDMA_OFFSET 0x0080 +#define RAMIPS_PDMA_OFFSET 0x0100 +#define RAMIPS_PPE_OFFSET 0x0200 +#define RAMIPS_CMTABLE_OFFSET 0x0400 +#define RAMIPS_POLICYTABLE_OFFSET 0x1000 + +#define RAMIPS_MDIO_ACCESS (RAMIPS_FE_OFFSET + 0x00) +#define RAMIPS_MDIO_CFG (RAMIPS_FE_OFFSET + 0x04) +#define RAMIPS_FE_GLO_CFG (RAMIPS_FE_OFFSET + 0x08) +#define RAMIPS_FE_RST_GL (RAMIPS_FE_OFFSET + 0x0C) +#define RAMIPS_FE_INT_STATUS (RAMIPS_FE_OFFSET + 0x10) +#define RAMIPS_FE_INT_ENABLE (RAMIPS_FE_OFFSET + 0x14) +#define RAMIPS_MDIO_CFG2 (RAMIPS_FE_OFFSET + 0x18) +#define RAMIPS_FOC_TS_T (RAMIPS_FE_OFFSET + 0x1C) + +#define RAMIPS_GDMA1_FWD_CFG (RAMIPS_GDMA_OFFSET + 0x00) +#define RAMIPS_GDMA1_SCH_CFG (RAMIPS_GDMA_OFFSET + 0x04) +#define RAMIPS_GDMA1_SHPR_CFG (RAMIPS_GDMA_OFFSET + 0x08) +#define RAMIPS_GDMA1_MAC_ADRL (RAMIPS_GDMA_OFFSET + 0x0C) +#define RAMIPS_GDMA1_MAC_ADRH (RAMIPS_GDMA_OFFSET + 0x10) + +#define RAMIPS_GDMA2_FWD_CFG (RAMIPS_GDMA2_OFFSET + 0x00) +#define RAMIPS_GDMA2_SCH_CFG (RAMIPS_GDMA2_OFFSET + 0x04) +#define RAMIPS_GDMA2_SHPR_CFG (RAMIPS_GDMA2_OFFSET + 0x08) +#define RAMIPS_GDMA2_MAC_ADRL (RAMIPS_GDMA2_OFFSET + 0x0C) +#define RAMIPS_GDMA2_MAC_ADRH (RAMIPS_GDMA2_OFFSET + 0x10) + +#define RAMIPS_PSE_FQ_CFG (RAMIPS_PSE_OFFSET + 0x00) +#define RAMIPS_CDMA_FC_CFG (RAMIPS_PSE_OFFSET + 0x04) +#define RAMIPS_GDMA1_FC_CFG (RAMIPS_PSE_OFFSET + 0x08) +#define RAMIPS_GDMA2_FC_CFG (RAMIPS_PSE_OFFSET + 0x0C) + +#define RAMIPS_CDMA_CSG_CFG (RAMIPS_CDMA_OFFSET + 0x00) +#define RAMIPS_CDMA_SCH_CFG (RAMIPS_CDMA_OFFSET + 0x04) + +#define RAMIPS_PDMA_GLO_CFG (RAMIPS_PDMA_OFFSET + 0x00) +#define RAMIPS_PDMA_RST_CFG (RAMIPS_PDMA_OFFSET + 0x04) +#define RAMIPS_PDMA_SCH_CFG (RAMIPS_PDMA_OFFSET + 0x08) +#define RAMIPS_DLY_INT_CFG (RAMIPS_PDMA_OFFSET + 0x0C) +#define RAMIPS_TX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x10) +#define RAMIPS_TX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x14) +#define RAMIPS_TX_CTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x18) +#define RAMIPS_TX_DTX_IDX0 (RAMIPS_PDMA_OFFSET + 0x1C) +#define RAMIPS_TX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x20) +#define RAMIPS_TX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x24) +#define RAMIPS_TX_CTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x28) +#define RAMIPS_TX_DTX_IDX1 (RAMIPS_PDMA_OFFSET + 0x2C) +#define RAMIPS_TX_BASE_PTR2 (RAMIPS_PDMA_OFFSET + 0x40) +#define RAMIPS_TX_MAX_CNT2 (RAMIPS_PDMA_OFFSET + 0x44) +#define RAMIPS_TX_CTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x48) +#define RAMIPS_TX_DTX_IDX2 (RAMIPS_PDMA_OFFSET + 0x4C) +#define RAMIPS_TX_BASE_PTR3 (RAMIPS_PDMA_OFFSET + 0x50) +#define RAMIPS_TX_MAX_CNT3 (RAMIPS_PDMA_OFFSET + 0x54) +#define RAMIPS_TX_CTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x58) +#define RAMIPS_TX_DTX_IDX3 (RAMIPS_PDMA_OFFSET + 0x5C) +#define RAMIPS_RX_BASE_PTR0 (RAMIPS_PDMA_OFFSET + 0x30) +#define RAMIPS_RX_MAX_CNT0 (RAMIPS_PDMA_OFFSET + 0x34) +#define RAMIPS_RX_CALC_IDX0 (RAMIPS_PDMA_OFFSET + 0x38) +#define RAMIPS_RX_DRX_IDX0 (RAMIPS_PDMA_OFFSET + 0x3C) +#define RAMIPS_RX_BASE_PTR1 (RAMIPS_PDMA_OFFSET + 0x40) +#define RAMIPS_RX_MAX_CNT1 (RAMIPS_PDMA_OFFSET + 0x44) +#define RAMIPS_RX_CALC_IDX1 (RAMIPS_PDMA_OFFSET + 0x48) +#define RAMIPS_RX_DRX_IDX1 (RAMIPS_PDMA_OFFSET + 0x4C) + +/* uni-cast port */ +#define RAMIPS_GDM1_ICS_EN (0x1 << 22) +#define RAMIPS_GDM1_TCS_EN (0x1 << 21) +#define RAMIPS_GDM1_UCS_EN (0x1 << 20) +#define RAMIPS_GDM1_JMB_EN (0x1 << 19) +#define RAMIPS_GDM1_STRPCRC (0x1 << 16) +#define RAMIPS_GDM1_UFRC_P_CPU (0 << 12) +#define RAMIPS_GDM1_UFRC_P_GDMA1 (1 << 12) +#define RAMIPS_GDM1_UFRC_P_PPE (6 << 12) + +/* checksums */ +#define RAMIPS_ICS_GEN_EN BIT(2) +#define RAMIPS_UCS_GEN_EN BIT(1) +#define RAMIPS_TCS_GEN_EN BIT(0) + +/* dma rimg */ +#define RAMIPS_PST_DRX_IDX0 BIT(16) +#define RAMIPS_PST_DTX_IDX3 BIT(3) +#define RAMIPS_PST_DTX_IDX2 BIT(2) +#define RAMIPS_PST_DTX_IDX1 BIT(1) +#define RAMIPS_PST_DTX_IDX0 BIT(0) + +#define RAMIPS_TX_WB_DDONE BIT(6) +#define RAMIPS_RX_DMA_BUSY BIT(3) +#define RAMIPS_TX_DMA_BUSY BIT(1) +#define RAMIPS_RX_DMA_EN BIT(2) +#define RAMIPS_TX_DMA_EN BIT(0) + +#define RAMIPS_PDMA_SIZE_4DWORDS (0<<4) +#define RAMIPS_PDMA_SIZE_8DWORDS (1<<4) +#define RAMIPS_PDMA_SIZE_16DWORDS (2<<4) + +#define RAMIPS_US_CYC_CNT_MASK 0xff +#define RAMIPS_US_CYC_CNT_SHIFT 0x8 +#define RAMIPS_US_CYC_CNT_DIVISOR 1000000 + + +#define RX_DMA_PLEN0(x) ((x >> 16) & 0x3fff) +#define RX_DMA_LSO BIT(30) +#define RX_DMA_DONE BIT(31) +struct ramips_rx_dma { + unsigned int rxd1; + unsigned int rxd2; + unsigned int rxd3; + unsigned int rxd4; +}; + +#define TX_DMA_PLEN0_MASK ((0x3fff) << 16) +#define TX_DMA_PLEN0(x) ((x & 0x3fff) << 16) +#define TX_DMA_LSO BIT(30) +#define TX_DMA_DONE BIT(31) +#define TX_DMA_QN(x) (x << 16) +#define TX_DMA_PN(x) (x << 24) +#define TX_DMA_QN_MASK TX_DMA_QN(0x7) +#define TX_DMA_PN_MASK TX_DMA_PN(0x7) +struct ramips_tx_dma { + unsigned int txd1; + unsigned int txd2; + unsigned int txd3; + unsigned int txd4; +}; + +struct raeth_priv +{ + unsigned int phy_rx; + struct tasklet_struct rx_tasklet; + struct ramips_rx_dma *rx; + + unsigned int phy_tx; + struct tasklet_struct tx_housekeeping_tasklet; + struct ramips_tx_dma *tx; + + unsigned int skb_free_idx; + struct net_device_stats stat; +}; + +#endif diff --git a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h index 7f0666d5b1..a17962d5aa 100644 --- a/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h +++ b/target/linux/ramips/files/arch/mips/include/asm/mach-ralink/rt305x_regs.h @@ -14,7 +14,7 @@ #include <linux/bitops.h> #define RT305X_SDRAM_BASE 0x00000000 -#define RT305X_SYSC_BASE 0x10000000 +#define RT305X_SYSC_BASE 0x10000000 #define RT305X_TIMER_BASE 0x10000100 #define RT305X_INTC_BASE 0x10000200 #define RT305X_MEMC_BASE 0x10000300 @@ -26,7 +26,7 @@ #define RT305X_I2S_BASE 0x10000a00 #define RT305X_SPI_BASE 0x10000b00 #define RT305X_UART1_BASE 0x10000c00 -#define RT305X_FE_BASE 0x10010000 +#define RT305X_FE_BASE 0x10100000 #define RT305X_SWITCH_BASE 0x10110000 #define RT305X_WMAC_BASE 0x00180000 #define RT305X_OTG_BASE 0x101c0000 @@ -35,6 +35,7 @@ #define RT305X_FLASH0_BASE 0x1f000000 #define RT305X_SYSC_SIZE 0x100 +#define RT305X_TIMER_SIZE 0x100 #define RT305X_INTC_SIZE 0x100 #define RT305X_MEMC_SIZE 0x100 #define RT305X_UART0_SIZE 0x100 diff --git a/target/linux/ramips/files/drivers/net/ramips.c b/target/linux/ramips/files/drivers/net/ramips.c new file mode 100644 index 0000000000..46def4051a --- /dev/null +++ b/target/linux/ramips/files/drivers/net/ramips.c @@ -0,0 +1,387 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. + * + * Copyright (C) 2009 John Crispin <blogic@openwrt.org> + */ + +#include <linux/module.h> +#include <linux/version.h> +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/pci.h> +#include <linux/init.h> +#include <linux/skbuff.h> +#include <linux/if_vlan.h> +#include <linux/if_ether.h> +#include <asm/uaccess.h> +#include <net/sock.h> +#include <asm/uaccess.h> + +#include <rt305x.h> +#include <rt305x_regs.h> +#include <eth.h> + +#define TX_TIMEOUT (20 * HZ / 100) +#define MAX_RX_LENGTH 1500 + +#ifdef CONFIG_RALINK_RT305X +#include "ramips_esw.c" +#endif + +static struct net_device * ramips_dev; +static void __iomem *ramips_fe_base = 0; + +static inline void +ramips_fe_wr(u32 val, unsigned reg) +{ + __raw_writel(val, ramips_fe_base + reg); +} + +static inline u32 +ramips_fe_rr(unsigned reg) +{ + return __raw_readl(ramips_fe_base + reg); +} + +static int +ramips_alloc_dma(struct net_device *dev) +{ +#define phys_to_bus(a) (a & 0x1FFFFFFF) + struct raeth_priv *priv = (struct raeth_priv*)netdev_priv(dev); + int i; + + priv->skb_free_idx = 0; + + /* setup tx ring */ + priv->tx = pci_alloc_consistent(NULL, + NUM_TX_DESC * sizeof(struct ramips_tx_dma), &priv->phy_tx); + for(i = 0; i < NUM_TX_DESC; i++) + { + memset(&priv->tx[i], 0, sizeof(struct ramips_tx_dma)); + priv->tx[i].txd2 |= TX_DMA_LSO | TX_DMA_DONE; + priv->tx[i].txd4 &= (TX_DMA_QN_MASK | TX_DMA_PN_MASK); + priv->tx[i].txd4 |= TX_DMA_QN(3) | TX_DMA_PN(1); + } + ramips_fe_wr(phys_to_bus(priv->phy_tx), RAMIPS_TX_BASE_PTR0); + ramips_fe_wr(NUM_TX_DESC, RAMIPS_TX_MAX_CNT0); + ramips_fe_wr(0, RAMIPS_TX_CTX_IDX0); + ramips_fe_wr(RAMIPS_PST_DTX_IDX0, RAMIPS_PDMA_RST_CFG); + + /* setup rx ring */ + priv->rx = pci_alloc_consistent(NULL, + NUM_RX_DESC * sizeof(struct ramips_rx_dma), &priv->phy_rx); + memset(priv->rx, 0, sizeof(struct ramips_rx_dma) * NUM_RX_DESC); + for(i = 0; i < NUM_RX_DESC; i++) + { + struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_LENGTH + 2); + BUG_ON(!new_skb); + skb_reserve(new_skb, 2); + priv->rx[i].rxd1 = + dma_map_single(NULL, skb_put(new_skb, 2), MAX_RX_LENGTH + 2, + PCI_DMA_FROMDEVICE); + priv->rx[i].rxd2 |= RX_DMA_LSO; + priv->rx[i].rxd3 = (unsigned int)new_skb; + } + dma_cache_wback_inv((unsigned long)priv->rx, + NUM_RX_DESC * (sizeof(struct ramips_rx_dma))); + + ramips_fe_wr(phys_to_bus(priv->phy_rx), RAMIPS_RX_BASE_PTR0); + ramips_fe_wr(NUM_RX_DESC, RAMIPS_RX_MAX_CNT0); + ramips_fe_wr((NUM_RX_DESC - 1), RAMIPS_RX_CALC_IDX0); + ramips_fe_wr(RAMIPS_PST_DRX_IDX0, RAMIPS_PDMA_RST_CFG); + + return 0; +} + +static int +ramips_eth_hard_start_xmit(struct sk_buff* skb, struct net_device *dev) +{ + struct raeth_priv *priv = (struct raeth_priv*)netdev_priv(dev); + unsigned long tx; + unsigned int tx_next; + +#ifdef CONFIG_RALINK_RT305X +#define MIN_PKT_LEN 64 + if(skb->len < MIN_PKT_LEN) + { + if(skb_padto(skb, MIN_PKT_LEN)) + { + printk(KERN_ERR "ramips_eth: skb_padto failed\n"); + kfree_skb(skb); + return 0; + } + skb_put(skb, MIN_PKT_LEN - skb->len); + } +#endif + dev->trans_start = jiffies; + dma_cache_wback_inv((unsigned long)skb->data, skb->len); + tx = ramips_fe_rr(RAMIPS_TX_CTX_IDX0); + if(tx == NUM_TX_DESC - 1) + tx_next = 0; + else + tx_next = tx + 1; + if((priv->tx[tx].txd3 == 0) && (priv->tx[tx_next].txd3 == 0)) + { + if(!(priv->tx[tx].txd2 & TX_DMA_DONE)) + { + kfree_skb(skb); + priv->stat.tx_dropped++; + printk(KERN_ERR "%s: dropping\n", dev->name); + return 0; + } + priv->tx[tx].txd1 = virt_to_phys(skb->data); + priv->tx[tx].txd2 &= ~(TX_DMA_PLEN0_MASK | TX_DMA_DONE); + priv->tx[tx].txd2 |= TX_DMA_PLEN0(skb->len); + ramips_fe_wr((tx + 1) % NUM_TX_DESC, RAMIPS_TX_CTX_IDX0); + priv->stat.tx_packets++; + priv->stat.tx_bytes += skb->len; + priv->tx[tx].txd3 = (unsigned int)skb; + ramips_fe_wr((tx + 1) % NUM_TX_DESC, RAMIPS_TX_CTX_IDX0); + } else { + priv->stat.tx_dropped++; + kfree_skb(skb); + } + return 0; +} + +static void +ramips_eth_rx_hw(unsigned long ptr) +{ + struct net_device *dev = (struct net_device*)ptr; + struct raeth_priv *priv = (struct raeth_priv*)netdev_priv(dev); + int rx; + int max_rx = 16; + + while(max_rx) + { + struct sk_buff *rx_skb, *new_skb; + + rx = (ramips_fe_rr(RAMIPS_RX_CALC_IDX0) + 1) % NUM_RX_DESC; + if(!(priv->rx[rx].rxd2 & RX_DMA_DONE)) + break; + max_rx--; + + rx_skb = (struct sk_buff*)priv->rx[rx].rxd3; + rx_skb->len = RX_DMA_PLEN0(priv->rx[rx].rxd2); + rx_skb->tail = rx_skb->data + rx_skb->len; + rx_skb->dev = dev; + rx_skb->protocol = eth_type_trans(rx_skb, dev); + rx_skb->ip_summed = CHECKSUM_NONE; + priv->stat.rx_packets++; + priv->stat.rx_bytes += rx_skb->len; + netif_rx(rx_skb); + + new_skb = __dev_alloc_skb(MAX_RX_LENGTH + 2, GFP_DMA | GFP_ATOMIC); + priv->rx[rx].rxd3 = (unsigned int)new_skb; + BUG_ON(!new_skb); + skb_reserve(new_skb, 2); + priv->rx[rx].rxd1 = + dma_map_single(NULL, new_skb->data, MAX_RX_LENGTH + 2, + PCI_DMA_FROMDEVICE); + priv->rx[rx].rxd2 &= ~RX_DMA_DONE; + dma_cache_wback_inv((unsigned long)&priv->rx[rx], + sizeof(struct ramips_rx_dma)); + ramips_fe_wr(rx, RAMIPS_RX_CALC_IDX0); + } + if(max_rx == 0) + tasklet_schedule(&priv->rx_tasklet); + else + ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) | RAMIPS_RX_DLY_INT, + RAMIPS_FE_INT_ENABLE); +} + +static void +ramips_eth_tx_housekeeping(unsigned long ptr) +{ + struct net_device *dev = (struct net_device*)ptr; + struct raeth_priv *priv = (struct raeth_priv*)netdev_priv(dev); + + while((priv->tx[priv->skb_free_idx].txd2 & TX_DMA_DONE) && + (priv->tx[priv->skb_free_idx].txd3)) + { + dev_kfree_skb_irq((struct sk_buff*)priv->tx[priv->skb_free_idx].txd3); + priv->tx[priv->skb_free_idx].txd3 = 0; + priv->skb_free_idx++; + if(priv->skb_free_idx >= NUM_TX_DESC) + priv->skb_free_idx = 0; + } + ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) | RAMIPS_TX_DLY_INT, + RAMIPS_FE_INT_ENABLE); +} + +static struct net_device_stats* +ramips_eth_get_stats(struct net_device *dev) +{ + return &((struct raeth_priv*)netdev_priv(dev))->stat; +} + +static int +ramips_eth_set_mac_addr(struct net_device *dev, void *priv) +{ + unsigned char *mac = (unsigned char*)priv; + + if(netif_running(dev)) + return -EBUSY; + memcpy(dev->dev_addr, ((struct sockaddr*)priv)->sa_data, dev->addr_len); + ramips_fe_wr((mac[0] << 8) | mac[1], RAMIPS_GDMA1_MAC_ADRH); + ramips_fe_wr(RAMIPS_GDMA1_MAC_ADRL, + (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5]); + return 0; +} + +static void +ramips_eth_timeout(struct net_device *dev) +{ + tasklet_schedule( + &((struct raeth_priv*)netdev_priv(dev))->tx_housekeeping_tasklet); +} + +static irqreturn_t +ramips_eth_irq(int irq, void *dev) +{ + struct raeth_priv *priv = (struct raeth_priv*)netdev_priv(dev); + unsigned long fe_int = ramips_fe_rr(RAMIPS_FE_INT_STATUS); + + if(fe_int & RAMIPS_RX_DLY_INT) + { + ramips_fe_wr(ramips_fe_rr(RAMIPS_FE_INT_ENABLE) & ~(RAMIPS_RX_DLY_INT), + RAMIPS_FE_INT_ENABLE); + tasklet_schedule(&priv->rx_tasklet); + } + if(fe_int & RAMIPS_TX_DLY_INT) + tasklet_schedule(&priv->tx_housekeeping_tasklet); + ramips_fe_wr(0xFFFFFFFF, RAMIPS_FE_INT_STATUS); + return IRQ_HANDLED; +} + +static int +ramips_eth_open(struct net_device *dev) +{ + struct raeth_priv *priv = (struct raeth_priv*)netdev_priv(dev); + + ramips_alloc_dma(dev); + ramips_fe_wr((ramips_fe_rr(RAMIPS_PDMA_GLO_CFG) & 0xff) | + (RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | + RAMIPS_TX_DMA_EN | RAMIPS_PDMA_SIZE_4DWORDS), + RAMIPS_PDMA_GLO_CFG); + ramips_fe_wr((ramips_fe_rr(RAMIPS_FE_GLO_CFG) & + ~(RAMIPS_US_CYC_CNT_MASK << RAMIPS_US_CYC_CNT_SHIFT)) | + ((rt305x_sys_freq / RAMIPS_US_CYC_CNT_DIVISOR) << RAMIPS_US_CYC_CNT_SHIFT), + RAMIPS_FE_GLO_CFG); + request_irq(dev->irq, ramips_eth_irq, IRQF_DISABLED, dev->name, dev); + tasklet_init(&priv->tx_housekeeping_tasklet, ramips_eth_tx_housekeeping, + (unsigned long)dev); + tasklet_init(&priv->rx_tasklet, ramips_eth_rx_hw, (unsigned long)dev); + ramips_fe_wr(RAMIPS_DELAY_INIT, RAMIPS_DLY_INT_CFG); + ramips_fe_wr(RAMIPS_TX_DLY_INT | RAMIPS_RX_DLY_INT, RAMIPS_FE_INT_ENABLE); + ramips_fe_wr(ramips_fe_rr(RAMIPS_GDMA1_FWD_CFG) & + ~(RAMIPS_GDM1_ICS_EN | RAMIPS_GDM1_TCS_EN | RAMIPS_GDM1_UCS_EN | 0xffff), + RAMIPS_GDMA1_FWD_CFG); + ramips_fe_wr(ramips_fe_rr(RAMIPS_CDMA_CSG_CFG) & + ~(RAMIPS_ICS_GEN_EN | RAMIPS_TCS_GEN_EN | RAMIPS_UCS_GEN_EN), + RAMIPS_CDMA_CSG_CFG); + ramips_fe_wr(RAMIPS_PSE_FQFC_CFG_INIT, RAMIPS_PSE_FQ_CFG); + ramips_fe_wr(1, RAMIPS_FE_RST_GL); + ramips_fe_wr(0, RAMIPS_FE_RST_GL); + netif_start_queue(dev); + return 0; +} + +static int +ramips_eth_stop(struct net_device *dev) +{ + struct raeth_priv *priv = (struct raeth_priv*)netdev_priv(dev); + + ramips_fe_wr(RAMIPS_PDMA_GLO_CFG, ramips_fe_rr(RAMIPS_PDMA_GLO_CFG) & + ~(RAMIPS_TX_WB_DDONE | RAMIPS_RX_DMA_EN | RAMIPS_TX_DMA_EN)); + free_irq(dev->irq, dev); + netif_stop_queue(dev); + tasklet_kill(&priv->tx_housekeeping_tasklet); + tasklet_kill(&priv->rx_tasklet); + pci_free_consistent(NULL, NUM_TX_DESC * sizeof(struct ramips_tx_dma), + priv->tx, priv->phy_tx); + pci_free_consistent(NULL, NUM_RX_DESC * sizeof(struct ramips_rx_dma), + priv->rx, priv->phy_rx); + printk(KERN_INFO "ramips_eth: stopped\n"); + return 0; +} + +int __init +ramips_eth_probe(struct net_device *dev) +{ + struct sockaddr addr; + unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80}; + + /* reset frame engine */ + rt305x_sysc_wr(RAMIPS_FE_RESET_BIT, RAMIPS_FE_RESET); + rt305x_sysc_wr(0, RAMIPS_FE_RESET); + + net_srandom(jiffies); + memcpy(addr.sa_data, mac_addr01234, 5); + addr.sa_data[5] = net_random()&0xFF; + ramips_eth_set_mac_addr(dev, &addr); + + ether_setup(dev); + dev->open = ramips_eth_open; + dev->stop = ramips_eth_stop; + dev->hard_start_xmit = ramips_eth_hard_start_xmit; + dev->get_stats = ramips_eth_get_stats; + dev->set_mac_address = ramips_eth_set_mac_addr; + dev->mtu = MAX_RX_LENGTH; + dev->tx_timeout = ramips_eth_timeout; + dev->watchdog_timeo = TX_TIMEOUT; + return 0; +} + +int __init +ramips_eth_init(void) +{ + ramips_fe_base = ioremap_nocache(RT305X_FE_BASE, PAGE_SIZE); + if(!ramips_fe_base) + return -ENOMEM; + ramips_dev = alloc_etherdev(sizeof(struct raeth_priv)); + if(!ramips_dev) + return -ENOMEM; + strcpy(ramips_dev->name, "eth%d"); + ramips_dev->irq = RT305X_CPU_IRQ_FE; + ramips_dev->addr_len = ETH_ALEN; + ramips_dev->base_addr = (unsigned long)ramips_fe_base; + ramips_dev->init = ramips_eth_probe; + if(register_netdev(ramips_dev)) + { + printk(KERN_ERR "ramips_eth: error bringing up device\n"); + return -ENXIO; + } +#ifdef CONFIG_RALINK_RT305X + rt305x_esw_init(); +#endif + printk(KERN_INFO "ramips_eth: loaded\n"); + return 0; +} + +void +ramips_eth_cleanup(void) +{ + unregister_netdev(ramips_dev); + free_netdev(ramips_dev); + printk(KERN_INFO "ramips_eth: unloaded"); +} + +module_init(ramips_eth_init); +module_exit(ramips_eth_cleanup); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>"); +MODULE_DESCRIPTION("ethernet driver for ramips boards"); diff --git a/target/linux/ramips/files/drivers/net/ramips_esw.c b/target/linux/ramips/files/drivers/net/ramips_esw.c new file mode 100644 index 0000000000..58bbc3faab --- /dev/null +++ b/target/linux/ramips/files/drivers/net/ramips_esw.c @@ -0,0 +1,119 @@ +#define GPIO_PRUPOSE 0x60 +#define GPIO_MDIO_BIT (1<<7) +#define RT305X_ESW_PHY_WRITE (1 << 13) +#define RT305X_ESW_PHY_TOUT (5 * HZ) +#define RT305X_ESW_PHY_CONTROL_0 0xC0 +#define RT305X_ESW_PHY_CONTROL_1 0xC4 + +static void __iomem *ramips_esw_base = 0; + +static inline void +ramips_esw_wr(u32 val, unsigned reg) +{ + __raw_writel(val, ramips_esw_base + reg); +} + +static inline u32 +ramips_esw_rr(unsigned reg) +{ + return __raw_readl(ramips_esw_base + reg); +} + +static void +ramips_enable_mdio(int s) +{ + u32 gpio = rt305x_sysc_rr(GPIO_PRUPOSE); + if(s) + gpio &= ~GPIO_MDIO_BIT; + else + gpio |= GPIO_MDIO_BIT; + rt305x_sysc_wr(gpio, GPIO_PRUPOSE); +} + +u32 +mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data) +{ + unsigned long volatile t_start = jiffies; + int ret = 0; + + ramips_enable_mdio(1); + while(1) + { + if(!(ramips_esw_rr(RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0))) + break; + if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT)) + { + ret = 1; + goto out; + } + } + ramips_esw_wr(((write_data & 0xFFFF) << 16) | (phy_register << 8) | + (phy_addr) | RT305X_ESW_PHY_WRITE, RT305X_ESW_PHY_CONTROL_0); + t_start = jiffies; + while(1) + { + if(ramips_esw_rr(RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0)) + break; + if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT)) + { + ret = 1; + break; + } + } +out: + ramips_enable_mdio(0); + if(ret) + printk(KERN_ERR "ramips_eth: MDIO timeout\n"); + return ret; +} + +static int +rt305x_esw_init(void) +{ + int i; + + ramips_esw_base = ioremap_nocache(RT305X_SWITCH_BASE, PAGE_SIZE); + if(!ramips_esw_base) + return -ENOMEM; + + /* vodoo from original driver */ + ramips_esw_wr(0xC8A07850, 0x08); + ramips_esw_wr(0x00000000, 0xe4); + ramips_esw_wr(0x00405555, 0x14); + ramips_esw_wr(0x00002001, 0x50); + ramips_esw_wr(0x00007f7f, 0x90); + ramips_esw_wr(0x00007f3f, 0x98); + ramips_esw_wr(0x00d6500c, 0xcc); + ramips_esw_wr(0x0008a301, 0x9c); + ramips_esw_wr(0x02404040, 0x8c); + ramips_esw_wr(0x00001002, 0x48); + ramips_esw_wr(0x3f502b28, 0xc8); + ramips_esw_wr(0x00000000, 0x84); + + mii_mgr_write(0, 31, 0x8000); + for(i = 0; i < 5; i++) + { + mii_mgr_write(i, 0, 0x3100); //TX10 waveform coefficient + mii_mgr_write(i, 26, 0x1601); //TX10 waveform coefficient + mii_mgr_write(i, 29, 0x7058); //TX100/TX10 AD/DA current bias + mii_mgr_write(i, 30, 0x0018); //TX100 slew rate control + } + /* PHY IOT */ + mii_mgr_write(0, 31, 0x0); //select global register + mii_mgr_write(0, 22, 0x052f); //tune TP_IDL tail and head waveform + mii_mgr_write(0, 17, 0x0fe0); //set TX10 signal amplitude threshold to minimum + mii_mgr_write(0, 18, 0x40ba); //set squelch amplitude to higher threshold + mii_mgr_write(0, 14, 0x65); //longer TP_IDL tail length + mii_mgr_write(0, 31, 0x8000); //select local register + + /* Port 5 Disabled */ + rt305x_sysc_wr(rt305x_sysc_rr(0x60) | (1 << 9), 0x60); //set RGMII to GPIO mode (GPIO41-GPIO50) + rt305x_sysc_wr(0xfff, 0x674); //GPIO41-GPIO50 output mode + rt305x_sysc_wr(0x0, 0x670); //GPIO41-GPIO50 output low + + /* set default vlan */ + ramips_esw_wr(0x2001, 0x50); + ramips_esw_wr(0x5041, 0x70); + + return 0; +} diff --git a/target/linux/ramips/patches-2.6.30/104-watchdog.patch b/target/linux/ramips/patches-2.6.30/104-watchdog.patch new file mode 100644 index 0000000000..793bea1c6c --- /dev/null +++ b/target/linux/ramips/patches-2.6.30/104-watchdog.patch @@ -0,0 +1,30 @@ +Index: linux-2.6.30.5/drivers/watchdog/Kconfig +=================================================================== +--- linux-2.6.30.5.orig/drivers/watchdog/Kconfig 2009-08-16 23:19:38.000000000 +0200 ++++ linux-2.6.30.5/drivers/watchdog/Kconfig 2009-09-04 15:19:34.000000000 +0200 +@@ -764,6 +764,13 @@ + help + Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. + ++config RAMIPS_WDT ++ tristate "Ralink Watchdog Timer" ++ depends on MIPS_RALINK ++ help ++ Hardware driver for the built-in watchdog timer on Ralink MIPS SoCs. ++ ++ + # PARISC Architecture + + # POWERPC Architecture +Index: linux-2.6.30.5/drivers/watchdog/Makefile +=================================================================== +--- linux-2.6.30.5.orig/drivers/watchdog/Makefile 2009-08-16 23:19:38.000000000 +0200 ++++ linux-2.6.30.5/drivers/watchdog/Makefile 2009-09-04 15:19:34.000000000 +0200 +@@ -105,6 +105,7 @@ + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o ++obj-$(CONFIG_RAMIPS_WDT) += ramipswdt.o + + # PARISC Architecture + diff --git a/target/linux/ramips/rt305x/config-2.6.30 b/target/linux/ramips/rt305x/config-2.6.30 index 1ce0825cbb..f757dbd7cf 100644 --- a/target/linux/ramips/rt305x/config-2.6.30 +++ b/target/linux/ramips/rt305x/config-2.6.30 @@ -98,6 +98,7 @@ CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_MIPS_RALINK=y +CONFIG_MIPS_RAMIPS_NET=y # CONFIG_MIPS_SIM is not set # CONFIG_MTD_CFI_INTELEXT is not set CONFIG_MTD_PHYSMAP=y |