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-rw-r--r--target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw5400-a.dts104
-rw-r--r--target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-ventana.dtsi51
-rw-r--r--target/linux/imx6/patches-3.10/110-gw5400-a.patch76
3 files changed, 103 insertions, 128 deletions
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw5400-a.dts b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw5400-a.dts
index ce30969c2e..f7ed236ebf 100644
--- a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -10,16 +10,43 @@
*/
/dts-v1/;
-#include "imx6q-ventana.dtsi"
+#include "imx6q.dtsi"
/ {
model = "Gateworks Ventana GW5400-A";
compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q";
+ /* these are used by bootloader for disabling nodes */
aliases {
ethernet0 = &fec;
ethernet1 = &eth1;
sky2 = &eth1;
+ ssi0 = &ssi1;
+ ssi1 = &ssi2;
+ ipu0 = &ipu1;
+ ipu1 = &ipu2;
+ usdhc0 = &usdhc1;
+ usdhc1 = &usdhc2;
+ usdhc2 = &usdhc3;
+ usdhc3 = &usdhc4;
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ usb0 = &usbh3;
+ usb1 = &usbotg;
+ spi0 = &ecspi1;
+ spi1 = &ecspi2;
+ spi2 = &ecspi3;
+ spi3 = &ecspi4;
+ spi4 = &ecspi5;
+ pwm0 = &pwm1;
+ pwm1 = &pwm2;
+ pwm2 = &pwm3;
+ pwm3 = &pwm4;
+ can0 = &can1;
+ led0 = &led0;
+ led1 = &led1;
+ led2 = &led2;
};
/* SDRAM addressing */
@@ -34,20 +61,23 @@
leds {
compatible = "gpio-leds";
- led0: user0 {
- label = "user0";
- gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG# */
+ led0: user1 {
+ label = "user1";
+ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */
+ default-state = "on";
linux,default-trigger = "heartbeat";
};
- led1: user1 {
- label = "user1";
- gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR# */
+ led1: user2 {
+ label = "user2";
+ gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */
+ default-state = "off";
};
- led2: user2 {
- label = "user2";
- gpios = <&gpio4 15 0>; /* 111 -> MX6_LOCLEDR# */
+ led2: user3 {
+ label = "user3";
+ gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */
+ default-state = "off";
};
};
@@ -102,34 +132,23 @@
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
- /* USB OTG Power Enable */
- MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000
-
- /* 3:19 SPINOR_CS0# */
- MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
-
- /* 1:09 MX6_DIO0 (could also be PWM1_PWM0) */
- MX6Q_PAD_GPIO_9__GPIO1_IO09 0x80000000
- /* 1:19 MX6_DIO1 (could also be PWM2_PWM0) */
- MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x80000000
- /* 2:09 MX6_DIO2 (could also be PWM3_PWM0) */
- MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x80000000
- /* 2:10 MX6_DIO3 (could also be PWM3_PWM0) */
- MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x80000000
-
- /* 1:16 USBHUB_RST# */
- MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
-
- /* PCIE IRQ */
- MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000
- /* PCIE RST */
- MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x08000000
-
- /* 1:12 MIPI_DIO */
- MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x80000000
-
- /* AUD4_MCK */
- MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000
+ MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */
+ MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */
+ MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user0 led */
+ MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user1 led */
+ MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user2 led */
+/* let bootloader choose these based on hwconfig */
+#if 0
+ MX6Q_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* MX6_DIO0 (or PWM1_PWM0) */
+ MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x80000000 /* MX6_DIO1 (or PWM2_PWM0) */
+ MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* MX6_DIO2 (or PWM3_PWM0) */
+ MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x80000000 /* MX6_DIO3 (or PWM3_PWM0) */
+#endif
+ MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */
+ MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */
+ MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x08000000 /* PCIE RST */
+ MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */
+ MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000 /* AUD4_MCK */
>;
};
};
@@ -262,7 +281,6 @@
&can1 {
reg = <0x02090000 0x4000>;
interrupts = <0 110 0x04>;
- //clock-frequency
status = "okay";
};
@@ -271,7 +289,7 @@
};
&pcie {
- reset-gpios = <&gpio1 29 0>;
+ reset-gpio = <&gpio1 29 0>;
status = "okay";
eth1: sky2@8 { /* MAC/PHY on bus 8 */
@@ -365,7 +383,7 @@
pmic: pfuze@08 {
compatible = "fsl,pfuze100";
- reg = <0x0a>;
+ reg = <0x08>;
};
pciswitch: pex8609@3f {
@@ -426,3 +444,7 @@
crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
};
};
+
+&sata {
+ status = "okay";
+};
diff --git a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-ventana.dtsi b/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-ventana.dtsi
deleted file mode 100644
index 7cebdba1ea..0000000000
--- a/target/linux/imx6/files-3.10/arch/arm/boot/dts/imx6q-ventana.dtsi
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2013 Gateworks Corporation
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include "imx6q.dtsi"
-
-/ {
- model = "Gateworks Ventana";
- system-serial = "";
-
- // these are used by bootloader for disabling nodes
- aliases {
- // ethernet0 = &eth0;
- // ethernet1 = &eth1;
- ssi0 = &ssi1;
- ssi1 = &ssi2;
- ipu0 = &ipu1;
- ipu1 = &ipu2;
- // mipi_csi = &mipi_csi;
- // mipi_dsi = &mipi_dsi;
- usdhc0 = &usdhc1;
- usdhc1 = &usdhc2;
- usdhc2 = &usdhc3;
- usdhc3 = &usdhc4;
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- usb0 = &usbh3;
- usb1 = &usbotg;
- spi0 = &ecspi1;
- spi1 = &ecspi2;
- spi2 = &ecspi3;
- spi3 = &ecspi4;
- spi4 = &ecspi5;
- pwm0 = &pwm1;
- pwm1 = &pwm2;
- pwm2 = &pwm3;
- pwm3 = &pwm4;
- can0 = &can1;
- led0 = &led0;
- led1 = &led1;
- led2 = &led2;
- };
-};
diff --git a/target/linux/imx6/patches-3.10/110-gw5400-a.patch b/target/linux/imx6/patches-3.10/110-gw5400-a.patch
index ac0721d925..e554540dad 100644
--- a/target/linux/imx6/patches-3.10/110-gw5400-a.patch
+++ b/target/linux/imx6/patches-3.10/110-gw5400-a.patch
@@ -25,7 +25,38 @@
};
ecspi1 {
-@@ -205,6 +213,12 @@
+@@ -187,6 +195,30 @@
+ MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
+ >;
+ };
++
++ /* No strobe */
++ pinctrl_gpmi_nand_2: gpmi-nand-2 {
++ fsl,pins = <
++ MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
++ MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
++ MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
++ MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ >;
++ };
+ };
+
+ i2c1 {
+@@ -205,6 +237,12 @@
MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
>;
};
@@ -38,7 +69,7 @@
};
i2c3 {
-@@ -214,6 +228,12 @@
+@@ -214,6 +252,12 @@
MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
@@ -51,7 +82,7 @@
};
uart1 {
-@@ -223,6 +243,12 @@
+@@ -223,6 +267,12 @@
MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
>;
};
@@ -64,7 +95,7 @@
};
uart2 {
-@@ -232,6 +258,21 @@
+@@ -232,6 +282,21 @@
MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
>;
};
@@ -86,7 +117,7 @@
};
uart4 {
-@@ -242,6 +283,15 @@
+@@ -242,6 +307,15 @@
>;
};
};
@@ -112,7 +143,7 @@
#include <linux/phy.h>
#include <linux/regmap.h>
#include <linux/micrel_phy.h>
-@@ -145,6 +146,65 @@ static void __init imx6q_sabrelite_init(
+@@ -145,6 +146,38 @@ static void __init imx6q_sabrelite_init(
imx6q_sabrelite_cko1_setup();
}
@@ -137,48 +168,21 @@
+ pci_read_config_dword(dev, 0x644, &dw);
+ dw |= 0xfe; // GPIO1-7 output high
+ pci_write_config_dword(dev, 0x644, dw);
++
++ mdelay(1);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609,
+ mx6_ventana_pciesw_early_fixup);
+
-+/*
-+ * configure PCIe core clock and PCIe ref clock
-+ *
-+ * TODO: disable CLK1 output and use CLK2 input from si52147 as PCIe ref
-+ */
-+static void __init imx6q_ventana_pcie_setup(void)
-+{
-+ struct clk *axi_sel, *axi, *ref;
-+
-+ axi_sel = clk_get_sys(NULL, "pcie_axi_sel");
-+ axi = clk_get_sys(NULL, "axi");
-+ ref = clk_get_sys(NULL, "pcie_ref_125m");
-+ if (IS_ERR(axi_sel) || IS_ERR(axi) || IS_ERR(ref)) {
-+ pr_err("pcie setup failed - can't get clocks\n");
-+ goto put_clk;
-+ }
-+ clk_set_parent(axi_sel, axi);
-+ clk_prepare_enable(ref);
-+
-+put_clk:
-+ if (!IS_ERR(axi_sel))
-+ clk_put(axi_sel);
-+ if (!IS_ERR(axi))
-+ clk_put(axi);
-+ if (!IS_ERR(ref))
-+ clk_put(ref);
-+}
-+
+static void __init imx6q_ventana_init(void)
+{
-+ imx6q_ventana_pcie_setup();
+ imx6q_sabrelite_cko1_setup();
+}
+
static void __init imx6q_1588_init(void)
{
struct regmap *gpr;
-@@ -163,6 +223,9 @@ static void __init imx6q_usb_init(void)
+@@ -163,6 +196,9 @@ static void __init imx6q_usb_init(void)
static void __init imx6q_init_machine(void)
{
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 15:40:44 +0000