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-rw-r--r--target/linux/sunxi/patches-5.10/103-arm64-dts-allwinner-orangepi-zero-plus-fix-PHY-mo.patch32
1 files changed, 32 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-5.10/103-arm64-dts-allwinner-orangepi-zero-plus-fix-PHY-mo.patch b/target/linux/sunxi/patches-5.10/103-arm64-dts-allwinner-orangepi-zero-plus-fix-PHY-mo.patch
new file mode 100644
index 0000000000..e3a00348b0
--- /dev/null
+++ b/target/linux/sunxi/patches-5.10/103-arm64-dts-allwinner-orangepi-zero-plus-fix-PHY-mo.patch
@@ -0,0 +1,32 @@
+From 4f45f9f370a5bc6a43a7a166f10b3a30ca21353c Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Wed, 17 Nov 2021 10:36:31 +0100
+Subject: [PATCH v2] arm64: dts: allwinner: orangepi-zero-plus: fix PHY mode
+
+Orange Pi Zero Plus uses a Realtek RTL8211E RGMII Gigabit PHY, but its
+currently set to plain RGMII mode meaning that it doesn't introduce
+delays.
+
+With this setup, TX packets are completely lost and changing the mode to
+RGMII-ID so the PHY will add delays internally fixes the issue.
+
+Fixes: a7affb13b271 ("arm64: allwinner: H5: Add Xunlong Orange Pi Zero Plus")
+
+Tested-by: Ron Goossens <rgoossens@gmail.com>
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Tested-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+@@ -69,7 +69,7 @@
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+- phy-mode = "rgmii";
++ phy-mode = "rgmii-id";
+ status = "okay";
+ };
+