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-rwxr-xr-xtarget/linux/rockchip/armv8/base-files/etc/board.d/01_leds20
-rwxr-xr-xtarget/linux/rockchip/armv8/base-files/etc/board.d/02_network42
-rw-r--r--target/linux/rockchip/armv8/config-5.42
-rw-r--r--target/linux/rockchip/image/armv8.mk11
-rw-r--r--target/linux/rockchip/image/nanopi-r2s.bootscript8
-rw-r--r--target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch370
-rw-r--r--target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch40
-rw-r--r--target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch62
-rw-r--r--target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch60
9 files changed, 609 insertions, 6 deletions
diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
new file mode 100755
index 0000000000..bba3e2aa56
--- /dev/null
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/01_leds
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+. /lib/functions/leds.sh
+. /lib/functions/uci-defaults.sh
+
+board=$(board_name)
+boardname="${board##*,}"
+
+board_config_update
+
+case $board in
+friendlyarm,nanopi-r2s)
+ ucidef_set_led_netdev "wan" "WAN" "$boardname:green:wan" "eth0"
+ ucidef_set_led_netdev "lan" "LAN" "$boardname:green:lan" "eth1"
+ ;;
+esac
+
+board_config_flush
+
+exit 0
diff --git a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
index c5adda1706..e129fd6a67 100755
--- a/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
+++ b/target/linux/rockchip/armv8/base-files/etc/board.d/02_network
@@ -1,15 +1,45 @@
#!/bin/sh
. /lib/functions/uci-defaults.sh
+. /lib/functions/system.sh
-board_config_update
+rockchip_setup_interfaces()
+{
+ local board="$1"
+
+ case "$board" in
+ friendlyarm,nanopi-r2s)
+ ucidef_set_interfaces_lan_wan 'eth1' 'eth0'
+ ;;
+ *)
+ ucidef_set_interface_lan 'eth0'
+ ;;
+ esac
+}
+
+rockchip_setup_macs()
+{
+ local board="$1"
+ local lan_mac=""
+ local wan_mac=""
+ local label_mac=""
-case "$(board_name)" in
-*)
- ucidef_set_interface_lan 'eth0'
- ;;
-esac
+ case "$board" in
+ friendlyarm,nanopi-r2s)
+ wan_mac=$(macaddr_random)
+ lan_mac=$(macaddr_add "$wan_mac" +1)
+ ;;
+ esac
+ [ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
+ [ -n "$wan_mac" ] && ucidef_set_interface_macaddr "wan" $wan_mac
+ [ -n "$label_mac" ] && ucidef_set_label_macaddr $label_mac
+}
+
+board_config_update
+board=$(board_name)
+rockchip_setup_interfaces $board
+rockchip_setup_macs $board
board_config_flush
exit 0
diff --git a/target/linux/rockchip/armv8/config-5.4 b/target/linux/rockchip/armv8/config-5.4
index 4f29204dd2..2615684fed 100644
--- a/target/linux/rockchip/armv8/config-5.4
+++ b/target/linux/rockchip/armv8/config-5.4
@@ -375,6 +375,7 @@ CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FAN53555=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
CONFIG_REGULATOR_PWM=y
CONFIG_REGULATOR_RK808=y
CONFIG_RELOCATABLE=y
@@ -482,6 +483,7 @@ CONFIG_UNINLINE_SPIN_UNLOCK=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
CONFIG_USB_DWC3_HOST=y
CONFIG_USB_DWC3_OF_SIMPLE=y
CONFIG_USB_EHCI_HCD=y
diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk
index 737c6e4f9a..8e4ba07e0b 100644
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@@ -4,6 +4,17 @@
# This is free software, licensed under the GNU General Public License v2.
# See /LICENSE for more information.
#
+
+define Device/friendlyarm_nanopi-r2s
+ DEVICE_VENDOR := FriendlyARM
+ DEVICE_MODEL := NanoPi R2S
+ SOC := rk3328
+ UBOOT_DEVICE_NAME := nanopi-r2s-rk3328
+ IMAGE/sysupgrade.img.gz := boot-common | boot-script nanopi-r2s | pine64-img | gzip | append-metadata
+ DEVICE_PACKAGES := kmod-usb-net kmod-usb-net-rtl8152
+endef
+TARGET_DEVICES += friendlyarm_nanopi-r2s
+
define Device/pine64_rockpro64
DEVICE_VENDOR := Pine64
DEVICE_MODEL := RockPro64
diff --git a/target/linux/rockchip/image/nanopi-r2s.bootscript b/target/linux/rockchip/image/nanopi-r2s.bootscript
new file mode 100644
index 0000000000..5198881a26
--- /dev/null
+++ b/target/linux/rockchip/image/nanopi-r2s.bootscript
@@ -0,0 +1,8 @@
+part uuid mmc ${devnum}:2 uuid
+
+setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff130000 root=PARTUUID=${uuid} rw rootwait"
+
+load mmc ${devnum}:1 ${fdt_addr_r} rockchip.dtb
+load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
+
+booti ${kernel_addr_r} - ${fdt_addr_r}
diff --git a/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
new file mode 100644
index 0000000000..904a2f31b6
--- /dev/null
+++ b/target/linux/rockchip/patches-5.4/001-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
@@ -0,0 +1,370 @@
+From 749cbb7b1a4bc2244b6af8cd7d8b471d4e33c80f Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 10 Jul 2020 15:57:46 +0200
+Subject: [PATCH] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
+
+This adds support for the NanoPi R2S from FriendlyARM.
+
+Rockchip RK3328 SoC
+1GB DDR4 RAM
+Gigabit Ethernet (WAN)
+Gigabit Ethernet (USB3) (LAN)
+USB 2.0 Host Port
+MicroSD slot
+Reset button
+WAN - LAN - SYS LED
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 334 ++++++++++++++++++
+ 2 files changed, 335 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -0,0 +1,334 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/gpio/gpio.h>
++#include "rk3328.dtsi"
++
++/ {
++ model = "FriendlyARM NanoPi R2S";
++ compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
++
++ chosen {
++ stdout-path = "serial2:1500000n8";
++ };
++
++ gmac_clkin: external-gmac-clock {
++ compatible = "fixed-clock";
++ clock-frequency = <125000000>;
++ clock-output-names = "gmac_clkin";
++ #clock-cells = <0>;
++ };
++
++ vcc_sd: sdmmc-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0m1_gpio>;
++ regulator-name = "vcc_sd";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc_io>;
++ };
++
++ vcc_sdio: sdmmcio-regulator {
++ compatible = "regulator-gpio";
++ gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ states = <1800000 0x1
++ 3300000 0x0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdio_vcc_pin>;
++ regulator-always-on;
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-name = "vcc_sdio";
++ regulator-settling-time-us = <5000>;
++ regulator-type = "voltage";
++ vin-supply = <&vcc_io>;
++ };
++
++ vcc_sys: vcc-sys {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&led_pins>;
++
++ sys {
++ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
++ label = "nanopi-r2s:red:sys";
++ };
++
++ lan {
++ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
++ label = "nanopi-r2s:green:lan";
++ };
++
++ wan {
++ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
++ label = "nanopi-r2s:green:wan";
++ };
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys-polled";
++ poll-interval = <100>;
++
++ pinctrl-names = "default";
++ pinctrl-0 = <&button_pins>;
++
++ reset {
++ label = "Reset Button";
++ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_RESTART>;
++ debounce-interval = <50>;
++ };
++ };
++};
++
++&cpu0 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++ cpu-supply = <&vdd_arm>;
++};
++
++&gmac2io {
++ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
++ assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
++ clock_in_out = "input";
++ phy-supply = <&vcc_io>;
++ phy-handle = <&rtl8211e>;
++ phy-mode = "rgmii";
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmiim1_pins>;
++ snps,aal;
++ snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++ snps,reset-active-low;
++ snps,reset-delays-us = <0 10000 50000>;
++ tx_delay = <0x24>;
++ rx_delay = <0x18>;
++ status = "okay";
++
++ mdio {
++ compatible = "snps,dwmac-mdio";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ rtl8211e: ethernet-phy@0 {
++ reg = <0>;
++ };
++ };
++};
++
++&i2c1 {
++ status = "okay";
++
++ rk805: rk805@18 {
++ compatible = "rockchip,rk805";
++ reg = <0x18>;
++ interrupt-parent = <&gpio2>;
++ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
++ #clock-cells = <1>;
++ clock-output-names = "xin32k", "rk805-clkout2";
++ gpio-controller;
++ #gpio-cells = <2>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pmic_int_l>;
++ rockchip,system-power-controller;
++ wakeup-source;
++
++ vcc1-supply = <&vcc_sys>;
++ vcc2-supply = <&vcc_sys>;
++ vcc3-supply = <&vcc_sys>;
++ vcc4-supply = <&vcc_sys>;
++ vcc5-supply = <&vcc_io>;
++ vcc6-supply = <&vcc_sys>;
++
++ regulators {
++ vdd_logic: DCDC_REG1 {
++ regulator-name = "vdd_logic";
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-ramp-delay = <12500>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++
++ vdd_arm: DCDC_REG2 {
++ regulator-name = "vdd_arm";
++ regulator-min-microvolt = <712500>;
++ regulator-max-microvolt = <1450000>;
++ regulator-ramp-delay = <12500>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <950000>;
++ };
++ };
++
++ vcc_ddr: DCDC_REG3 {
++ regulator-name = "vcc_ddr";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ };
++ };
++
++ vcc_io: DCDC_REG4 {
++ regulator-name = "vcc_io";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <3300000>;
++ };
++ };
++
++ vcc_18: LDO_REG1 {
++ regulator-name = "vcc_18";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vcc18_emmc: LDO_REG2 {
++ regulator-name = "vcc18_emmc";
++ regulator-min-microvolt = <1800000>;
++ regulator-max-microvolt = <1800000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1800000>;
++ };
++ };
++
++ vdd_10: LDO_REG3 {
++ regulator-name = "vdd_10";
++ regulator-min-microvolt = <1000000>;
++ regulator-max-microvolt = <1000000>;
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-state-mem {
++ regulator-on-in-suspend;
++ regulator-suspend-microvolt = <1000000>;
++ };
++ };
++ };
++ };
++};
++
++&io_domains {
++ status = "okay";
++
++ vccio1-supply = <&vcc_io>;
++ vccio2-supply = <&vcc18_emmc>;
++ vccio3-supply = <&vcc_sdio>;
++ vccio4-supply = <&vcc_18>;
++ vccio5-supply = <&vcc_io>;
++ vccio6-supply = <&vcc_io>;
++ pmuio-supply = <&vcc_io>;
++};
++
++&pinctrl {
++ leds {
++ led_pins: led-pins {
++ rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>,
++ <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>,
++ <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ button {
++ button_pins: button-pins {
++ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
++ pmic {
++ pmic_int_l: pmic-int-l {
++ rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++
++ sd {
++ sdio_vcc_pin: sdio-vcc-pin {
++ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
++ };
++ };
++};
++
++&sdmmc {
++ bus-width = <4>;
++ cap-mmc-highspeed;
++ cap-sd-highspeed;
++ disable-wp;
++ max-frequency = <150000000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
++ vmmc-supply = <&vcc_sd>;
++ vqmmc-supply = <&vcc_sdio>;
++ status = "okay";
++};
++
++&tsadc {
++ rockchip,hw-tshut-mode = <0>;
++ rockchip,hw-tshut-polarity = <0>;
++ status = "okay";
++};
++
++&uart2 {
++ status = "okay";
++};
++
++&u2phy {
++ status = "okay";
++
++ u2phy_host: host-port {
++ status = "okay";
++ };
++};
++
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
diff --git a/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch
new file mode 100644
index 0000000000..1250dbcd9b
--- /dev/null
+++ b/target/linux/rockchip/patches-5.4/100-rockchip-use-system-LED-for-OpenWrt.patch
@@ -0,0 +1,40 @@
+From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 10 Jul 2020 21:38:20 +0200
+Subject: [PATCH] rockchip: use system LED for OpenWrt
+
+Use the SYS LED on the casing for showing system status.
+
+This patch is kept seperate from the NanoPi R2S support patch, as i plan
+on submitting the device support upstream.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -17,6 +17,13 @@
+ stdout-path = "serial2:1500000n8";
+ };
+
++ aliases {
++ led-boot = &led_sys;
++ led-failsafe = &led_sys;
++ led-running = &led_sys;
++ led-upgrade = &led_sys;
++ };
++
+ gmac_clkin: external-gmac-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+@@ -67,7 +74,7 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+- sys {
++ led_sys: sys {
+ gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ label = "nanopi-r2s:red:sys";
+ };
diff --git a/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch
new file mode 100644
index 0000000000..316f7c01d3
--- /dev/null
+++ b/target/linux/rockchip/patches-5.4/101-dts-rockchip-add-usb3-controller-node-for-RK3328-SoCs.patch
@@ -0,0 +1,62 @@
+From: William Wu <william.wu@rock-chips.com>
+
+RK3328 has one USB 3.0 OTG controller which uses DWC_USB3
+core's general architecture. It can act as static xHCI host
+controller, static device controller, USB 3.0/2.0 OTG basing
+on ID of USB3.0 PHY.
+
+Signed-off-by: William Wu <william.wu@rock-chips.com>
+Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
+
+---
+
+NOTE: This binding still has issues. From the original thread:
+
+the rk3328 usb3-phy has an issue with detecting any plugin events
+after a previous device got removed - see the inno-usb3-phy driver
+in the vendor kernel.
+
+The current state is good-enough for enabling the USB3 attached LAN
+port of the NanoPi R2S. However, it might explode depending on your
+use-case. You've been warned.
+
+---
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 27 ++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -936,6 +936,33 @@
+ status = "disabled";
+ };
+
++ usbdrd3: usb@ff600000 {
++ compatible = "rockchip,rk3328-dwc3", "rockchip,rk3399-dwc3";
++ clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
++ <&cru ACLK_USB3OTG>;
++ clock-names = "ref_clk", "suspend_clk",
++ "bus_clk";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++ status = "disabled";
++
++ usbdrd_dwc3: dwc3@ff600000 {
++ compatible = "snps,dwc3";
++ reg = <0x0 0xff600000 0x0 0x100000>;
++ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
++ dr_mode = "otg";
++ phy_type = "utmi_wide";
++ snps,dis_enblslpm_quirk;
++ snps,dis-u2-freeclk-exists-quirk;
++ snps,dis_u2_susphy_quirk;
++ snps,dis_u3_susphy_quirk;
++ snps,dis-del-phy-power-chg-quirk;
++ snps,dis-tx-ipgap-linecheck-quirk;
++ status = "disabled";
++ };
++ };
++
+ gic: interrupt-controller@ff811000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
diff --git a/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch
new file mode 100644
index 0000000000..1b52de231e
--- /dev/null
+++ b/target/linux/rockchip/patches-5.4/102-rockchip-enable-LAN-port-on-NanoPi-R2S.patch
@@ -0,0 +1,60 @@
+From 0fc3b9b7619c4878f73a6a7989863f0d1a3fd392 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 10 Jul 2020 21:12:16 +0200
+Subject: [PATCH] rockchip: enabled LAN port on NanoPi R2S
+
+Enable the USB3 port on the FriendlyARM NanoPi R2S.
+This is required for the USB3 attached LAN port to work.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ .../boot/dts/rockchip/rk3328-nanopi-r2s.dts | 27 +++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -68,6 +68,18 @@
+ regulator-max-microvolt = <5000000>;
+ };
+
++ vcc_rtl8153: vcc-rtl8153-regulator {
++ compatible = "regulator-fixed";
++ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&rtl8153_en_drv>;
++ regulator-always-on;
++ regulator-name = "vcc_rtl8153";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ enable-active-high;
++ };
++
+ leds {
+ compatible = "gpio-leds";
+
+@@ -288,6 +300,12 @@
+ rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
++
++ usb {
++ rtl8153_en_drv: rtl8153-en-drv {
++ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
+ };
+
+ &sdmmc {
+@@ -328,3 +346,12 @@
+ &usb_host0_ohci {
+ status = "okay";
+ };
++
++&usbdrd3 {
++ status = "okay";
++};
++
++&usbdrd_dwc3 {
++ dr_mode = "host";
++ status = "okay";
++};