diff options
Diffstat (limited to 'target')
| -rw-r--r-- | target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch | 3184 |
1 files changed, 3184 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch b/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch new file mode 100644 index 0000000000..38f75c8342 --- /dev/null +++ b/target/linux/lantiq/patches-3.18/0042-USB-DWC2-big-endian-support.patch @@ -0,0 +1,3184 @@ +--- a/drivers/usb/dwc2/core.c 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/core.c 2015-02-09 19:34:42.863106075 +0200 +@@ -67,10 +67,10 @@ + u32 intmsk; + + /* Clear any pending OTG Interrupts */ +- writel(0xffffffff, hsotg->regs + GOTGINT); ++ dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + + /* Clear any pending interrupts */ +- writel(0xffffffff, hsotg->regs + GINTSTS); ++ dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + + /* Enable the interrupts in the GINTMSK */ + intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT; +@@ -81,7 +81,7 @@ + intmsk |= GINTSTS_CONIDSTSCHNG | GINTSTS_WKUPINT | GINTSTS_USBSUSP | + GINTSTS_SESSREQINT; + +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /* +@@ -104,10 +104,10 @@ + } + + dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val); +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + + /* +@@ -125,7 +125,7 @@ + /* Wait for AHB master IDLE state */ + do { + usleep_range(20000, 40000); +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 50) { + dev_warn(hsotg->dev, + "%s() HANG! AHB Idle GRSTCTL=%0x\n", +@@ -137,10 +137,10 @@ + /* Core Soft Reset */ + count = 0; + greset |= GRSTCTL_CSFTRST; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + do { + usleep_range(20000, 40000); +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 50) { + dev_warn(hsotg->dev, + "%s() HANG! Soft Reset GRSTCTL=%0x\n", +@@ -150,20 +150,20 @@ + } while (greset & GRSTCTL_CSFTRST); + + if (hsotg->dr_mode == USB_DR_MODE_HOST) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEDEVMODE; + gusbcfg |= GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; + gusbcfg |= GUSBCFG_FORCEDEVMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } else if (hsotg->dr_mode == USB_DR_MODE_OTG) { +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; + gusbcfg &= ~GUSBCFG_FORCEDEVMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + } + + /* +@@ -186,9 +186,9 @@ + */ + if (select_phy) { + dev_dbg(hsotg->dev, "FS PHY selected\n"); +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_PHYSEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset after a PHY select */ + retval = dwc2_core_reset(hsotg); +@@ -211,18 +211,18 @@ + dev_dbg(hsotg->dev, "FS PHY enabling I2C\n"); + + /* Program GUSBCFG.OtgUtmiFsSel to I2C */ +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Program GI2CCTL.I2CEn */ +- i2cctl = readl(hsotg->regs + GI2CCTL); ++ i2cctl = dwc2_readl(hsotg->regs + GI2CCTL); + i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK; + i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT; + i2cctl &= ~GI2CCTL_I2CEN; +- writel(i2cctl, hsotg->regs + GI2CCTL); ++ dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); + i2cctl |= GI2CCTL_I2CEN; +- writel(i2cctl, hsotg->regs + GI2CCTL); ++ dwc2_writel(i2cctl, hsotg->regs + GI2CCTL); + } + + return retval; +@@ -236,7 +236,7 @@ + if (!select_phy) + return 0; + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + + /* + * HS PHY parameters. These parameters are preserved during soft reset +@@ -264,7 +264,7 @@ + break; + } + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset after setting the PHY parameters */ + retval = dwc2_core_reset(hsotg); +@@ -299,15 +299,15 @@ + hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && + hsotg->core_params->ulpi_fs_ls > 0) { + dev_dbg(hsotg->dev, "Setting ULPI FSLS\n"); +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg |= GUSBCFG_ULPI_FS_LS; + usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } else { +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg &= ~GUSBCFG_ULPI_FS_LS; + usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } + + return retval; +@@ -315,7 +315,7 @@ + + static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + switch (hsotg->hw_params.arch) { + case GHWCFG2_EXT_DMA_ARCH: +@@ -354,7 +354,7 @@ + if (hsotg->core_params->dma_enable > 0) + ahbcfg |= GAHBCFG_DMA_EN; + +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + + return 0; + } +@@ -363,7 +363,7 @@ + { + u32 usbcfg; + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP); + + switch (hsotg->hw_params.op_mode) { +@@ -391,7 +391,7 @@ + break; + } + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + } + + /** +@@ -409,7 +409,7 @@ + + dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + + /* Set ULPI External VBUS bit if needed */ + usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV; +@@ -422,7 +422,7 @@ + if (hsotg->core_params->ts_dline > 0) + usbcfg |= GUSBCFG_TERMSELDLPULSE; + +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + + /* Reset the Controller */ + retval = dwc2_core_reset(hsotg); +@@ -448,11 +448,11 @@ + dwc2_gusbcfg_init(hsotg); + + /* Program the GOTGCTL register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_OTGVER; + if (hsotg->core_params->otg_ver > 0) + otgctl |= GOTGCTL_OTGVER; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver); + + /* Clear the SRP success bit for FS-I2c */ +@@ -498,16 +498,16 @@ + dev_dbg(hsotg->dev, "%s()\n", __func__); + + /* Disable all interrupts */ +- writel(0, hsotg->regs + GINTMSK); +- writel(0, hsotg->regs + HAINTMSK); ++ dwc2_writel(0, hsotg->regs + GINTMSK); ++ dwc2_writel(0, hsotg->regs + HAINTMSK); + + /* Enable the common interrupts */ + dwc2_enable_common_interrupts(hsotg); + + /* Enable host mode interrupts without disturbing common interrupts */ +- intmsk = readl(hsotg->regs + GINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT; +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /** +@@ -517,12 +517,12 @@ + */ + void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 intmsk = readl(hsotg->regs + GINTMSK); ++ u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK); + + /* Disable host mode interrupts without disturbing common interrupts */ + intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT | + GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP); +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + } + + /* +@@ -602,36 +602,36 @@ + dwc2_calculate_dynamic_fifo(hsotg); + + /* Rx FIFO */ +- grxfsiz = readl(hsotg->regs + GRXFSIZ); ++ grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz); + grxfsiz &= ~GRXFSIZ_DEPTH_MASK; + grxfsiz |= params->host_rx_fifo_size << + GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK; +- writel(grxfsiz, hsotg->regs + GRXFSIZ); +- dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", readl(hsotg->regs + GRXFSIZ)); ++ dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ); ++ dev_dbg(hsotg->dev, "new grxfsiz=%08x\n", dwc2_readl(hsotg->regs + GRXFSIZ)); + + /* Non-periodic Tx FIFO */ + dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n", +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + nptxfsiz = params->host_nperio_tx_fifo_size << + FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; + nptxfsiz |= params->host_rx_fifo_size << + FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; +- writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); ++ dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ); + dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n", +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + + /* Periodic Tx FIFO */ + dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n", +- readl(hsotg->regs + HPTXFSIZ)); ++ dwc2_readl(hsotg->regs + HPTXFSIZ)); + hptxfsiz = params->host_perio_tx_fifo_size << + FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK; + hptxfsiz |= (params->host_rx_fifo_size + + params->host_nperio_tx_fifo_size) << + FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK; +- writel(hptxfsiz, hsotg->regs + HPTXFSIZ); ++ dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ); + dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n", +- readl(hsotg->regs + HPTXFSIZ)); ++ dwc2_readl(hsotg->regs + HPTXFSIZ)); + + if (hsotg->core_params->en_multiple_tx_fifo > 0 && + hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) { +@@ -639,14 +639,14 @@ + * Global DFIFOCFG calculation for Host mode - + * include RxFIFO, NPTXFIFO and HPTXFIFO + */ +- dfifocfg = readl(hsotg->regs + GDFIFOCFG); ++ dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG); + dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK; + dfifocfg |= (params->host_rx_fifo_size + + params->host_nperio_tx_fifo_size + + params->host_perio_tx_fifo_size) << + GDFIFOCFG_EPINFOBASE_SHIFT & + GDFIFOCFG_EPINFOBASE_MASK; +- writel(dfifocfg, hsotg->regs + GDFIFOCFG); ++ dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG); + } + } + +@@ -667,14 +667,14 @@ + dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + /* Restart the Phy Clock */ +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + + /* Initialize Host Configuration Register */ + dwc2_init_fs_ls_pclk_sel(hsotg); + if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) { +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg |= HCFG_FSLSSUPP; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + + /* +@@ -683,9 +683,9 @@ + * and its value must not be changed during runtime. + */ + if (hsotg->core_params->reload_ctl > 0) { +- hfir = readl(hsotg->regs + HFIR); ++ hfir = dwc2_readl(hsotg->regs + HFIR); + hfir |= HFIR_RLDCTRL; +- writel(hfir, hsotg->regs + HFIR); ++ dwc2_writel(hfir, hsotg->regs + HFIR); + } + + if (hsotg->core_params->dma_desc_enable > 0) { +@@ -701,9 +701,9 @@ + "falling back to buffer DMA mode.\n"); + hsotg->core_params->dma_desc_enable = 0; + } else { +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + hcfg |= HCFG_DESCDMA; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + } + } + +@@ -712,18 +712,18 @@ + + /* TODO - check this */ + /* Clear Host Set HNP Enable in the OTG Control Register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_HSTSETHNPEN; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + /* Make sure the FIFOs are flushed */ + dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */); + dwc2_flush_rx_fifo(hsotg); + + /* Clear Host Set HNP Enable in the OTG Control Register */ +- otgctl = readl(hsotg->regs + GOTGCTL); ++ otgctl = dwc2_readl(hsotg->regs + GOTGCTL); + otgctl &= ~GOTGCTL_HSTSETHNPEN; +- writel(otgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(otgctl, hsotg->regs + GOTGCTL); + + if (hsotg->core_params->dma_desc_enable <= 0) { + int num_channels, i; +@@ -732,25 +732,25 @@ + /* Flush out any leftover queued requests */ + num_channels = hsotg->core_params->host_channels; + for (i = 0; i < num_channels; i++) { +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar &= ~HCCHAR_CHENA; + hcchar |= HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + + /* Halt all channels to put them into a known state */ + for (i = 0; i < num_channels; i++) { + int count = 0; + +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS; + hcchar &= ~HCCHAR_EPDIR; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + dev_dbg(hsotg->dev, "%s: Halt channel %d\n", + __func__, i); + do { +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (++count > 1000) { + dev_err(hsotg->dev, + "Unable to clear enable on channel %d\n", +@@ -771,7 +771,7 @@ + !!(hprt0 & HPRT0_PWR)); + if (!(hprt0 & HPRT0_PWR)) { + hprt0 |= HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + } + +@@ -851,7 +851,7 @@ + break; + } + +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); + } +@@ -888,7 +888,7 @@ + } + } + +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk); + } +@@ -909,16 +909,16 @@ + } + + /* Enable the top level host channel interrupt */ +- intmsk = readl(hsotg->regs + HAINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + HAINTMSK); + intmsk |= 1 << chan->hc_num; +- writel(intmsk, hsotg->regs + HAINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + HAINTMSK); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk); + + /* Make sure host channel interrupts are enabled */ +- intmsk = readl(hsotg->regs + GINTMSK); ++ intmsk = dwc2_readl(hsotg->regs + GINTMSK); + intmsk |= GINTSTS_HCHINT; +- writel(intmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(intmsk, hsotg->regs + GINTMSK); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk); + } +@@ -947,7 +947,7 @@ + /* Clear old interrupt conditions for this host channel */ + hcintmsk = 0xffffffff; + hcintmsk &= ~HCINTMSK_RESERVED14_31; +- writel(hcintmsk, hsotg->regs + HCINT(hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num)); + + /* Enable channel interrupts required for this transfer */ + dwc2_hc_enable_ints(hsotg, chan); +@@ -964,7 +964,7 @@ + hcchar |= HCCHAR_LSPDDEV; + hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK; + hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK; +- writel(hcchar, hsotg->regs + HCCHAR(hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num)); + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n", + hc_num, hcchar); +@@ -1018,7 +1018,7 @@ + } + } + +- writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); ++ dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num)); + } + + /** +@@ -1070,14 +1070,14 @@ + u32 hcintmsk = HCINTMSK_CHHLTD; + + dev_vdbg(hsotg->dev, "dequeue/error\n"); +- writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num)); + + /* + * Make sure no other interrupts besides halt are currently + * pending. Handling another interrupt could cause a crash due + * to the QTD and QH state. + */ +- writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); ++ dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + + /* + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR +@@ -1086,7 +1086,7 @@ + */ + chan->halt_status = halt_status; + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + if (!(hcchar & HCCHAR_CHENA)) { + /* + * The channel is either already halted or it hasn't +@@ -1114,7 +1114,7 @@ + return; + } + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + + /* No need to set the bit in DDMA for disabling the channel */ + /* TODO check it everywhere channel is disabled */ +@@ -1137,7 +1137,7 @@ + if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || + chan->ep_type == USB_ENDPOINT_XFER_BULK) { + dev_vdbg(hsotg->dev, "control/bulk\n"); +- nptxsts = readl(hsotg->regs + GNPTXSTS); ++ nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) { + dev_vdbg(hsotg->dev, "Disabling channel\n"); + hcchar &= ~HCCHAR_CHENA; +@@ -1145,7 +1145,7 @@ + } else { + if (dbg_perio()) + dev_vdbg(hsotg->dev, "isoc/intr\n"); +- hptxsts = readl(hsotg->regs + HPTXSTS); ++ hptxsts = dwc2_readl(hsotg->regs + HPTXSTS); + if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 || + hsotg->queuing_high_bandwidth) { + if (dbg_perio()) +@@ -1158,7 +1158,7 @@ + dev_vdbg(hsotg->dev, "DMA enabled\n"); + } + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + chan->halt_status = halt_status; + + if (hcchar & HCCHAR_CHENA) { +@@ -1205,10 +1205,10 @@ + * Clear channel interrupt enables and any unhandled channel interrupt + * conditions + */ +- writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); ++ dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num)); + hcintmsk = 0xffffffff; + hcintmsk &= ~HCINTMSK_RESERVED14_31; +- writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); ++ dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num)); + } + + /** +@@ -1294,13 +1294,13 @@ + if (((unsigned long)data_buf & 0x3) == 0) { + /* xfer_buf is DWORD aligned */ + for (i = 0; i < dword_count; i++, data_buf++) +- writel(*data_buf, data_fifo); ++ dwc2_writel(*data_buf, data_fifo); + } else { + /* xfer_buf is not DWORD aligned */ + for (i = 0; i < dword_count; i++, data_buf++) { + u32 data = data_buf[0] | data_buf[1] << 8 | + data_buf[2] << 16 | data_buf[3] << 24; +- writel(data, data_fifo); ++ dwc2_writel(data, data_fifo); + } + } + +@@ -1453,7 +1453,7 @@ + hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK; + hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & + TSIZ_SC_MC_PID_MASK; +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + if (dbg_hc(chan)) { + dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n", + hctsiz, chan->hc_num); +@@ -1481,7 +1481,7 @@ + } else { + dma_addr = chan->xfer_dma; + } +- writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); ++ dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n", + (unsigned long)dma_addr, chan->hc_num); +@@ -1489,13 +1489,13 @@ + + /* Start the split */ + if (chan->do_split) { +- u32 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); ++ u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); + + hcsplt |= HCSPLT_SPLTENA; +- writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); ++ dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num)); + } + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar &= ~HCCHAR_MULTICNT_MASK; + hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & + HCCHAR_MULTICNT_MASK; +@@ -1515,7 +1515,7 @@ + (hcchar & HCCHAR_MULTICNT_MASK) >> + HCCHAR_MULTICNT_SHIFT); + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, + chan->hc_num); +@@ -1574,18 +1574,18 @@ + dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1); + } + +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + + hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK; + + /* Always start from first descriptor */ + hc_dma &= ~HCDMA_CTD_MASK; +- writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); ++ dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n", + hc_dma, chan->hc_num); + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar &= ~HCCHAR_MULTICNT_MASK; + hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & + HCCHAR_MULTICNT_MASK; +@@ -1604,7 +1604,7 @@ + (hcchar & HCCHAR_MULTICNT_MASK) >> + HCCHAR_MULTICNT_SHIFT); + +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, + chan->hc_num); +@@ -1661,7 +1661,7 @@ + * transfer completes, the extra requests for the channel will + * be flushed. + */ +- u32 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + + dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar); + hcchar |= HCCHAR_CHENA; +@@ -1669,7 +1669,7 @@ + if (dbg_hc(chan)) + dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n", + hcchar); +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + chan->requests++; + return 1; + } +@@ -1679,7 +1679,7 @@ + if (chan->xfer_count < chan->xfer_len) { + if (chan->ep_type == USB_ENDPOINT_XFER_INT || + chan->ep_type == USB_ENDPOINT_XFER_ISOC) { +- u32 hcchar = readl(hsotg->regs + ++ u32 hcchar = dwc2_readl(hsotg->regs + + HCCHAR(chan->hc_num)); + + dwc2_hc_set_even_odd_frame(hsotg, chan, +@@ -1716,12 +1716,12 @@ + + hctsiz = TSIZ_DOPNG; + hctsiz |= 1 << TSIZ_PKTCNT_SHIFT; +- writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); ++ dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num)); + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); + hcchar |= HCCHAR_CHENA; + hcchar &= ~HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num)); + } + + /** +@@ -1740,8 +1740,8 @@ + u32 hprt0; + int clock = 60; /* default value */ + +- usbcfg = readl(hsotg->regs + GUSBCFG); +- hprt0 = readl(hsotg->regs + HPRT0); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) && + !(usbcfg & GUSBCFG_PHYIF16)) +@@ -1797,7 +1797,7 @@ + dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes); + + for (i = 0; i < word_count; i++, data_buf++) +- *data_buf = readl(fifo); ++ *data_buf = dwc2_readl(fifo); + } + + /** +@@ -1817,56 +1817,56 @@ + dev_dbg(hsotg->dev, "Host Global Registers\n"); + addr = hsotg->regs + HCFG; + dev_dbg(hsotg->dev, "HCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HFIR; + dev_dbg(hsotg->dev, "HFIR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HFNUM; + dev_dbg(hsotg->dev, "HFNUM @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HPTXSTS; + dev_dbg(hsotg->dev, "HPTXSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HAINT; + dev_dbg(hsotg->dev, "HAINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HAINTMSK; + dev_dbg(hsotg->dev, "HAINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + if (hsotg->core_params->dma_desc_enable > 0) { + addr = hsotg->regs + HFLBADDR; + dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + } + + addr = hsotg->regs + HPRT0; + dev_dbg(hsotg->dev, "HPRT0 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + + for (i = 0; i < hsotg->core_params->host_channels; i++) { + dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i); + addr = hsotg->regs + HCCHAR(i); + dev_dbg(hsotg->dev, "HCCHAR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCSPLT(i); + dev_dbg(hsotg->dev, "HCSPLT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCINT(i); + dev_dbg(hsotg->dev, "HCINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCINTMSK(i); + dev_dbg(hsotg->dev, "HCINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCTSIZ(i); + dev_dbg(hsotg->dev, "HCTSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HCDMA(i); + dev_dbg(hsotg->dev, "HCDMA @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + if (hsotg->core_params->dma_desc_enable > 0) { + addr = hsotg->regs + HCDMAB(i); + dev_dbg(hsotg->dev, "HCDMAB @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + } + } + #endif +@@ -1888,80 +1888,80 @@ + dev_dbg(hsotg->dev, "Core Global Registers\n"); + addr = hsotg->regs + GOTGCTL; + dev_dbg(hsotg->dev, "GOTGCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GOTGINT; + dev_dbg(hsotg->dev, "GOTGINT @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GAHBCFG; + dev_dbg(hsotg->dev, "GAHBCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GUSBCFG; + dev_dbg(hsotg->dev, "GUSBCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRSTCTL; + dev_dbg(hsotg->dev, "GRSTCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GINTSTS; + dev_dbg(hsotg->dev, "GINTSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GINTMSK; + dev_dbg(hsotg->dev, "GINTMSK @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRXSTSR; + dev_dbg(hsotg->dev, "GRXSTSR @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GRXFSIZ; + dev_dbg(hsotg->dev, "GRXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GNPTXFSIZ; + dev_dbg(hsotg->dev, "GNPTXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GNPTXSTS; + dev_dbg(hsotg->dev, "GNPTXSTS @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GI2CCTL; + dev_dbg(hsotg->dev, "GI2CCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GPVNDCTL; + dev_dbg(hsotg->dev, "GPVNDCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GGPIO; + dev_dbg(hsotg->dev, "GGPIO @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GUID; + dev_dbg(hsotg->dev, "GUID @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GSNPSID; + dev_dbg(hsotg->dev, "GSNPSID @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG1; + dev_dbg(hsotg->dev, "GHWCFG1 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG2; + dev_dbg(hsotg->dev, "GHWCFG2 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG3; + dev_dbg(hsotg->dev, "GHWCFG3 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GHWCFG4; + dev_dbg(hsotg->dev, "GHWCFG4 @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GLPMCFG; + dev_dbg(hsotg->dev, "GLPMCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GPWRDN; + dev_dbg(hsotg->dev, "GPWRDN @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + GDFIFOCFG; + dev_dbg(hsotg->dev, "GDFIFOCFG @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + addr = hsotg->regs + HPTXFSIZ; + dev_dbg(hsotg->dev, "HPTXFSIZ @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + + addr = hsotg->regs + PCGCTL; + dev_dbg(hsotg->dev, "PCGCTL @0x%08lX : 0x%08X\n", +- (unsigned long)addr, readl(addr)); ++ (unsigned long)addr, dwc2_readl(addr)); + #endif + } + +@@ -1980,15 +1980,15 @@ + + greset = GRSTCTL_TXFFLSH; + greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + + do { +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 10000) { + dev_warn(hsotg->dev, + "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", + __func__, greset, +- readl(hsotg->regs + GNPTXSTS)); ++ dwc2_readl(hsotg->regs + GNPTXSTS)); + break; + } + udelay(1); +@@ -2011,10 +2011,10 @@ + dev_vdbg(hsotg->dev, "%s()\n", __func__); + + greset = GRSTCTL_RXFFLSH; +- writel(greset, hsotg->regs + GRSTCTL); ++ dwc2_writel(greset, hsotg->regs + GRSTCTL); + + do { +- greset = readl(hsotg->regs + GRSTCTL); ++ greset = dwc2_readl(hsotg->regs + GRSTCTL); + if (++count > 10000) { + dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n", + __func__, greset); +@@ -2676,7 +2676,7 @@ + * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3", + * as in "OTG version 2.xx" or "OTG version 3.xx". + */ +- hw->snpsid = readl(hsotg->regs + GSNPSID); ++ hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID); + if ((hw->snpsid & 0xfffff000) != 0x4f542000 && + (hw->snpsid & 0xfffff000) != 0x4f543000) { + dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", +@@ -2688,11 +2688,11 @@ + hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf, + hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid); + +- hwcfg1 = readl(hsotg->regs + GHWCFG1); +- hwcfg2 = readl(hsotg->regs + GHWCFG2); +- hwcfg3 = readl(hsotg->regs + GHWCFG3); +- hwcfg4 = readl(hsotg->regs + GHWCFG4); +- grxfsiz = readl(hsotg->regs + GRXFSIZ); ++ hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1); ++ hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2); ++ hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3); ++ hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4); ++ grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ); + + dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1); + dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2); +@@ -2701,18 +2701,18 @@ + dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz); + + /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */ +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg |= GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + usleep_range(100000, 150000); + +- gnptxfsiz = readl(hsotg->regs + GNPTXFSIZ); +- hptxfsiz = readl(hsotg->regs + HPTXFSIZ); ++ gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ); ++ hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ); + dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz); + dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz); +- gusbcfg = readl(hsotg->regs + GUSBCFG); ++ gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + gusbcfg &= ~GUSBCFG_FORCEHOSTMODE; +- writel(gusbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG); + usleep_range(100000, 150000); + + /* hwcfg2 */ +@@ -2831,7 +2831,7 @@ + + bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) + { +- if (readl(hsotg->regs + GSNPSID) == 0xffffffff) ++ if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff) + return false; + else + return true; +@@ -2845,10 +2845,10 @@ + */ + void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + ahbcfg |= GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + } + + /** +@@ -2859,10 +2859,10 @@ + */ + void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg) + { +- u32 ahbcfg = readl(hsotg->regs + GAHBCFG); ++ u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); + } + + MODULE_DESCRIPTION("DESIGNWARE HS OTG Core"); +--- a/drivers/usb/dwc2/core.h 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/core.h 2015-02-09 19:34:09.985105325 +0200 +@@ -44,16 +44,28 @@ + #include <linux/usb/phy.h> + #include "hw.h" + +-#ifdef DWC2_LOG_WRITES +-static inline void do_write(u32 value, void *addr) ++static inline u32 dwc2_readl(const void __iomem *addr) + { +- writel(value, addr); +- pr_info("INFO:: wrote %08x to %p\n", value, addr); ++ u32 value = __raw_readl(addr); ++ ++ /* In order to preserve endianness __raw_* operation is used. Therefore ++ a barrier is needed to ensure IO access is not re-ordered across ++ reads or writes */ ++ mb(); ++ return value; + } + +-#undef writel +-#define writel(v, a) do_write(v, a) ++static inline void dwc2_writel(u32 value, void __iomem *addr) ++{ ++ __raw_writel(value, addr); ++ /* In order to preserve endianness __raw_* operation is used. Therefore ++ a barrier is needed to ensure IO access is not re-ordered across ++ reads or writes */ ++ mb(); ++#ifdef DWC2_LOG_WRITES ++ pr_info("INFO:: wrote %08x to %p\n", value, addr); + #endif ++} + + /* Maximum number of Endpoints/HostChannels */ + #define MAX_EPS_CHANNELS 16 +--- a/drivers/usb/dwc2/core_intr.c 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/core_intr.c 2015-02-09 19:34:42.865106075 +0200 +@@ -80,15 +80,15 @@ + */ + static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg) + { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + if (hprt0 & HPRT0_ENACHG) { + hprt0 &= ~HPRT0_ENA; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + /* Clear interrupt */ +- writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS); + } + + /** +@@ -102,7 +102,7 @@ + dwc2_is_host_mode(hsotg) ? "Host" : "Device"); + + /* Clear interrupt */ +- writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); + } + + /** +@@ -117,8 +117,8 @@ + u32 gotgctl; + u32 gintmsk; + +- gotgint = readl(hsotg->regs + GOTGINT); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgint = dwc2_readl(hsotg->regs + GOTGINT); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint, + dwc2_op_state_str(hsotg)); + +@@ -126,7 +126,7 @@ + dev_dbg(hsotg->dev, + " ++OTG Interrupt: Session End Detected++ (%s)\n", + dwc2_op_state_str(hsotg)); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + + if (hsotg->op_state == OTG_STATE_B_HOST) { + hsotg->op_state = OTG_STATE_B_PERIPHERAL; +@@ -149,15 +149,15 @@ + hsotg->lx_state = DWC2_L0; + } + +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~GOTGCTL_DEVHNPEN; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + } + + if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) { + dev_dbg(hsotg->dev, + " ++OTG Interrupt: Session Request Success Status Change++\n"); +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + if (gotgctl & GOTGCTL_SESREQSCS) { + if (hsotg->core_params->phy_type == + DWC2_PHY_TYPE_PARAM_FS +@@ -165,9 +165,9 @@ + hsotg->srp_success = 1; + } else { + /* Clear Session Request */ +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~GOTGCTL_SESREQ; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + } + } + } +@@ -177,7 +177,7 @@ + * Print statements during the HNP interrupt handling + * can cause it to fail + */ +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + /* + * WA for 3.00a- HW is not setting cur_mode, even sometimes + * this does not help +@@ -197,9 +197,9 @@ + * interrupt does not get handled and Linux + * complains loudly. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + + /* + * Call callback function with spin lock +@@ -213,9 +213,9 @@ + hsotg->op_state = OTG_STATE_B_HOST; + } + } else { +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN); +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "HNP Failed\n"); + dev_err(hsotg->dev, + "Device Not Connected/Responding\n"); +@@ -241,9 +241,9 @@ + hsotg->op_state = OTG_STATE_A_PERIPHERAL; + } else { + /* Need to disable SOF interrupt immediately */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + spin_unlock(&hsotg->lock); + dwc2_hcd_start(hsotg); + spin_lock(&hsotg->lock); +@@ -258,7 +258,7 @@ + dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n"); + + /* Clear GOTGINT */ +- writel(gotgint, hsotg->regs + GOTGINT); ++ dwc2_writel(gotgint, hsotg->regs + GOTGINT); + } + + /** +@@ -273,11 +273,11 @@ + */ + static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg) + { +- u32 gintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + /* Need to disable SOF interrupt immediately */ + gintmsk &= ~GINTSTS_SOF; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + + dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n", + dwc2_is_host_mode(hsotg) ? "Host" : "Device"); +@@ -292,7 +292,7 @@ + spin_lock(&hsotg->lock); + + /* Clear interrupt */ +- writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); + } + + /** +@@ -311,7 +311,7 @@ + dev_dbg(hsotg->dev, "++Session Request Interrupt++\n"); + + /* Clear interrupt */ +- writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); + } + + /* +@@ -327,23 +327,23 @@ + dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state); + + if (dwc2_is_device_mode(hsotg)) { +- dev_dbg(hsotg->dev, "DSTS=0x%0x\n", readl(hsotg->regs + DSTS)); ++ dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dwc2_readl(hsotg->regs + DSTS)); + if (hsotg->lx_state == DWC2_L2) { +- u32 dctl = readl(hsotg->regs + DCTL); ++ u32 dctl = dwc2_readl(hsotg->regs + DCTL); + + /* Clear Remote Wakeup Signaling */ + dctl &= ~DCTL_RMTWKUPSIG; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + /* Change to L0 state */ + hsotg->lx_state = DWC2_L0; + } else { + if (hsotg->lx_state != DWC2_L1) { +- u32 pcgcctl = readl(hsotg->regs + PCGCTL); ++ u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL); + + /* Restart the Phy Clock */ + pcgcctl &= ~PCGCTL_STOPPCLK; +- writel(pcgcctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgcctl, hsotg->regs + PCGCTL); + mod_timer(&hsotg->wkp_timer, + jiffies + msecs_to_jiffies(71)); + } else { +@@ -353,7 +353,7 @@ + } + + /* Clear interrupt */ +- writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); + } + + /* +@@ -369,7 +369,7 @@ + /* Change to L3 (OFF) state */ + hsotg->lx_state = DWC2_L3; + +- writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS); + } + + /* +@@ -391,7 +391,7 @@ + * Check the Device status register to determine if the Suspend + * state is active + */ +- dsts = readl(hsotg->regs + DSTS); ++ dsts = dwc2_readl(hsotg->regs + DSTS); + dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts); + dev_dbg(hsotg->dev, + "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n", +@@ -413,7 +413,7 @@ + hsotg->lx_state = DWC2_L2; + + /* Clear interrupt */ +- writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); + } + + #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \ +@@ -431,9 +431,9 @@ + u32 gahbcfg; + u32 gintmsk_common = GINTMSK_COMMON; + +- gintsts = readl(hsotg->regs + GINTSTS); +- gintmsk = readl(hsotg->regs + GINTMSK); +- gahbcfg = readl(hsotg->regs + GAHBCFG); ++ gintsts = dwc2_readl(hsotg->regs + GINTSTS); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); ++ gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + /* If any common interrupts set */ + if (gintsts & gintmsk_common) +--- a/drivers/usb/dwc2/gadget.c 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/gadget.c 2015-02-09 19:34:42.891106076 +0200 +@@ -55,12 +55,12 @@ + + static inline void __orr32(void __iomem *ptr, u32 val) + { +- writel(readl(ptr) | val, ptr); ++ dwc2_writel(dwc2_readl(ptr) | val, ptr); + } + + static inline void __bic32(void __iomem *ptr, u32 val) + { +- writel(readl(ptr) & ~val, ptr); ++ dwc2_writel(dwc2_readl(ptr) & ~val, ptr); + } + + /* forward decleration of functions */ +@@ -97,14 +97,14 @@ + */ + static void s3c_hsotg_en_gsint(struct s3c_hsotg *hsotg, u32 ints) + { +- u32 gsintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 new_gsintmsk; + + new_gsintmsk = gsintmsk | ints; + + if (new_gsintmsk != gsintmsk) { + dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk); +- writel(new_gsintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); + } + } + +@@ -115,13 +115,13 @@ + */ + static void s3c_hsotg_disable_gsint(struct s3c_hsotg *hsotg, u32 ints) + { +- u32 gsintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK); + u32 new_gsintmsk; + + new_gsintmsk = gsintmsk & ~ints; + + if (new_gsintmsk != gsintmsk) +- writel(new_gsintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK); + } + + /** +@@ -146,12 +146,12 @@ + bit <<= 16; + + local_irq_save(flags); +- daint = readl(hsotg->regs + DAINTMSK); ++ daint = dwc2_readl(hsotg->regs + DAINTMSK); + if (en) + daint |= bit; + else + daint &= ~bit; +- writel(daint, hsotg->regs + DAINTMSK); ++ dwc2_writel(daint, hsotg->regs + DAINTMSK); + local_irq_restore(flags); + } + +@@ -169,8 +169,8 @@ + + /* set FIFO sizes to 2048/1024 */ + +- writel(2048, hsotg->regs + GRXFSIZ); +- writel((2048 << FIFOSIZE_STARTADDR_SHIFT) | ++ dwc2_writel(2048, hsotg->regs + GRXFSIZ); ++ dwc2_writel((2048 << FIFOSIZE_STARTADDR_SHIFT) | + (1024 << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ); + + /* +@@ -200,7 +200,7 @@ + "insufficient fifo memory"); + addr += size; + +- writel(val, hsotg->regs + DPTXFSIZN(ep)); ++ dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); + } + /* 768*4=3072 bytes FIFO length */ + size = 768; +@@ -211,7 +211,7 @@ + "insufficient fifo memory"); + addr += size; + +- writel(val, hsotg->regs + DPTXFSIZN(ep)); ++ dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep)); + } + + /* +@@ -219,13 +219,13 @@ + * all fifos are flushed before continuing + */ + +- writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | ++ dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | + GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL); + + /* wait until the fifos are both flushed */ + timeout = 100; + while (1) { +- val = readl(hsotg->regs + GRSTCTL); ++ val = dwc2_readl(hsotg->regs + GRSTCTL); + + if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) + break; +@@ -317,7 +317,7 @@ + struct s3c_hsotg_req *hs_req) + { + bool periodic = is_ep_periodic(hs_ep); +- u32 gnptxsts = readl(hsotg->regs + GNPTXSTS); ++ u32 gnptxsts = dwc2_readl(hsotg->regs + GNPTXSTS); + int buf_pos = hs_req->req.actual; + int to_write = hs_ep->size_loaded; + void *data; +@@ -332,7 +332,7 @@ + return 0; + + if (periodic && !hsotg->dedicated_fifos) { +- u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); ++ u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); + int size_left; + int size_done; + +@@ -373,7 +373,7 @@ + return -ENOSPC; + } + } else if (hsotg->dedicated_fifos && hs_ep->index != 0) { +- can_write = readl(hsotg->regs + DTXFSTS(hs_ep->index)); ++ can_write = dwc2_readl(hsotg->regs + DTXFSTS(hs_ep->index)); + + can_write &= 0xffff; + can_write *= 4; +@@ -550,11 +550,11 @@ + epsize_reg = dir_in ? DIEPTSIZ(index) : DOEPTSIZ(index); + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n", +- __func__, readl(hsotg->regs + epctrl_reg), index, ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg), index, + hs_ep->dir_in ? "in" : "out"); + + /* If endpoint is stalled, we will restart request later */ +- ctrl = readl(hsotg->regs + epctrl_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctrl_reg); + + if (ctrl & DXEPCTL_STALL) { + dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index); +@@ -622,7 +622,7 @@ + hs_ep->req = hs_req; + + /* write size / packets */ +- writel(epsize, hsotg->regs + epsize_reg); ++ dwc2_writel(epsize, hsotg->regs + epsize_reg); + + if (using_dma(hsotg) && !continuing) { + unsigned int dma_reg; +@@ -633,7 +633,7 @@ + */ + + dma_reg = dir_in ? DIEPDMA(index) : DOEPDMA(index); +- writel(ureq->dma, hsotg->regs + dma_reg); ++ dwc2_writel(ureq->dma, hsotg->regs + dma_reg); + + dev_dbg(hsotg->dev, "%s: %pad => 0x%08x\n", + __func__, &ureq->dma, dma_reg); +@@ -652,7 +652,7 @@ + + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); +- writel(ctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctrl_reg); + + /* + * set these, it seems that DMA support increments past the end +@@ -674,7 +674,7 @@ + * to debugging to see what is going on. + */ + if (dir_in) +- writel(DIEPMSK_INTKNTXFEMPMSK, ++ dwc2_writel(DIEPMSK_INTKNTXFEMPMSK, + hsotg->regs + DIEPINT(index)); + + /* +@@ -683,13 +683,13 @@ + */ + + /* check ep is enabled */ +- if (!(readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) ++ if (!(dwc2_readl(hsotg->regs + epctrl_reg) & DXEPCTL_EPENA)) + dev_warn(hsotg->dev, + "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n", +- index, readl(hsotg->regs + epctrl_reg)); ++ index, dwc2_readl(hsotg->regs + epctrl_reg)); + + dev_dbg(hsotg->dev, "%s: DXEPCTL=0x%08x\n", +- __func__, readl(hsotg->regs + epctrl_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg)); + + /* enable ep interrupts */ + s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 1); +@@ -1051,14 +1051,14 @@ + * taken effect, so no need to clear later. + */ + +- ctrl = readl(hsotg->regs + reg); ++ ctrl = dwc2_readl(hsotg->regs + reg); + ctrl |= DXEPCTL_STALL; + ctrl |= DXEPCTL_CNAK; +- writel(ctrl, hsotg->regs + reg); ++ dwc2_writel(ctrl, hsotg->regs + reg); + + dev_dbg(hsotg->dev, + "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n", +- ctrl, reg, readl(hsotg->regs + reg)); ++ ctrl, reg, dwc2_readl(hsotg->regs + reg)); + + /* + * complete won't be called, so we enqueue +@@ -1108,11 +1108,11 @@ + switch (ctrl->bRequest) { + case USB_REQ_SET_ADDRESS: + s3c_hsotg_disconnect(hsotg); +- dcfg = readl(hsotg->regs + DCFG); ++ dcfg = dwc2_readl(hsotg->regs + DCFG); + dcfg &= ~DCFG_DEVADDR_MASK; + dcfg |= (le16_to_cpu(ctrl->wValue) << + DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK; +- writel(dcfg, hsotg->regs + DCFG); ++ dwc2_writel(dcfg, hsotg->regs + DCFG); + + dev_info(hsotg->dev, "new address %d\n", ctrl->wValue); + +@@ -1302,7 +1302,7 @@ + + + if (!hs_req) { +- u32 epctl = readl(hsotg->regs + DOEPCTL(ep_idx)); ++ u32 epctl = dwc2_readl(hsotg->regs + DOEPCTL(ep_idx)); + int ptr; + + dev_warn(hsotg->dev, +@@ -1311,7 +1311,7 @@ + + /* dump the data from the FIFO, we've nothing we can do */ + for (ptr = 0; ptr < size; ptr += 4) +- (void)readl(fifo); ++ (void)dwc2_readl(fifo); + + return; + } +@@ -1378,14 +1378,14 @@ + dev_dbg(hsotg->dev, "sending zero-length packet\n"); + + /* issue a zero-sized packet to terminate this */ +- writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | ++ dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(0), hsotg->regs + DIEPTSIZ(0)); + +- ctrl = readl(hsotg->regs + DIEPCTL0); ++ ctrl = dwc2_readl(hsotg->regs + DIEPCTL0); + ctrl |= DXEPCTL_CNAK; /* clear NAK set by core */ + ctrl |= DXEPCTL_EPENA; /* ensure ep enabled */ + ctrl |= DXEPCTL_USBACTEP; +- writel(ctrl, hsotg->regs + DIEPCTL0); ++ dwc2_writel(ctrl, hsotg->regs + DIEPCTL0); + } + + /** +@@ -1401,7 +1401,7 @@ + static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg, + int epnum, bool was_setup) + { +- u32 epsize = readl(hsotg->regs + DOEPTSIZ(epnum)); ++ u32 epsize = dwc2_readl(hsotg->regs + DOEPTSIZ(epnum)); + struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum]; + struct s3c_hsotg_req *hs_req = hs_ep->req; + struct usb_request *req = &hs_req->req; +@@ -1475,7 +1475,7 @@ + { + u32 dsts; + +- dsts = readl(hsotg->regs + DSTS); ++ dsts = dwc2_readl(hsotg->regs + DSTS); + dsts &= DSTS_SOFFN_MASK; + dsts >>= DSTS_SOFFN_SHIFT; + +@@ -1500,7 +1500,7 @@ + */ + static void s3c_hsotg_handle_rx(struct s3c_hsotg *hsotg) + { +- u32 grxstsr = readl(hsotg->regs + GRXSTSP); ++ u32 grxstsr = dwc2_readl(hsotg->regs + GRXSTSP); + u32 epnum, status, size; + + WARN_ON(using_dma(hsotg)); +@@ -1532,7 +1532,7 @@ + dev_dbg(hsotg->dev, + "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n", + s3c_hsotg_read_frameno(hsotg), +- readl(hsotg->regs + DOEPCTL(0))); ++ dwc2_readl(hsotg->regs + DOEPCTL(0))); + + s3c_hsotg_handle_outdone(hsotg, epnum, true); + break; +@@ -1545,7 +1545,7 @@ + dev_dbg(hsotg->dev, + "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n", + s3c_hsotg_read_frameno(hsotg), +- readl(hsotg->regs + DOEPCTL(0))); ++ dwc2_readl(hsotg->regs + DOEPCTL(0))); + + s3c_hsotg_rx_data(hsotg, epnum, size); + break; +@@ -1622,16 +1622,16 @@ + * if one of the directions may not be in use. + */ + +- reg = readl(regs + DIEPCTL(ep)); ++ reg = dwc2_readl(regs + DIEPCTL(ep)); + reg &= ~DXEPCTL_MPS_MASK; + reg |= mpsval; +- writel(reg, regs + DIEPCTL(ep)); ++ dwc2_writel(reg, regs + DIEPCTL(ep)); + + if (ep) { +- reg = readl(regs + DOEPCTL(ep)); ++ reg = dwc2_readl(regs + DOEPCTL(ep)); + reg &= ~DXEPCTL_MPS_MASK; + reg |= mpsval; +- writel(reg, regs + DOEPCTL(ep)); ++ dwc2_writel(reg, regs + DOEPCTL(ep)); + } + + return; +@@ -1650,14 +1650,14 @@ + int timeout; + int val; + +- writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, ++ dwc2_writel(GRSTCTL_TXFNUM(idx) | GRSTCTL_TXFFLSH, + hsotg->regs + GRSTCTL); + + /* wait until the fifo is flushed */ + timeout = 100; + + while (1) { +- val = readl(hsotg->regs + GRSTCTL); ++ val = dwc2_readl(hsotg->regs + GRSTCTL); + + if ((val & (GRSTCTL_TXFFLSH)) == 0) + break; +@@ -1718,7 +1718,7 @@ + struct s3c_hsotg_ep *hs_ep) + { + struct s3c_hsotg_req *hs_req = hs_ep->req; +- u32 epsize = readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); ++ u32 epsize = dwc2_readl(hsotg->regs + DIEPTSIZ(hs_ep->index)); + int size_left, size_done; + + if (!hs_req) { +@@ -1801,11 +1801,11 @@ + u32 ints; + u32 ctrl; + +- ints = readl(hsotg->regs + epint_reg); +- ctrl = readl(hsotg->regs + epctl_reg); ++ ints = dwc2_readl(hsotg->regs + epint_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctl_reg); + + /* Clear endpoint interrupts */ +- writel(ints, hsotg->regs + epint_reg); ++ dwc2_writel(ints, hsotg->regs + epint_reg); + + dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n", + __func__, idx, dir_in ? "in" : "out", ints); +@@ -1816,13 +1816,13 @@ + ctrl |= DXEPCTL_SETEVENFR; + else + ctrl |= DXEPCTL_SETODDFR; +- writel(ctrl, hsotg->regs + epctl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctl_reg); + } + + dev_dbg(hsotg->dev, + "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n", +- __func__, readl(hsotg->regs + epctl_reg), +- readl(hsotg->regs + epsiz_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctl_reg), ++ dwc2_readl(hsotg->regs + epsiz_reg)); + + /* + * we get OutDone from the FIFO, so we only need to look +@@ -1847,16 +1847,16 @@ + dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__); + + if (dir_in) { +- int epctl = readl(hsotg->regs + epctl_reg); ++ int epctl = dwc2_readl(hsotg->regs + epctl_reg); + + s3c_hsotg_txfifo_flush(hsotg, hs_ep->fifo_index); + + if ((epctl & DXEPCTL_STALL) && + (epctl & DXEPCTL_EPTYPE_BULK)) { +- int dctl = readl(hsotg->regs + DCTL); ++ int dctl = dwc2_readl(hsotg->regs + DCTL); + + dctl |= DCTL_CGNPINNAK; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + } + } +@@ -1918,7 +1918,7 @@ + */ + static void s3c_hsotg_irq_enumdone(struct s3c_hsotg *hsotg) + { +- u32 dsts = readl(hsotg->regs + DSTS); ++ u32 dsts = dwc2_readl(hsotg->regs + DSTS); + int ep0_mps = 0, ep_mps = 8; + + /* +@@ -1979,8 +1979,8 @@ + s3c_hsotg_enqueue_setup(hsotg); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + } + + /** +@@ -2014,7 +2014,7 @@ + } + if (!hsotg->dedicated_fifos) + return; +- size = (readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; ++ size = (dwc2_readl(hsotg->regs + DTXFSTS(ep->index)) & 0xffff) * 4; + if (size < ep->fifo_size) + s3c_hsotg_txfifo_flush(hsotg, ep->fifo_index); + } +@@ -2084,11 +2084,11 @@ + dev_dbg(hsotg->dev, "resetting core\n"); + + /* issue soft reset */ +- writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); ++ dwc2_writel(GRSTCTL_CSFTRST, hsotg->regs + GRSTCTL); + + timeout = 10000; + do { +- grstctl = readl(hsotg->regs + GRSTCTL); ++ grstctl = dwc2_readl(hsotg->regs + GRSTCTL); + } while ((grstctl & GRSTCTL_CSFTRST) && timeout-- > 0); + + if (grstctl & GRSTCTL_CSFTRST) { +@@ -2099,7 +2099,7 @@ + timeout = 10000; + + while (1) { +- u32 grstctl = readl(hsotg->regs + GRSTCTL); ++ u32 grstctl = dwc2_readl(hsotg->regs + GRSTCTL); + + if (timeout-- < 0) { + dev_info(hsotg->dev, +@@ -2134,22 +2134,22 @@ + */ + + /* set the PLL on, remove the HNP/SRP and set the PHY */ +- writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | ++ dwc2_writel(hsotg->phyif | GUSBCFG_TOUTCAL(7) | + (0x5 << 10), hsotg->regs + GUSBCFG); + + s3c_hsotg_init_fifo(hsotg); + + __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); + +- writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); ++ dwc2_writel(1 << 18 | DCFG_DEVSPD_HS, hsotg->regs + DCFG); + + /* Clear any pending OTG interrupts */ +- writel(0xffffffff, hsotg->regs + GOTGINT); ++ dwc2_writel(0xffffffff, hsotg->regs + GOTGINT); + + /* Clear any pending interrupts */ +- writel(0xffffffff, hsotg->regs + GINTSTS); ++ dwc2_writel(0xffffffff, hsotg->regs + GINTSTS); + +- writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | ++ dwc2_writel(GINTSTS_ERLYSUSP | GINTSTS_SESSREQINT | + GINTSTS_GOUTNAKEFF | GINTSTS_GINNAKEFF | + GINTSTS_CONIDSTSCHNG | GINTSTS_USBRST | + GINTSTS_ENUMDONE | GINTSTS_OTGINT | +@@ -2157,11 +2157,11 @@ + hsotg->regs + GINTMSK); + + if (using_dma(hsotg)) +- writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | ++ dwc2_writel(GAHBCFG_GLBL_INTR_EN | GAHBCFG_DMA_EN | + GAHBCFG_HBSTLEN_INCR4, + hsotg->regs + GAHBCFG); + else +- writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | ++ dwc2_writel(((hsotg->dedicated_fifos) ? (GAHBCFG_NP_TXF_EMP_LVL | + GAHBCFG_P_TXF_EMP_LVL) : 0) | + GAHBCFG_GLBL_INTR_EN, + hsotg->regs + GAHBCFG); +@@ -2172,7 +2172,7 @@ + * interrupts. + */ + +- writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY | ++ dwc2_writel(((hsotg->dedicated_fifos) ? DIEPMSK_TXFIFOEMPTY | + DIEPMSK_INTKNTXFEMPMSK : 0) | + DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK | + DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | +@@ -2183,17 +2183,17 @@ + * don't need XferCompl, we get that from RXFIFO in slave mode. In + * DMA mode we may need this. + */ +- writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | ++ dwc2_writel((using_dma(hsotg) ? (DIEPMSK_XFERCOMPLMSK | + DIEPMSK_TIMEOUTMSK) : 0) | + DOEPMSK_EPDISBLDMSK | DOEPMSK_AHBERRMSK | + DOEPMSK_SETUPMSK, + hsotg->regs + DOEPMSK); + +- writel(0, hsotg->regs + DAINTMSK); ++ dwc2_writel(0, hsotg->regs + DAINTMSK); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + + /* enable in and out endpoint interrupts */ + s3c_hsotg_en_gsint(hsotg, GINTSTS_OEPINT | GINTSTS_IEPINT); +@@ -2214,7 +2214,7 @@ + udelay(10); /* see openiboot */ + __bic32(hsotg->regs + DCTL, DCTL_PWRONPRGDONE); + +- dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + DCTL)); ++ dev_dbg(hsotg->dev, "DCTL=0x%08x\n", dwc2_readl(hsotg->regs + DCTL)); + + /* + * DxEPCTL_USBActEp says RO in manual, but seems to be set by +@@ -2222,26 +2222,26 @@ + */ + + /* set to read 1 8byte packet */ +- writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | ++ dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) | + DXEPTSIZ_XFERSIZE(8), hsotg->regs + DOEPTSIZ0); + +- writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | ++ dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | + DXEPCTL_CNAK | DXEPCTL_EPENA | + DXEPCTL_USBACTEP, + hsotg->regs + DOEPCTL0); + + /* enable, but don't activate EP0in */ +- writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | ++ dwc2_writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) | + DXEPCTL_USBACTEP, hsotg->regs + DIEPCTL0); + + s3c_hsotg_enqueue_setup(hsotg); + + dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n", +- readl(hsotg->regs + DIEPCTL0), +- readl(hsotg->regs + DOEPCTL0)); ++ dwc2_readl(hsotg->regs + DIEPCTL0), ++ dwc2_readl(hsotg->regs + DOEPCTL0)); + + /* clear global NAKs */ +- writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK, ++ dwc2_writel(DCTL_CGOUTNAK | DCTL_CGNPINNAK, + hsotg->regs + DCTL); + + /* must be at-least 3ms to allow bus to see disconnect */ +@@ -2265,8 +2265,8 @@ + + spin_lock(&hsotg->lock); + irq_retry: +- gintsts = readl(hsotg->regs + GINTSTS); +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintsts = dwc2_readl(hsotg->regs + GINTSTS); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + dev_dbg(hsotg->dev, "%s: %08x %08x (%08x) retry %d\n", + __func__, gintsts, gintsts & gintmsk, gintmsk, retry_count); +@@ -2274,35 +2274,35 @@ + gintsts &= gintmsk; + + if (gintsts & GINTSTS_OTGINT) { +- u32 otgint = readl(hsotg->regs + GOTGINT); ++ u32 otgint = dwc2_readl(hsotg->regs + GOTGINT); + + dev_info(hsotg->dev, "OTGInt: %08x\n", otgint); + +- writel(otgint, hsotg->regs + GOTGINT); ++ dwc2_writel(otgint, hsotg->regs + GOTGINT); + } + + if (gintsts & GINTSTS_SESSREQINT) { + dev_dbg(hsotg->dev, "%s: SessReqInt\n", __func__); +- writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS); + } + + if (gintsts & GINTSTS_ENUMDONE) { +- writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_ENUMDONE, hsotg->regs + GINTSTS); + + s3c_hsotg_irq_enumdone(hsotg); + } + + if (gintsts & GINTSTS_CONIDSTSCHNG) { + dev_dbg(hsotg->dev, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n", +- readl(hsotg->regs + DSTS), +- readl(hsotg->regs + GOTGCTL)); ++ dwc2_readl(hsotg->regs + DSTS), ++ dwc2_readl(hsotg->regs + GOTGCTL)); + +- writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS); + } + + if (gintsts & (GINTSTS_OEPINT | GINTSTS_IEPINT)) { +- u32 daint = readl(hsotg->regs + DAINT); +- u32 daintmsk = readl(hsotg->regs + DAINTMSK); ++ u32 daint = dwc2_readl(hsotg->regs + DAINT); ++ u32 daintmsk = dwc2_readl(hsotg->regs + DAINTMSK); + u32 daint_out, daint_in; + int ep; + +@@ -2325,13 +2325,13 @@ + + if (gintsts & GINTSTS_USBRST) { + +- u32 usb_status = readl(hsotg->regs + GOTGCTL); ++ u32 usb_status = dwc2_readl(hsotg->regs + GOTGCTL); + + dev_dbg(hsotg->dev, "%s: USBRst\n", __func__); + dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n", +- readl(hsotg->regs + GNPTXSTS)); ++ dwc2_readl(hsotg->regs + GNPTXSTS)); + +- writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_USBRST, hsotg->regs + GINTSTS); + + if (usb_status & GOTGCTL_BSESVLD) { + if (time_after(jiffies, hsotg->last_rst + +@@ -2382,26 +2382,26 @@ + + if (gintsts & GINTSTS_MODEMIS) { + dev_warn(hsotg->dev, "warning, mode mismatch triggered\n"); +- writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS); + } + + if (gintsts & GINTSTS_USBSUSP) { + dev_info(hsotg->dev, "GINTSTS_USBSusp\n"); +- writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS); + + call_gadget(hsotg, suspend); + } + + if (gintsts & GINTSTS_WKUPINT) { + dev_info(hsotg->dev, "GINTSTS_WkUpIn\n"); +- writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS); + + call_gadget(hsotg, resume); + } + + if (gintsts & GINTSTS_ERLYSUSP) { + dev_dbg(hsotg->dev, "GINTSTS_ErlySusp\n"); +- writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_ERLYSUSP, hsotg->regs + GINTSTS); + } + + /* +@@ -2413,7 +2413,7 @@ + if (gintsts & GINTSTS_GOUTNAKEFF) { + dev_info(hsotg->dev, "GOUTNakEff triggered\n"); + +- writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); ++ dwc2_writel(DCTL_CGOUTNAK, hsotg->regs + DCTL); + + s3c_hsotg_dump(hsotg); + } +@@ -2421,7 +2421,7 @@ + if (gintsts & GINTSTS_GINNAKEFF) { + dev_info(hsotg->dev, "GINNakEff triggered\n"); + +- writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); ++ dwc2_writel(DCTL_CGNPINNAK, hsotg->regs + DCTL); + + s3c_hsotg_dump(hsotg); + } +@@ -2479,7 +2479,7 @@ + /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */ + + epctrl_reg = dir_in ? DIEPCTL(index) : DOEPCTL(index); +- epctrl = readl(hsotg->regs + epctrl_reg); ++ epctrl = dwc2_readl(hsotg->regs + epctrl_reg); + + dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x from 0x%08x\n", + __func__, epctrl, epctrl_reg); +@@ -2550,7 +2550,7 @@ + for (i = 1; i <= 8; ++i) { + if (hsotg->fifo_map & (1<<i)) + continue; +- val = readl(hsotg->regs + DPTXFSIZN(i)); ++ val = dwc2_readl(hsotg->regs + DPTXFSIZN(i)); + val = (val >> FIFOSIZE_DEPTH_SHIFT)*4; + if (val < size) + continue; +@@ -2574,9 +2574,9 @@ + dev_dbg(hsotg->dev, "%s: write DxEPCTL=0x%08x\n", + __func__, epctrl); + +- writel(epctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(epctrl, hsotg->regs + epctrl_reg); + dev_dbg(hsotg->dev, "%s: read DxEPCTL=0x%08x\n", +- __func__, readl(hsotg->regs + epctrl_reg)); ++ __func__, dwc2_readl(hsotg->regs + epctrl_reg)); + + /* enable the endpoint interrupt */ + s3c_hsotg_ctrl_epint(hsotg, index, dir_in, 1); +@@ -2617,13 +2617,13 @@ + hs_ep->fifo_index = 0; + hs_ep->fifo_size = 0; + +- ctrl = readl(hsotg->regs + epctrl_reg); ++ ctrl = dwc2_readl(hsotg->regs + epctrl_reg); + ctrl &= ~DXEPCTL_EPENA; + ctrl &= ~DXEPCTL_USBACTEP; + ctrl |= DXEPCTL_SNAK; + + dev_dbg(hsotg->dev, "%s: DxEPCTL=0x%08x\n", __func__, ctrl); +- writel(ctrl, hsotg->regs + epctrl_reg); ++ dwc2_writel(ctrl, hsotg->regs + epctrl_reg); + + /* disable endpoint interrupts */ + s3c_hsotg_ctrl_epint(hsotg, hs_ep->index, hs_ep->dir_in, 0); +@@ -2704,7 +2704,7 @@ + /* write both IN and OUT control registers */ + + epreg = DIEPCTL(index); +- epctl = readl(hs->regs + epreg); ++ epctl = dwc2_readl(hs->regs + epreg); + + if (value) { + epctl |= DXEPCTL_STALL + DXEPCTL_SNAK; +@@ -2718,10 +2718,10 @@ + epctl |= DXEPCTL_SETD0PID; + } + +- writel(epctl, hs->regs + epreg); ++ dwc2_writel(epctl, hs->regs + epreg); + + epreg = DOEPCTL(index); +- epctl = readl(hs->regs + epreg); ++ epctl = dwc2_readl(hs->regs + epreg); + + if (value) + epctl |= DXEPCTL_STALL; +@@ -2733,7 +2733,7 @@ + epctl |= DXEPCTL_SETD0PID; + } + +- writel(epctl, hs->regs + epreg); ++ dwc2_writel(epctl, hs->regs + epreg); + + hs_ep->halted = value; + +@@ -2822,38 +2822,38 @@ + { + /* unmask subset of endpoint interrupts */ + +- writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | ++ dwc2_writel(DIEPMSK_TIMEOUTMSK | DIEPMSK_AHBERRMSK | + DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK, + hsotg->regs + DIEPMSK); + +- writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | ++ dwc2_writel(DOEPMSK_SETUPMSK | DOEPMSK_AHBERRMSK | + DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK, + hsotg->regs + DOEPMSK); + +- writel(0, hsotg->regs + DAINTMSK); ++ dwc2_writel(0, hsotg->regs + DAINTMSK); + + /* Be in disconnected state until gadget is registered */ + __orr32(hsotg->regs + DCTL, DCTL_SFTDISCON); + + if (0) { + /* post global nak until we're ready */ +- writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK, ++ dwc2_writel(DCTL_SGNPINNAK | DCTL_SGOUTNAK, + hsotg->regs + DCTL); + } + + /* setup fifos */ + + dev_dbg(hsotg->dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", +- readl(hsotg->regs + GRXFSIZ), +- readl(hsotg->regs + GNPTXFSIZ)); ++ dwc2_readl(hsotg->regs + GRXFSIZ), ++ dwc2_readl(hsotg->regs + GNPTXFSIZ)); + + s3c_hsotg_init_fifo(hsotg); + + /* set the PLL on, remove the HNP/SRP and set the PHY */ +- writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), ++ dwc2_writel(GUSBCFG_PHYIF16 | GUSBCFG_TOUTCAL(7) | (0x5 << 10), + hsotg->regs + GUSBCFG); + +- writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0, ++ dwc2_writel(using_dma(hsotg) ? GAHBCFG_DMA_EN : 0x0, + hsotg->regs + GAHBCFG); + } + +@@ -3045,8 +3045,8 @@ + + if (using_dma(hsotg)) { + u32 next = DXEPCTL_NEXTEP((epnum + 1) % 15); +- writel(next, hsotg->regs + DIEPCTL(epnum)); +- writel(next, hsotg->regs + DOEPCTL(epnum)); ++ dwc2_writel(next, hsotg->regs + DIEPCTL(epnum)); ++ dwc2_writel(next, hsotg->regs + DOEPCTL(epnum)); + } + } + +@@ -3061,13 +3061,13 @@ + u32 cfg2, cfg3, cfg4; + /* check hardware configuration */ + +- cfg2 = readl(hsotg->regs + 0x48); ++ cfg2 = dwc2_readl(hsotg->regs + 0x48); + hsotg->num_of_eps = (cfg2 >> 10) & 0xF; + +- cfg3 = readl(hsotg->regs + 0x4C); ++ cfg3 = dwc2_readl(hsotg->regs + 0x4C); + hsotg->fifo_mem = (cfg3 >> 16); + +- cfg4 = readl(hsotg->regs + 0x50); ++ cfg4 = dwc2_readl(hsotg->regs + 0x50); + hsotg->dedicated_fifos = (cfg4 >> 25) & 1; + + dev_info(hsotg->dev, "EPs: %d, %s fifos, %d entries in SPRAM\n", +@@ -3089,19 +3089,19 @@ + int idx; + + dev_info(dev, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n", +- readl(regs + DCFG), readl(regs + DCTL), +- readl(regs + DIEPMSK)); ++ dwc2_readl(regs + DCFG), dwc2_readl(regs + DCTL), ++ dwc2_readl(regs + DIEPMSK)); + + dev_info(dev, "GAHBCFG=0x%08x, 0x44=0x%08x\n", +- readl(regs + GAHBCFG), readl(regs + 0x44)); ++ dwc2_readl(regs + GAHBCFG), dwc2_readl(regs + 0x44)); + + dev_info(dev, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n", +- readl(regs + GRXFSIZ), readl(regs + GNPTXFSIZ)); ++ dwc2_readl(regs + GRXFSIZ), dwc2_readl(regs + GNPTXFSIZ)); + + /* show periodic fifo settings */ + + for (idx = 1; idx <= 15; idx++) { +- val = readl(regs + DPTXFSIZN(idx)); ++ val = dwc2_readl(regs + DPTXFSIZN(idx)); + dev_info(dev, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx, + val >> FIFOSIZE_DEPTH_SHIFT, + val & FIFOSIZE_STARTADDR_MASK); +@@ -3110,21 +3110,21 @@ + for (idx = 0; idx < 15; idx++) { + dev_info(dev, + "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx, +- readl(regs + DIEPCTL(idx)), +- readl(regs + DIEPTSIZ(idx)), +- readl(regs + DIEPDMA(idx))); ++ dwc2_readl(regs + DIEPCTL(idx)), ++ dwc2_readl(regs + DIEPTSIZ(idx)), ++ dwc2_readl(regs + DIEPDMA(idx))); + +- val = readl(regs + DOEPCTL(idx)); ++ val = dwc2_readl(regs + DOEPCTL(idx)); + dev_info(dev, + "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", +- idx, readl(regs + DOEPCTL(idx)), +- readl(regs + DOEPTSIZ(idx)), +- readl(regs + DOEPDMA(idx))); ++ idx, dwc2_readl(regs + DOEPCTL(idx)), ++ dwc2_readl(regs + DOEPTSIZ(idx)), ++ dwc2_readl(regs + DOEPDMA(idx))); + + } + + dev_info(dev, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n", +- readl(regs + DVBUSDIS), readl(regs + DVBUSPULSE)); ++ dwc2_readl(regs + DVBUSDIS), dwc2_readl(regs + DVBUSPULSE)); + #endif + } + +@@ -3144,38 +3144,38 @@ + int idx; + + seq_printf(seq, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n", +- readl(regs + DCFG), +- readl(regs + DCTL), +- readl(regs + DSTS)); ++ dwc2_readl(regs + DCFG), ++ dwc2_readl(regs + DCTL), ++ dwc2_readl(regs + DSTS)); + + seq_printf(seq, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n", +- readl(regs + DIEPMSK), readl(regs + DOEPMSK)); ++ dwc2_readl(regs + DIEPMSK), dwc2_readl(regs + DOEPMSK)); + + seq_printf(seq, "GINTMSK=0x%08x, GINTSTS=0x%08x\n", +- readl(regs + GINTMSK), +- readl(regs + GINTSTS)); ++ dwc2_readl(regs + GINTMSK), ++ dwc2_readl(regs + GINTSTS)); + + seq_printf(seq, "DAINTMSK=0x%08x, DAINT=0x%08x\n", +- readl(regs + DAINTMSK), +- readl(regs + DAINT)); ++ dwc2_readl(regs + DAINTMSK), ++ dwc2_readl(regs + DAINT)); + + seq_printf(seq, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n", +- readl(regs + GNPTXSTS), +- readl(regs + GRXSTSR)); ++ dwc2_readl(regs + GNPTXSTS), ++ dwc2_readl(regs + GRXSTSR)); + + seq_puts(seq, "\nEndpoint status:\n"); + + for (idx = 0; idx < 15; idx++) { + u32 in, out; + +- in = readl(regs + DIEPCTL(idx)); +- out = readl(regs + DOEPCTL(idx)); ++ in = dwc2_readl(regs + DIEPCTL(idx)); ++ out = dwc2_readl(regs + DOEPCTL(idx)); + + seq_printf(seq, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x", + idx, in, out); + +- in = readl(regs + DIEPTSIZ(idx)); +- out = readl(regs + DOEPTSIZ(idx)); ++ in = dwc2_readl(regs + DIEPTSIZ(idx)); ++ out = dwc2_readl(regs + DOEPTSIZ(idx)); + + seq_printf(seq, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x", + in, out); +@@ -3215,9 +3215,9 @@ + int idx; + + seq_puts(seq, "Non-periodic FIFOs:\n"); +- seq_printf(seq, "RXFIFO: Size %d\n", readl(regs + GRXFSIZ)); ++ seq_printf(seq, "RXFIFO: Size %d\n", dwc2_readl(regs + GRXFSIZ)); + +- val = readl(regs + GNPTXFSIZ); ++ val = dwc2_readl(regs + GNPTXFSIZ); + seq_printf(seq, "NPTXFIFO: Size %d, Start 0x%08x\n", + val >> FIFOSIZE_DEPTH_SHIFT, + val & FIFOSIZE_DEPTH_MASK); +@@ -3225,7 +3225,7 @@ + seq_puts(seq, "\nPeriodic TXFIFOs:\n"); + + for (idx = 1; idx <= 15; idx++) { +- val = readl(regs + DPTXFSIZN(idx)); ++ val = dwc2_readl(regs + DPTXFSIZN(idx)); + + seq_printf(seq, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx, + val >> FIFOSIZE_DEPTH_SHIFT, +@@ -3278,20 +3278,20 @@ + /* first show the register state */ + + seq_printf(seq, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n", +- readl(regs + DIEPCTL(index)), +- readl(regs + DOEPCTL(index))); ++ dwc2_readl(regs + DIEPCTL(index)), ++ dwc2_readl(regs + DOEPCTL(index))); + + seq_printf(seq, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n", +- readl(regs + DIEPDMA(index)), +- readl(regs + DOEPDMA(index))); ++ dwc2_readl(regs + DIEPDMA(index)), ++ dwc2_readl(regs + DOEPDMA(index))); + + seq_printf(seq, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n", +- readl(regs + DIEPINT(index)), +- readl(regs + DOEPINT(index))); ++ dwc2_readl(regs + DIEPINT(index)), ++ dwc2_readl(regs + DOEPINT(index))); + + seq_printf(seq, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n", +- readl(regs + DIEPTSIZ(index)), +- readl(regs + DOEPTSIZ(index))); ++ dwc2_readl(regs + DIEPTSIZ(index)), ++ dwc2_readl(regs + DOEPTSIZ(index))); + + seq_puts(seq, "\n"); + seq_printf(seq, "mps %d\n", ep->ep.maxpacket); +--- a/drivers/usb/dwc2/hcd.c 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/hcd.c 2015-02-09 19:34:42.911106076 +0200 +@@ -80,10 +80,10 @@ + if (chan == NULL) + return; + +- hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num)); +- hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num)); +- hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num)); ++ hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num)); + + dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan); + dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", +@@ -207,7 +207,7 @@ + */ + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, +@@ -228,11 +228,11 @@ + channel = hsotg->hc_ptr_array[i]; + if (!list_empty(&channel->hc_list_entry)) + continue; +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR); + hcchar |= HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + } + } +@@ -241,11 +241,11 @@ + channel = hsotg->hc_ptr_array[i]; + if (!list_empty(&channel->hc_list_entry)) + continue; +- hcchar = readl(hsotg->regs + HCCHAR(i)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); + if (hcchar & HCCHAR_CHENA) { + /* Halt the channel */ + hcchar |= HCCHAR_CHDIS; +- writel(hcchar, hsotg->regs + HCCHAR(i)); ++ dwc2_writel(hcchar, hsotg->regs + HCCHAR(i)); + } + + dwc2_hc_cleanup(hsotg, channel); +@@ -279,11 +279,11 @@ + * interrupt mask and status bits and disabling subsequent host + * channel interrupts. + */ +- intr = readl(hsotg->regs + GINTMSK); ++ intr = dwc2_readl(hsotg->regs + GINTMSK); + intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT); +- writel(intr, hsotg->regs + GINTMSK); ++ dwc2_writel(intr, hsotg->regs + GINTMSK); + intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT; +- writel(intr, hsotg->regs + GINTSTS); ++ dwc2_writel(intr, hsotg->regs + GINTSTS); + + /* + * Turn off the vbus power only if the core has transitioned to device +@@ -293,7 +293,7 @@ + if (dwc2_is_device_mode(hsotg)) { + if (hsotg->op_state != OTG_STATE_A_SUSPEND) { + dev_dbg(hsotg->dev, "Disconnect: PortPower off\n"); +- writel(0, hsotg->regs + HPRT0); ++ dwc2_writel(0, hsotg->regs + HPRT0); + } + + dwc2_disable_host_interrupts(hsotg); +@@ -344,7 +344,7 @@ + + /* Turn off the vbus power */ + dev_dbg(hsotg->dev, "PortPower off\n"); +- writel(0, hsotg->regs + HPRT0); ++ dwc2_writel(0, hsotg->regs + HPRT0); + } + + static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg, +@@ -369,7 +369,7 @@ + if ((dev_speed == USB_SPEED_LOW) && + (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) && + (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + + if (prtspd == HPRT0_SPD_FULL_SPEED) +@@ -391,7 +391,7 @@ + return retval; + } + +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + if (!(intr_mask & GINTSTS_SOF)) { + enum dwc2_transaction_type tr_type; + +@@ -1059,7 +1059,7 @@ + if (dbg_perio()) + dev_vdbg(hsotg->dev, "Queue periodic transactions\n"); + +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1074,7 +1074,7 @@ + + qh_ptr = hsotg->periodic_sched_assigned.next; + while (qh_ptr != &hsotg->periodic_sched_assigned) { +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + if (qspcavail == 0) { +@@ -1134,7 +1134,7 @@ + } + + if (hsotg->core_params->dma_enable <= 0) { +- tx_status = readl(hsotg->regs + HPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1157,9 +1157,9 @@ + * level to ensure that new requests are loaded as + * soon as possible.) + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are +@@ -1168,9 +1168,9 @@ + * handlers to queue more transactions as transfer + * states change. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1199,7 +1199,7 @@ + + dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n"); + +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1222,7 +1222,7 @@ + * available in the request queue or the Tx FIFO + */ + do { +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) { +@@ -1259,7 +1259,7 @@ + } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr); + + if (hsotg->core_params->dma_enable <= 0) { +- tx_status = readl(hsotg->regs + GNPTXSTS); ++ tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >> + TXSTS_QSPCAVAIL_SHIFT; + fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >> +@@ -1279,9 +1279,9 @@ + * level to ensure that new requests are loaded as + * soon as possible.) + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + /* + * Disable the Tx FIFO empty interrupt since there are +@@ -1290,9 +1290,9 @@ + * handlers to queue more transactions as transfer + * states change. + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk &= ~GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1330,10 +1330,10 @@ + * Ensure NP Tx FIFO empty interrupt is disabled when + * there are no non-periodic transfers to process + */ +- u32 gintmsk = readl(hsotg->regs + GINTMSK); ++ u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + + gintmsk &= ~GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -1347,7 +1347,7 @@ + + dev_dbg(hsotg->dev, "%s()\n", __func__); + +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl); + dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n", + !!(gotgctl & GOTGCTL_CONID_B)); +@@ -1408,9 +1408,9 @@ + hprt0 = dwc2_read_hprt0(hsotg); + dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0); + hprt0 &= ~HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n", +- readl(hsotg->regs + HPRT0)); ++ dwc2_readl(hsotg->regs + HPRT0)); + + dwc2_hcd_rem_wakeup(hsotg); + +@@ -1438,30 +1438,30 @@ + spin_lock_irqsave(&hsotg->lock, flags); + + if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) { +- gotgctl = readl(hsotg->regs + GOTGCTL); ++ gotgctl = dwc2_readl(hsotg->regs + GOTGCTL); + gotgctl |= GOTGCTL_HSTSETHNPEN; +- writel(gotgctl, hsotg->regs + GOTGCTL); ++ dwc2_writel(gotgctl, hsotg->regs + GOTGCTL); + hsotg->op_state = OTG_STATE_A_SUSPEND; + } + + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_SUSP; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + + /* Update lx_state */ + hsotg->lx_state = DWC2_L2; + + /* Suspend the Phy Clock */ +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl |= PCGCTL_STOPPCLK; +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + udelay(10); + + /* For HNP the bus must be suspended for at least 200ms */ + if (dwc2_host_is_b_hnp_enabled(hsotg)) { +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~PCGCTL_STOPPCLK; +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + + spin_unlock_irqrestore(&hsotg->lock, flags); + +@@ -1510,23 +1510,23 @@ + "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_ENA; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_SUSPEND: + dev_dbg(hsotg->dev, + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + usleep_range(20000, 40000); + + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hprt0 &= ~HPRT0_SUSP; + usleep_range(100000, 150000); + + hprt0 &= ~HPRT0_RES; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_POWER: +@@ -1534,7 +1534,7 @@ + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 &= ~HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_INDICATOR: +@@ -1653,7 +1653,7 @@ + break; + } + +- hprt0 = readl(hsotg->regs + HPRT0); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0); + + if (hprt0 & HPRT0_CONNSTS) +@@ -1718,18 +1718,18 @@ + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 |= HPRT0_PWR; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + break; + + case USB_PORT_FEAT_RESET: + hprt0 = dwc2_read_hprt0(hsotg); + dev_dbg(hsotg->dev, + "SetPortFeature - USB_PORT_FEAT_RESET\n"); +- pcgctl = readl(hsotg->regs + PCGCTL); ++ pcgctl = dwc2_readl(hsotg->regs + PCGCTL); + pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK); +- writel(pcgctl, hsotg->regs + PCGCTL); ++ dwc2_writel(pcgctl, hsotg->regs + PCGCTL); + /* ??? Original driver does this */ +- writel(0, hsotg->regs + PCGCTL); ++ dwc2_writel(0, hsotg->regs + PCGCTL); + + hprt0 = dwc2_read_hprt0(hsotg); + /* Clear suspend bit if resetting from suspend state */ +@@ -1744,13 +1744,13 @@ + hprt0 |= HPRT0_PWR | HPRT0_RST; + dev_dbg(hsotg->dev, + "In host mode, hprt0=%08x\n", hprt0); +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + } + + /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ + usleep_range(50000, 70000); + hprt0 &= ~HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hsotg->lx_state = DWC2_L0; /* Now back to On state */ + break; + +@@ -1814,7 +1814,7 @@ + + int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg) + { +- u32 hfnum = readl(hsotg->regs + HFNUM); ++ u32 hfnum = dwc2_readl(hsotg->regs + HFNUM); + + #ifdef DWC2_DEBUG_SOF + dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n", +@@ -1917,11 +1917,11 @@ + if (chan->xfer_started) { + u32 hfnum, hcchar, hctsiz, hcint, hcintmsk; + +- hfnum = readl(hsotg->regs + HFNUM); +- hcchar = readl(hsotg->regs + HCCHAR(i)); +- hctsiz = readl(hsotg->regs + HCTSIZ(i)); +- hcint = readl(hsotg->regs + HCINT(i)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(i)); ++ hfnum = dwc2_readl(hsotg->regs + HFNUM); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(i)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i)); ++ hcint = dwc2_readl(hsotg->regs + HCINT(i)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i)); + dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum); + dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar); + dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz); +@@ -1969,12 +1969,12 @@ + dev_dbg(hsotg->dev, " periodic_channels: %d\n", + hsotg->periodic_channels); + dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs); +- np_tx_status = readl(hsotg->regs + GNPTXSTS); ++ np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS); + dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n", + (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); + dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n", + (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT); +- p_tx_status = readl(hsotg->regs + HPTXSTS); ++ p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS); + dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n", + (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT); + dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n", +@@ -2238,7 +2238,7 @@ + dev_dbg(hsotg->dev, "USB RESET function called\n"); + hprt0 = dwc2_read_hprt0(hsotg); + hprt0 &= ~HPRT0_RST; +- writel(hprt0, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0, hsotg->regs + HPRT0); + hsotg->flags.b.port_reset_change = 1; + } + +@@ -2715,17 +2715,17 @@ + hsotg->status_buf = NULL; + } + +- ahbcfg = readl(hsotg->regs + GAHBCFG); ++ ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG); + + /* Disable all interrupts */ + ahbcfg &= ~GAHBCFG_GLBL_INTR_EN; +- writel(ahbcfg, hsotg->regs + GAHBCFG); +- writel(0, hsotg->regs + GINTMSK); ++ dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG); ++ dwc2_writel(0, hsotg->regs + GINTMSK); + + if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) { +- dctl = readl(hsotg->regs + DCTL); ++ dctl = dwc2_readl(hsotg->regs + DCTL); + dctl |= DCTL_SFTDISCON; +- writel(dctl, hsotg->regs + DCTL); ++ dwc2_writel(dctl, hsotg->regs + DCTL); + } + + if (hsotg->wq_otg) { +@@ -2788,7 +2788,7 @@ + + retval = -ENOMEM; + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg); + + #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS +--- a/drivers/usb/dwc2/hcd_ddma.c 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/hcd_ddma.c 2015-02-09 19:34:42.921106076 +0200 +@@ -169,19 +169,19 @@ + + spin_lock_irqsave(&hsotg->lock, flags); + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + if (hcfg & HCFG_PERSCHEDENA) { + /* already enabled */ + spin_unlock_irqrestore(&hsotg->lock, flags); + return; + } + +- writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); ++ dwc2_writel(hsotg->frame_list_dma, hsotg->regs + HFLBADDR); + + hcfg &= ~HCFG_FRLISTEN_MASK; + hcfg |= fr_list_en | HCFG_PERSCHEDENA; + dev_vdbg(hsotg->dev, "Enabling Periodic schedule\n"); +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + + spin_unlock_irqrestore(&hsotg->lock, flags); + } +@@ -193,7 +193,7 @@ + + spin_lock_irqsave(&hsotg->lock, flags); + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + if (!(hcfg & HCFG_PERSCHEDENA)) { + /* already disabled */ + spin_unlock_irqrestore(&hsotg->lock, flags); +@@ -202,7 +202,7 @@ + + hcfg &= ~HCFG_PERSCHEDENA; + dev_vdbg(hsotg->dev, "Disabling Periodic schedule\n"); +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + + spin_unlock_irqrestore(&hsotg->lock, flags); + } +--- a/drivers/usb/dwc2/hcd.h 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/hcd.h 2015-02-09 19:34:42.949106077 +0200 +@@ -371,10 +371,10 @@ + */ + static inline void disable_hc_int(struct dwc2_hsotg *hsotg, int chnum, u32 intr) + { +- u32 mask = readl(hsotg->regs + HCINTMSK(chnum)); ++ u32 mask = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + + mask &= ~intr; +- writel(mask, hsotg->regs + HCINTMSK(chnum)); ++ dwc2_writel(mask, hsotg->regs + HCINTMSK(chnum)); + } + + /* +@@ -382,11 +382,11 @@ + */ + static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg) + { +- return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; ++ return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0; + } + static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg) + { +- return (readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; ++ return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0; + } + + /* +@@ -395,7 +395,7 @@ + */ + static inline u32 dwc2_read_hprt0(struct dwc2_hsotg *hsotg) + { +- u32 hprt0 = readl(hsotg->regs + HPRT0); ++ u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0); + + hprt0 &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG | HPRT0_OVRCURRCHG); + return hprt0; +@@ -582,7 +582,7 @@ + */ + static inline u32 dwc2_read_core_intr(struct dwc2_hsotg *hsotg) + { +- return readl(hsotg->regs + GINTSTS) & readl(hsotg->regs + GINTMSK); ++ return dwc2_readl(hsotg->regs + GINTSTS) & dwc2_readl(hsotg->regs + GINTMSK); + } + + static inline u32 dwc2_hcd_urb_get_status(struct dwc2_hcd_urb *dwc2_urb) +@@ -744,7 +744,7 @@ + qtd_list_entry); \ + if (usb_pipeint(_qtd_->urb->pipe) && \ + (_qh_)->start_split_frame != 0 && !_qtd_->complete_split) { \ +- _hfnum_.d32 = readl((_hcd_)->regs + HFNUM); \ ++ _hfnum_.d32 = dwc2_readl((_hcd_)->regs + HFNUM); \ + switch (_hfnum_.b.frnum & 0x7) { \ + case 7: \ + (_hcd_)->hfnum_7_samples_##_letter_++; \ +--- a/drivers/usb/dwc2/hcd_intr.c 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/hcd_intr.c 2015-02-09 19:34:42.935106077 +0200 +@@ -148,7 +148,7 @@ + dwc2_hcd_queue_transactions(hsotg, tr_type); + + /* Clear interrupt */ +- writel(GINTSTS_SOF, hsotg->regs + GINTSTS); ++ dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS); + } + + /* +@@ -164,7 +164,7 @@ + if (dbg_perio()) + dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n"); + +- grxsts = readl(hsotg->regs + GRXSTSP); ++ grxsts = dwc2_readl(hsotg->regs + GRXSTSP); + chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT; + chan = hsotg->hc_ptr_array[chnum]; + if (!chan) { +@@ -247,11 +247,11 @@ + dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg); + + /* Every time when port enables calculate HFIR.FrInterval */ +- hfir = readl(hsotg->regs + HFIR); ++ hfir = dwc2_readl(hsotg->regs + HFIR); + hfir &= ~HFIR_FRINT_MASK; + hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT & + HFIR_FRINT_MASK; +- writel(hfir, hsotg->regs + HFIR); ++ dwc2_writel(hfir, hsotg->regs + HFIR); + + /* Check if we need to adjust the PHY clock speed for low power */ + if (!params->host_support_fs_ls_low_power) { +@@ -260,7 +260,7 @@ + return; + } + +- usbcfg = readl(hsotg->regs + GUSBCFG); ++ usbcfg = dwc2_readl(hsotg->regs + GUSBCFG); + prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + + if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) { +@@ -268,11 +268,11 @@ + if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) { + /* Set PHY low power clock select for FS/LS devices */ + usbcfg |= GUSBCFG_PHY_LP_CLK_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + do_reset = 1; + } + +- hcfg = readl(hsotg->regs + HCFG); ++ hcfg = dwc2_readl(hsotg->regs + HCFG); + fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >> + HCFG_FSLSPCLKSEL_SHIFT; + +@@ -286,7 +286,7 @@ + fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ; + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + do_reset = 1; + } + } else { +@@ -297,7 +297,7 @@ + fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ; + hcfg &= ~HCFG_FSLSPCLKSEL_MASK; + hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT; +- writel(hcfg, hsotg->regs + HCFG); ++ dwc2_writel(hcfg, hsotg->regs + HCFG); + do_reset = 1; + } + } +@@ -305,7 +305,7 @@ + /* Not low power */ + if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) { + usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL; +- writel(usbcfg, hsotg->regs + GUSBCFG); ++ dwc2_writel(usbcfg, hsotg->regs + GUSBCFG); + do_reset = 1; + } + } +@@ -332,7 +332,7 @@ + + dev_vdbg(hsotg->dev, "--Port Interrupt--\n"); + +- hprt0 = readl(hsotg->regs + HPRT0); ++ hprt0 = dwc2_readl(hsotg->regs + HPRT0); + hprt0_modify = hprt0; + + /* +@@ -385,7 +385,7 @@ + } + + /* Clear Port Interrupts */ +- writel(hprt0_modify, hsotg->regs + HPRT0); ++ dwc2_writel(hprt0_modify, hsotg->regs + HPRT0); + } + + /* +@@ -405,7 +405,7 @@ + { + u32 hctsiz, count, length; + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + + if (halt_status == DWC2_HC_XFER_COMPLETE) { + if (chan->ep_is_in) { +@@ -483,7 +483,7 @@ + urb->status = 0; + } + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", + __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); + dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len); +@@ -506,7 +506,7 @@ + struct dwc2_host_chan *chan, int chnum, + struct dwc2_qtd *qtd) + { +- u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT; + + if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) { +@@ -753,9 +753,9 @@ + } + } + +- haintmsk = readl(hsotg->regs + HAINTMSK); ++ haintmsk = dwc2_readl(hsotg->regs + HAINTMSK); + haintmsk &= ~(1 << chan->hc_num); +- writel(haintmsk, hsotg->regs + HAINTMSK); ++ dwc2_writel(haintmsk, hsotg->regs + HAINTMSK); + + /* Try to queue more transfers now that there's a free channel */ + tr_type = dwc2_hcd_select_transactions(hsotg); +@@ -802,9 +802,9 @@ + * is enabled so that the non-periodic schedule will + * be processed + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_NPTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } else { + dev_vdbg(hsotg->dev, "isoc/intr\n"); + /* +@@ -821,9 +821,9 @@ + * enabled so that the periodic schedule will be + * processed + */ +- gintmsk = readl(hsotg->regs + GINTMSK); ++ gintmsk = dwc2_readl(hsotg->regs + GINTMSK); + gintmsk |= GINTSTS_PTXFEMP; +- writel(gintmsk, hsotg->regs + GINTMSK); ++ dwc2_writel(gintmsk, hsotg->regs + GINTMSK); + } + } + } +@@ -888,7 +888,7 @@ + struct dwc2_qtd *qtd, + enum dwc2_halt_status halt_status) + { +- u32 hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + + qtd->error_count = 0; + +@@ -1158,7 +1158,7 @@ + + urb->actual_length += xfer_length; + +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); + dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n", + __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum); + dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n", +@@ -1469,10 +1469,10 @@ + + dwc2_hc_handle_tt_clear(hsotg, chan, qtd); + +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); +- hcsplt = readl(hsotg->regs + HCSPLT(chnum)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); +- hc_dma = readl(hsotg->regs + HCDMA(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); ++ hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum)); + + dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum); + dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt); +@@ -1685,10 +1685,10 @@ + * This code is here only as a check. This condition should + * never happen. Ignore the halt if it does occur. + */ +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); +- hctsiz = readl(hsotg->regs + HCTSIZ(chnum)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); +- hcsplt = readl(hsotg->regs + HCSPLT(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); ++ hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); ++ hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum)); + dev_dbg(hsotg->dev, + "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n", + __func__); +@@ -1712,7 +1712,7 @@ + * when the halt interrupt occurs. Halt the channel again if it does + * occur. + */ +- hcchar = readl(hsotg->regs + HCCHAR(chnum)); ++ hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum)); + if (hcchar & HCCHAR_CHDIS) { + dev_warn(hsotg->dev, + "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n", +@@ -1772,7 +1772,7 @@ + return; + } + +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + + if (chan->hcint & HCINTMSK_XFERCOMPL) { + /* +@@ -1867,7 +1867,7 @@ + dev_err(hsotg->dev, + "hcint 0x%08x, intsts 0x%08x\n", + chan->hcint, +- readl(hsotg->regs + GINTSTS)); ++ dwc2_readl(hsotg->regs + GINTSTS)); + goto error; + } + } +@@ -1922,11 +1922,11 @@ + + chan = hsotg->hc_ptr_array[chnum]; + +- hcint = readl(hsotg->regs + HCINT(chnum)); +- hcintmsk = readl(hsotg->regs + HCINTMSK(chnum)); ++ hcint = dwc2_readl(hsotg->regs + HCINT(chnum)); ++ hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum)); + if (!chan) { + dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n"); +- writel(hcint, hsotg->regs + HCINT(chnum)); ++ dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + return; + } + +@@ -1938,7 +1938,7 @@ + hcint, hcintmsk, hcint & hcintmsk); + } + +- writel(hcint, hsotg->regs + HCINT(chnum)); ++ dwc2_writel(hcint, hsotg->regs + HCINT(chnum)); + chan->hcint = hcint; + hcint &= hcintmsk; + +@@ -2030,7 +2030,7 @@ + u32 haint; + int i; + +- haint = readl(hsotg->regs + HAINT); ++ haint = dwc2_readl(hsotg->regs + HAINT); + if (dbg_perio()) { + dev_vdbg(hsotg->dev, "%s()\n", __func__); + +@@ -2098,8 +2098,8 @@ + "DWC OTG HCD Finished Servicing Interrupts\n"); + dev_vdbg(hsotg->dev, + "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n", +- readl(hsotg->regs + GINTSTS), +- readl(hsotg->regs + GINTMSK)); ++ dwc2_readl(hsotg->regs + GINTSTS), ++ dwc2_readl(hsotg->regs + GINTMSK)); + } + } + +--- a/drivers/usb/dwc2/hcd_queue.c 2015-02-06 16:53:48.000000000 +0200 ++++ b/drivers/usb/dwc2/hcd_queue.c 2015-02-09 19:34:42.941106077 +0200 +@@ -115,7 +115,7 @@ + if (qh->ep_type == USB_ENDPOINT_XFER_INT) + qh->interval = 8; + #endif +- hprt = readl(hsotg->regs + HPRT0); ++ hprt = dwc2_readl(hsotg->regs + HPRT0); + prtspd = (hprt & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT; + if (prtspd == HPRT0_SPD_HIGH_SPEED && + (dev_speed == USB_SPEED_LOW || +@@ -593,9 +593,9 @@ + if (status) + return status; + if (!hsotg->periodic_qh_count) { +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask |= GINTSTS_SOF; +- writel(intr_mask, hsotg->regs + GINTMSK); ++ dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + } + hsotg->periodic_qh_count++; + +@@ -630,9 +630,9 @@ + dwc2_deschedule_periodic(hsotg, qh); + hsotg->periodic_qh_count--; + if (!hsotg->periodic_qh_count) { +- intr_mask = readl(hsotg->regs + GINTMSK); ++ intr_mask = dwc2_readl(hsotg->regs + GINTMSK); + intr_mask &= ~GINTSTS_SOF; +- writel(intr_mask, hsotg->regs + GINTMSK); ++ dwc2_writel(intr_mask, hsotg->regs + GINTMSK); + } + } + |