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-rw-r--r--target/linux/generic/patches-3.18/020-ssb_update.patch55
-rw-r--r--target/linux/generic/patches-4.0/020-ssb_update.patch29
2 files changed, 84 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.18/020-ssb_update.patch b/target/linux/generic/patches-3.18/020-ssb_update.patch
index 9171b24704..7afba07763 100644
--- a/target/linux/generic/patches-3.18/020-ssb_update.patch
+++ b/target/linux/generic/patches-3.18/020-ssb_update.patch
@@ -76,3 +76,58 @@
return pci_register_driver(driver);
}
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -357,6 +357,15 @@ static void ssb_pcicore_init_hostmode(st
+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
+ SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
+
++ /*
++ * Accessing PCI config without a proper delay after devices reset (not
++ * GPIO reset) was causing reboots on WRT300N v1.0.
++ * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it
++ * completely. Flushing all writes was also tested but with no luck.
++ */
++ if (pc->dev->bus->chip_id == 0x4704)
++ usleep_range(1000, 2000);
++
+ /* Enable PCI bridge BAR0 prefetch and burst */
+ val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -90,25 +90,6 @@ found:
+ }
+ #endif /* CONFIG_SSB_PCMCIAHOST */
+
+-#ifdef CONFIG_SSB_SDIOHOST
+-struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
+-{
+- struct ssb_bus *bus;
+-
+- ssb_buses_lock();
+- list_for_each_entry(bus, &buses, list) {
+- if (bus->bustype == SSB_BUSTYPE_SDIO &&
+- bus->host_sdio == func)
+- goto found;
+- }
+- bus = NULL;
+-found:
+- ssb_buses_unlock();
+-
+- return bus;
+-}
+-#endif /* CONFIG_SSB_SDIOHOST */
+-
+ int ssb_for_each_bus_call(unsigned long data,
+ int (*func)(struct ssb_bus *bus, unsigned long data))
+ {
+@@ -1154,6 +1135,8 @@ static u32 ssb_tmslow_reject_bitmask(str
+ case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
+ case SSB_IDLOW_SSBREV_27: /* same here */
+ return SSB_TMSLOW_REJECT; /* this is a guess */
++ case SSB_IDLOW_SSBREV:
++ break;
+ default:
+ WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+ }
diff --git a/target/linux/generic/patches-4.0/020-ssb_update.patch b/target/linux/generic/patches-4.0/020-ssb_update.patch
new file mode 100644
index 0000000000..946cb3b106
--- /dev/null
+++ b/target/linux/generic/patches-4.0/020-ssb_update.patch
@@ -0,0 +1,29 @@
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -357,6 +357,15 @@ static void ssb_pcicore_init_hostmode(st
+ pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
+ SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
+
++ /*
++ * Accessing PCI config without a proper delay after devices reset (not
++ * GPIO reset) was causing reboots on WRT300N v1.0.
++ * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it
++ * completely. Flushing all writes was also tested but with no luck.
++ */
++ if (pc->dev->bus->chip_id == 0x4704)
++ usleep_range(1000, 2000);
++
+ /* Enable PCI bridge BAR0 prefetch and burst */
+ val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
+--- a/drivers/ssb/main.c
++++ b/drivers/ssb/main.c
+@@ -1135,6 +1135,8 @@ static u32 ssb_tmslow_reject_bitmask(str
+ case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
+ case SSB_IDLOW_SSBREV_27: /* same here */
+ return SSB_TMSLOW_REJECT; /* this is a guess */
++ case SSB_IDLOW_SSBREV:
++ break;
+ default:
+ WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
+ }