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-rw-r--r--target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch27
1 files changed, 0 insertions, 27 deletions
diff --git a/target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch b/target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch
deleted file mode 100644
index 269a0fbf6c..0000000000
--- a/target/linux/cns3xxx/patches-3.3/066-pcie_bus_topology.patch
+++ /dev/null
@@ -1,27 +0,0 @@
---- a/arch/arm/mach-cns3xxx/pcie.c
-+++ b/arch/arm/mach-cns3xxx/pcie.c
-@@ -79,9 +79,11 @@ static void __iomem *cns3xxx_pci_cfg_bas
- * the first device on the same bus as the CNS PCI bridge.
- */
- if (busno == 0) {
-- if (slot > 1)
-+ if (slot > 0)
- return NULL;
- type = slot;
-+ } else if (busno == 1) {
-+ type = CNS3XXX_CFG0_TYPE;
- } else {
- type = CNS3XXX_CFG1_TYPE;
- }
-@@ -428,8 +430,9 @@ static void __init cns3xxx_pcie_hw_init(
- if (!cnspci->linked)
- return;
-
-- /* Set Device Max_Read_Request_Size to 128 byte */
-- devfn = PCI_DEVFN(1, 0);
-+ /* Configure Root Complex: Set Device Max_Read_Request_Size to 128 byte */
-+ bus.number = 1;
-+ devfn = PCI_DEVFN(0, 0);
- pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
- pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
- dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */