diff options
Diffstat (limited to 'target/linux')
| -rw-r--r-- | target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c | 16 | ||||
| -rw-r--r-- | target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h | 6 |
2 files changed, 22 insertions, 0 deletions
diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c index a9ca85c7f5..6ef255db4b 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/dsa.c @@ -162,6 +162,16 @@ static void rtl83xx_setup_bpdu_traps(struct rtl838x_switch_priv *priv) priv->r->set_receive_management_action(i, BPDU, COPY2CPU); } +static void rtl83xx_port_set_salrn(struct rtl838x_switch_priv *priv, + int port, bool enable) +{ + int shift = SALRN_PORT_SHIFT(port); + int val = enable ? SALRN_MODE_HARDWARE : SALRN_MODE_DISABLED; + + sw_w32_mask(SALRN_MODE_MASK << shift, val << shift, + priv->r->l2_port_new_salrn(port)); +} + static int rtl83xx_setup(struct dsa_switch *ds) { int i; @@ -205,6 +215,9 @@ static int rtl83xx_setup(struct dsa_switch *ds) priv->r->l2_learning_setup(); + rtl83xx_port_set_salrn(priv, priv->cpu_port, false); + ds->assisted_learning_on_cpu_port = true; + /* * Make sure all frames sent to the switch's MAC are trapped to the CPU-port * 0: FWD, 1: DROP, 2: TRAP2CPU @@ -263,6 +276,9 @@ static int rtl93xx_setup(struct dsa_switch *ds) priv->r->l2_learning_setup(); + rtl83xx_port_set_salrn(priv, priv->cpu_port, false); + ds->assisted_learning_on_cpu_port = true; + rtl83xx_enable_phy_polling(priv); priv->r->pie_init(priv); diff --git a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h index e2b82a4975..10913dacef 100644 --- a/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h +++ b/target/linux/realtek/files-5.10/drivers/net/dsa/rtl83xx/rtl838x.h @@ -245,6 +245,12 @@ #define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2))) #define RTL930X_L2_PORT_SALRN(p) (0x8FEC + (((p >> 4) << 2))) #define RTL931X_L2_PORT_NEW_SALRN(p) (0xC820 + (((p >> 4) << 2))) + +#define SALRN_PORT_SHIFT(p) ((p % 16) * 2) +#define SALRN_MODE_MASK 0x3 +#define SALRN_MODE_HARDWARE 0 +#define SALRN_MODE_DISABLED 2 + #define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2))) #define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2))) #define RTL930X_L2_PORT_NEW_SA_FWD(p) (0x8FF4 + (((p / 10) << 2))) |