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-rw-r--r--target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch73
1 files changed, 73 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch b/target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch
new file mode 100644
index 0000000000..6a6c828937
--- /dev/null
+++ b/target/linux/imx6/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch
@@ -0,0 +1,73 @@
+From 62e7f0b553038e3a1a1b2b067dd1fbdacd634e37 Mon Sep 17 00:00:00 2001
+From: Robert Jones <rjones@gateworks.com>
+Date: Fri, 14 Feb 2020 13:02:41 -0800
+Subject: [PATCH] ARM: dts: imx6qdl-gw553x: add lsm9ds1 iio imu/magn support
+
+Add one node for the accel/gyro i2c device and another for the separate
+magnetometer device in the lsm9ds1.
+
+Signed-off-by: Robert Jones <rjones@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 31 +++++++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
+index a106689..ee85031 100644
+--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
+@@ -173,6 +173,25 @@
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
++ magn@1c {
++ compatible = "st,lsm9ds1-magn";
++ reg = <0x1c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mag>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
++ };
++
++ imu@6a {
++ compatible = "st,lsm9ds1-imu";
++ reg = <0x6a>;
++ st,drdy-int-pin = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_imu>;
++ interrupt-parent = <&gpio7>;
++ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
+ ltc3676: pmic@3c {
+ compatible = "lltc,ltc3676";
+ reg = <0x3c>;
+@@ -426,6 +445,12 @@
+ >;
+ };
+
++ pinctrl_imu: imugrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
++ >;
++ };
++
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+@@ -449,6 +474,12 @@
+ >;
+ };
+
++ pinctrl_mag: maggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
++ >;
++ };
++
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
+--
+2.7.4
+