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-rw-r--r--target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR-defines.patch27
-rw-r--r--target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR_BW-defines.patch12
-rw-r--r--target/linux/ppc40x/patches/004-magicbox.patch8
-rw-r--r--target/linux/ppc40x/patches/005-openrb.patch8
4 files changed, 37 insertions, 18 deletions
diff --git a/target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR-defines.patch b/target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR-defines.patch
new file mode 100644
index 0000000000..ca70f7223c
--- /dev/null
+++ b/target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR-defines.patch
@@ -0,0 +1,27 @@
+--- a/arch/powerpc/boot/dcr.h
++++ b/arch/powerpc/boot/dcr.h
+@@ -49,6 +49,14 @@ static const unsigned long sdram_bxcr[]
+ #define EBC_BXCR(n) (n)
+ #define EBC_BXCR_BAS 0xfff00000
+ #define EBC_BXCR_BS 0x000e0000
++#define EBC_BXCR_BS_1M 0x00000000
++#define EBC_BXCR_BS_2M 0x00020000
++#define EBC_BXCR_BS_4M 0x00040000
++#define EBC_BXCR_BS_8M 0x00060000
++#define EBC_BXCR_BS_16M 0x00080000
++#define EBC_BXCR_BS_32M 0x000a0000
++#define EBC_BXCR_BS_64M 0x000c0000
++#define EBC_BXCR_BS_128M 0x000e0000
+ #define EBC_BXCR_BANK_SIZE(reg) \
+ (0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
+ #define EBC_BXCR_BU 0x00018000
+@@ -57,6 +65,9 @@ static const unsigned long sdram_bxcr[]
+ #define EBC_BXCR_BU_WO 0x00010000
+ #define EBC_BXCR_BU_RW 0x00018000
+ #define EBC_BXCR_BW 0x00006000
++#define EBC_BXCR_BW_8 0x00000000
++#define EBC_BXCR_BW_16 0x00002000
++#define EBC_BXCR_BW_32 0x00006000
+ #define EBC_B0AP 0x10
+ #define EBC_B1AP 0x11
+ #define EBC_B2AP 0x12
diff --git a/target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR_BW-defines.patch b/target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR_BW-defines.patch
deleted file mode 100644
index 8e380c1c9c..0000000000
--- a/target/linux/ppc40x/patches/003-powerpc-add-EBC_BXCR_BW-defines.patch
+++ /dev/null
@@ -1,12 +0,0 @@
---- a/arch/powerpc/boot/dcr.h
-+++ b/arch/powerpc/boot/dcr.h
-@@ -57,6 +57,9 @@ static const unsigned long sdram_bxcr[]
- #define EBC_BXCR_BU_WO 0x00010000
- #define EBC_BXCR_BU_RW 0x00018000
- #define EBC_BXCR_BW 0x00006000
-+#define EBC_BXCR_BW_8 0x00000000
-+#define EBC_BXCR_BW_16 0x00002000
-+#define EBC_BXCR_BW_32 0x00006000
- #define EBC_B0AP 0x10
- #define EBC_B1AP 0x11
- #define EBC_B2AP 0x12
diff --git a/target/linux/ppc40x/patches/004-magicbox.patch b/target/linux/ppc40x/patches/004-magicbox.patch
index 8de4a11b57..2797424211 100644
--- a/target/linux/ppc40x/patches/004-magicbox.patch
+++ b/target/linux/ppc40x/patches/004-magicbox.patch
@@ -1,6 +1,6 @@
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-magicbox.c
-@@ -0,0 +1,96 @@
+@@ -0,0 +1,98 @@
+/*
+ * Old U-boot compatibility for Magicbox boards
+ *
@@ -44,13 +44,15 @@
+
+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
-+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
++ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BS_1M |
++ EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
-+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
++ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BS_1M |
++ EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
diff --git a/target/linux/ppc40x/patches/005-openrb.patch b/target/linux/ppc40x/patches/005-openrb.patch
index 17a6bb12ce..e7dab6f36a 100644
--- a/target/linux/ppc40x/patches/005-openrb.patch
+++ b/target/linux/ppc40x/patches/005-openrb.patch
@@ -1,6 +1,6 @@
--- /dev/null
+++ b/arch/powerpc/boot/cuboot-openrb.c
-@@ -0,0 +1,77 @@
+@@ -0,0 +1,79 @@
+/*
+ * Old U-boot compatibility for OpenRB boards
+ *
@@ -44,13 +44,15 @@
+
+ /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
-+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
++ mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BS_1M |
++ EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+
+ /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
-+ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
++ mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BS_1M |
++ EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
+ mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
+ mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
+