diff options
Diffstat (limited to 'target/linux')
22 files changed, 17723 insertions, 53 deletions
diff --git a/target/linux/lantiq/Makefile b/target/linux/lantiq/Makefile index a9109c8cdb..ffe8e1b9f2 100644 --- a/target/linux/lantiq/Makefile +++ b/target/linux/lantiq/Makefile @@ -6,9 +6,8 @@ # include $(TOPDIR)/rules.mk -ARCH:=mips BOARD:=lantiq -BOARDNAME:=Lantiq GPON/XWAY +BOARDNAME:=Lantiq GPON/XWAY/SVIP FEATURES:=squashfs jffs2 DEFAULT_SUBTARGET:=danube diff --git a/target/linux/lantiq/ar9/config-default b/target/linux/lantiq/ar9/config-default index 0ed3f4abf7..67b6a46094 100644 --- a/target/linux/lantiq/ar9/config-default +++ b/target/linux/lantiq/ar9/config-default @@ -35,5 +35,6 @@ CONFIG_RTL8306_PHY=y # CONFIG_SOC_FALCON is not set CONFIG_SOC_TYPE_XWAY=y CONFIG_SOC_XWAY=y +# CONFIG_SOC_SVIP is not set CONFIG_USB_ARCH_HAS_XHCI=y CONFIG_USB_SUPPORT=y diff --git a/target/linux/lantiq/ase/config-default b/target/linux/lantiq/ase/config-default index 33db8103b1..bb3abdf397 100644 --- a/target/linux/lantiq/ase/config-default +++ b/target/linux/lantiq/ase/config-default @@ -15,6 +15,7 @@ CONFIG_SOC_AMAZON_SE=y # CONFIG_SOC_FALCON is not set CONFIG_SOC_TYPE_XWAY=y # CONFIG_SOC_XWAY is not set +# CONFIG_SOC_SVIP is not set # CONFIG_USB_ARCH_HAS_EHCI is not set # CONFIG_USB_ARCH_HAS_OHCI is not set # CONFIG_USB_ARCH_HAS_XHCI is not set diff --git a/target/linux/lantiq/danube/config-default b/target/linux/lantiq/danube/config-default index c211dc0faf..822969a0cb 100644 --- a/target/linux/lantiq/danube/config-default +++ b/target/linux/lantiq/danube/config-default @@ -31,6 +31,7 @@ CONFIG_PCI_LANTIQ=y CONFIG_RTL8306_PHY=y # CONFIG_SOC_AMAZON_SE is not set # CONFIG_SOC_FALCON is not set +# CONFIG_SOC_SVIP is not set CONFIG_SOC_TYPE_XWAY=y CONFIG_SOC_XWAY=y CONFIG_USB_ARCH_HAS_XHCI=y diff --git a/target/linux/lantiq/falcon/config-default b/target/linux/lantiq/falcon/config-default index 491857507c..55231ea870 100644 --- a/target/linux/lantiq/falcon/config-default +++ b/target/linux/lantiq/falcon/config-default @@ -14,6 +14,7 @@ CONFIG_MTD_NAND_PLATFORM=y CONFIG_SOC_FALCON=y # CONFIG_SOC_TYPE_XWAY is not set # CONFIG_SOC_XWAY is not set +# CONFIG_SOC_SVIP is not set CONFIG_SPI=y CONFIG_SPI_FALCON=y CONFIG_SPI_MASTER=y diff --git a/target/linux/lantiq/image/Makefile b/target/linux/lantiq/image/Makefile index 0ef73f1997..96179a5bc1 100644 --- a/target/linux/lantiq/image/Makefile +++ b/target/linux/lantiq/image/Makefile @@ -12,6 +12,7 @@ JFFS2_BLOCKSIZE = 64k 128k 256k ase_cmdline=-console=ttyLTQ0,115200 rootfstype=squashfs,jffs2 xway_cmdline=-console=ttyLTQ1,115200 rootfstype=squashfs,jffs2 falcon_cmdline=-console=ttyLTQ0,115200 rootfstype=squashfs,jffs2 +svip_cmdline=-console=ttyLTQ0,115200 rootfstype=squashfs,jffs2 sx76x_cmdline=console=ttyLTQ1,115200 rootfstype=squashfs,jffs2 define CompressLzma @@ -42,6 +43,22 @@ define MkImageEVA cat ./eva.dummy.squashfs >> $(KDIR)/$(1).eva endef +define CompressGzip + gzip -c $(1) > $(2) +endef + +define PatchKernelGzip + cp $(KDIR)/vmlinux $(KDIR)/vmlinux-$(1) + $(STAGING_DIR_HOST)/bin/patch-cmdline $(KDIR)/vmlinux-$(1) '$(strip $(2))' + $(call CompressGzip,$(KDIR)/vmlinux-$(1),$(KDIR)/vmlinux-$(1).gzip) +endef + +define MkImageGzip + mkimage -A mips -O linux -T kernel -a 0x80002000 -C gzip \ + -e 0x80002000 -n 'MIPS OpenWrt Linux-$(LINUX_VERSION)' \ + -d $(KDIR)/vmlinux-$(1).gzip $(KDIR)/uImage-$(1) +endef + define Image/Build/squashfs cat $(KDIR)/uImage-$(2) $(KDIR)/root.$(1) > $(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image $(call prepare_generic_squashfs,$(BIN_DIR)/$(IMG_PREFIX)-$(2)-$(1).image) @@ -80,6 +97,12 @@ define Image/BuildKernelEVA/Template $(CP) $(KDIR)/$(1).eva $(BIN_DIR)/$(IMG_PREFIX)-$(1).eva endef +define Image/BuildKernelGzip/Template + $(call PatchKernelGzip,$(1),$(if $(2),$(2) machtype=$(1),)) + $(call MkImageGzip,$(1)) + $(CP) $(KDIR)/uImage-$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1)-uImage +endef + ifeq ($(CONFIG_TARGET_lantiq_danube),y) Image/BuildKernel/Profile/EASY50712=$(call Image/BuildKernel/Template,EASY50712,$(xway_cmdline)) @@ -198,6 +221,58 @@ define Image/Build/Profile/Generic endef endif +ifeq ($(CONFIG_TARGET_lantiq_svip_be),y) +define Image/BuildKernel/Profile/EASY33016 + $(call Image/BuildKernelGzip/Template,EASY33016,$(svip_cmdline)) +endef + +define Image/Build/Profile/EASY33016 + $(call Image/Build/$(1),$(1),EASY33016) +endef + +define Image/BuildKernel/Profile/EASY336 + $(call Image/BuildKernelGzip/Template,EASY33016,$(svip_cmdline)) +endef + +define Image/Build/Profile/EASY336 + $(call Image/Build/$(1),$(1),EASY33016) +endef + +define Image/BuildKernel/Profile/Generic + $(call Image/BuildKernelGzip/Template,EASY33016,$(svip_cmdline)) + $(call Image/BuildKernelGzip/Template,EASY336,$(svip_cmdline)) + $(call Image/BuildKernelGzip/Template,NONE) +endef + +define Image/Build/Profile/Generic + $(call Image/Build/$(1),$(1),EASY33016) + $(call Image/Build/$(1),$(1),EASY336) + $(call Image/Build/$(1),$(1),NONE) + $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs +endef +endif + +ifeq ($(CONFIG_TARGET_lantiq_svip_le),y) +define Image/BuildKernel/Profile/EASY336 + $(call Image/BuildKernelGzip/Template,EASY33016,$(svip_cmdline)) +endef + +define Image/Build/Profile/EASY336 + $(call Image/Build/$(1),$(1),EASY33016) +endef + +define Image/BuildKernel/Profile/Generic + $(call Image/BuildKernelGzip/Template,EASY336,$(svip_cmdline)) + $(call Image/BuildKernelGzip/Template,NONE) +endef + +define Image/Build/Profile/Generic + $(call Image/Build/$(1),$(1),EASY336) + $(call Image/Build/$(1),$(1),NONE) + $(CP) $(KDIR)/root.$(1) $(BIN_DIR)/$(IMG_PREFIX)-$(1).rootfs +endef +endif + define Image/BuildKernel $(call Image/BuildKernel/Profile/$(PROFILE)) endef diff --git a/target/linux/lantiq/patches-3.3/0031-MIPS-lantiq-unify-xway-prom-code.patch b/target/linux/lantiq/patches-3.3/0031-MIPS-lantiq-unify-xway-prom-code.patch index 605063fc23..130c69474e 100644 --- a/target/linux/lantiq/patches-3.3/0031-MIPS-lantiq-unify-xway-prom-code.patch +++ b/target/linux/lantiq/patches-3.3/0031-MIPS-lantiq-unify-xway-prom-code.patch @@ -18,8 +18,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org> delete mode 100644 arch/mips/lantiq/xway/prom-xway.c create mode 100644 arch/mips/lantiq/xway/prom.c ---- a/arch/mips/lantiq/xway/Makefile -+++ b/arch/mips/lantiq/xway/Makefile +Index: linux-3.3.8/arch/mips/lantiq/xway/Makefile +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/xway/Makefile 2012-07-31 08:34:35.000000000 +0200 ++++ linux-3.3.8/arch/mips/lantiq/xway/Makefile 2012-07-31 08:52:14.155414782 +0200 @@ -1,7 +1,4 @@ -obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o - @@ -29,22 +31,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org> obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ---- a/arch/mips/lantiq/xway/Makefile.rej -+++ /dev/null -@@ -1,11 +0,0 @@ ----- arch/mips/lantiq/xway/Makefile --+++ arch/mips/lantiq/xway/Makefile --@@ -1,7 +1,4 @@ ---obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o --- ---obj-$(CONFIG_SOC_XWAY) += prom-xway.o ---obj-$(CONFIG_SOC_AMAZON_SE) += prom-ase.o --+obj-y := prom.o sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o clk.o -- -- obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o -- obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ---- a/arch/mips/lantiq/xway/prom-ase.c -+++ /dev/null +Index: linux-3.3.8/arch/mips/lantiq/xway/prom-ase.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/xway/prom-ase.c 2012-07-31 08:34:34.000000000 +0200 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,48 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it @@ -94,8 +84,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org> - ltq_register_gpio(); - ltq_register_wdt(); -} ---- a/arch/mips/lantiq/xway/prom-xway.c -+++ /dev/null +Index: linux-3.3.8/arch/mips/lantiq/xway/prom-xway.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/xway/prom-xway.c 2012-07-31 08:34:34.000000000 +0200 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,64 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it @@ -161,8 +153,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org> - ltq_register_gpio(); - ltq_register_wdt(); -} ---- /dev/null -+++ b/arch/mips/lantiq/xway/prom.c +Index: linux-3.3.8/arch/mips/lantiq/xway/prom.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/xway/prom.c 2012-07-31 08:52:14.155414782 +0200 @@ -0,0 +1,79 @@ +/* + * This program is free software; you can redistribute it and/or modify it diff --git a/target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch b/target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch deleted file mode 100644 index bcdae2174e..0000000000 --- a/target/linux/lantiq/patches-3.3/0063-MIPS-lantiq-irqs-were-not-cleared-properly-on-boot.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 875a7139535da541aa2e9de308b3f6f791a131d0 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Tue, 20 Mar 2012 09:44:27 +0100 -Subject: [PATCH 63/70] MIPS: lantiq: irqs were not cleared properly on boot - ---- - arch/mips/lantiq/irq.c | 10 +++++----- - 1 files changed, 5 insertions(+), 5 deletions(-) - ---- a/arch/mips/lantiq/irq.c -+++ b/arch/mips/lantiq/irq.c -@@ -326,12 +326,12 @@ void __init arch_init_irq(void) - panic("Failed to remap eiu memory\n"); - } - -- /* make sure all irqs are turned off by default */ -- for (i = 0; i < 5; i++) -+ for (i = 0; i < 5; i++) { -+ /* make sure all irqs are turned off by default */ - ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); -- -- /* clear all possibly pending interrupts */ -- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); -+ /* clear all possibly pending interrupts */ -+ ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); -+ } - - mips_cpu_irq_init(); - diff --git a/target/linux/lantiq/patches-3.3/0070-icu-multi-base.patch b/target/linux/lantiq/patches-3.3/0070-icu-multi-base.patch new file mode 100644 index 0000000000..d7e098f909 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/0070-icu-multi-base.patch @@ -0,0 +1,233 @@ +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +=================================================================== +--- linux-3.3.8.orig/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h 2012-07-31 08:34:35.000000000 +0200 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h 2012-07-31 08:34:46.063369976 +0200 +@@ -9,6 +9,8 @@ + #ifndef _LANTIQ_XWAY_IRQ_H__ + #define _LANTIQ_XWAY_IRQ_H__ + ++#define IM_NUM 5 ++ + #define INT_NUM_IRQ0 8 + #define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) + #define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) +Index: linux-3.3.8/arch/mips/lantiq/irq.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/irq.c 2012-07-31 08:34:35.000000000 +0200 ++++ linux-3.3.8/arch/mips/lantiq/irq.c 2012-07-31 08:51:40.203413329 +0200 +@@ -48,8 +48,8 @@ + */ + #define LTQ_ICU_EBU_IRQ 22 + +-#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y)) +-#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x)) ++#define ltq_icu_w32(x, y, m) ltq_w32((x), ltq_icu_membase[m] + (y)) ++#define ltq_icu_r32(x, m) ltq_r32(ltq_icu_membase[m] + (x)) + + #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y)) + #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x)) +@@ -63,11 +63,78 @@ + LTQ_EIU_IR5, + }; + +-static struct resource ltq_icu_resource = { +- .name = "icu", +- .start = LTQ_ICU_BASE_ADDR, +- .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_SIZE - 1, +- .flags = IORESOURCE_MEM, ++static struct resource ltq_icu_resource[IM_NUM] = { ++{ ++ .name = "icu_im0", ++ .start = LTQ_ICU_BASE_ADDR, ++ .end = LTQ_ICU_BASE_ADDR + LTQ_ICU_OFFSET - 1, ++ .flags = IORESOURCE_MEM, ++}, ++#if IM_NUM >= 2 ++{ ++ .name = "icu_im1", ++#ifdef LTQ_ICU_BASE_ADDR1 ++ .start = LTQ_ICU_BASE_ADDR1, ++ .end = LTQ_ICU_BASE_ADDR1 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 1), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 2) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif ++#if IM_NUM >= 3 ++{ ++ .name = "icu_im2", ++#ifdef LTQ_ICU_BASE_ADDR2 ++ .start = LTQ_ICU_BASE_ADDR2, ++ .end = LTQ_ICU_BASE_ADDR2 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 2), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 3) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif ++#if IM_NUM >= 4 ++{ ++ .name = "icu_im3", ++#ifdef LTQ_ICU_BASE_ADDR3 ++ .start = LTQ_ICU_BASE_ADDR3, ++ .end = LTQ_ICU_BASE_ADDR3 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 3), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 4) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif ++#if IM_NUM >= 5 ++{ ++ .name = "icu_im4", ++#ifdef LTQ_ICU_BASE_ADDR4 ++ .start = LTQ_ICU_BASE_ADDR4, ++ .end = LTQ_ICU_BASE_ADDR4 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 4), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 5) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif ++#if IM_NUM >= 6 ++{ ++ .name = "icu_im5", ++#ifdef LTQ_ICU_BASE_ADDR5 ++ .start = LTQ_ICU_BASE_ADDR5, ++ .end = LTQ_ICU_BASE_ADDR5 + LTQ_ICU_OFFSET - 1, ++#else ++ .start = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 5), ++ .end = LTQ_ICU_BASE_ADDR + (LTQ_ICU_OFFSET * 6) - 1, ++#endif ++ .flags = IORESOURCE_MEM, ++}, ++#endif + }; + + static struct resource ltq_eiu_resource = { +@@ -77,50 +144,56 @@ + .flags = IORESOURCE_MEM, + }; + +-static void __iomem *ltq_icu_membase; ++static void __iomem *ltq_icu_membase[IM_NUM]; + static void __iomem *ltq_eiu_membase; + + void ltq_disable_irq(struct irq_data *d) + { +- u32 ier = LTQ_ICU_IM0_IER; + int irq_nr = d->irq - INT_NUM_IRQ0; ++ unsigned int im_nr; + +- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); ++ im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; +- ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); ++ ++ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) & ~(1 << irq_nr), ++ LTQ_ICU_IM0_IER, im_nr); + } + + void ltq_mask_and_ack_irq(struct irq_data *d) + { +- u32 ier = LTQ_ICU_IM0_IER; +- u32 isr = LTQ_ICU_IM0_ISR; + int irq_nr = d->irq - INT_NUM_IRQ0; ++ unsigned int im_nr; + +- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); +- isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); ++ irq_nr -= INT_NUM_IRQ0; ++ im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; +- ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); +- ltq_icu_w32((1 << irq_nr), isr); ++ ++ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) & ~(1 << irq_nr), LTQ_ICU_IM0_IER, im_nr); ++ ltq_icu_w32((1 << irq_nr), LTQ_ICU_IM0_ISR, im_nr); + } + + static void ltq_ack_irq(struct irq_data *d) + { +- u32 isr = LTQ_ICU_IM0_ISR; + int irq_nr = d->irq - INT_NUM_IRQ0; ++ unsigned int im_nr; + +- isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); ++ irq_nr -= INT_NUM_IRQ0; ++ im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; +- ltq_icu_w32((1 << irq_nr), isr); ++ ++ ltq_icu_w32((1 << irq_nr), LTQ_ICU_IM0_ISR, im_nr); + } + + void ltq_enable_irq(struct irq_data *d) + { +- u32 ier = LTQ_ICU_IM0_IER; + int irq_nr = d->irq - INT_NUM_IRQ0; ++ unsigned int im_nr; + +- ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); ++ irq_nr -= INT_NUM_IRQ0; ++ im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; +- ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier); ++ ++ ltq_icu_w32(ltq_icu_r32(LTQ_ICU_IM0_IER, im_nr) | (1 << irq_nr), LTQ_ICU_IM0_IER, im_nr); + } + + static unsigned int ltq_startup_eiu_irq(struct irq_data *d) +@@ -187,7 +260,7 @@ + { + u32 irq; + +- irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); ++ irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR, module); + if (irq == 0) + return; + +@@ -250,8 +323,19 @@ + { + int i; + +- if (insert_resource(&iomem_resource, <q_icu_resource) < 0) +- panic("Failed to insert icu memory"); ++ for (i=0; i < IM_NUM; i++) { ++ if (insert_resource(&iomem_resource, <q_icu_resource[i]) < 0) ++ panic("Failed to insert icu memory\n"); ++ ++ if (request_mem_region(ltq_icu_resource[i].start, ++ resource_size(<q_icu_resource[i]), "icu") < 0) ++ panic("Failed to request icu memory\n"); ++ ++ ltq_icu_membase[i] = ioremap_nocache(ltq_icu_resource[i].start, ++ resource_size(<q_icu_resource[i])); ++ if (!ltq_icu_membase[i]) ++ panic("Failed to remap icu memory\n"); ++ } + + if (request_mem_region(ltq_icu_resource.start, + resource_size(<q_icu_resource), "icu") < 0) +@@ -277,11 +361,11 @@ + } + + /* make sure all irqs are turned off by default */ +- for (i = 0; i < 5; i++) +- ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET)); +- +- /* clear all possibly pending interrupts */ +- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET)); ++ for (i = 0; i < IM_NUM; i++) ++ ltq_icu_w32(0, LTQ_ICU_IM0_IER, i); ++ /* clear all possibly pending interrupts */ ++ ltq_icu_w32(~0, LTQ_ICU_IM0_ISR, i); ++ } + + mips_cpu_irq_init(); + diff --git a/target/linux/lantiq/patches-3.3/105-falcon_header_update.patch b/target/linux/lantiq/patches-3.3/105-falcon_header_update.patch new file mode 100644 index 0000000000..d428de860c --- /dev/null +++ b/target/linux/lantiq/patches-3.3/105-falcon_header_update.patch @@ -0,0 +1,11 @@ +--- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h ++++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +@@ -18,6 +18,8 @@ + #ifndef _FALCON_IRQ__ + #define _FALCON_IRQ__ + ++#define IM_NUM 5 ++ + #define INT_NUM_IRQ0 8 + #define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) + #define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32)diff --git a/target/linux/lantiq/patches-2.6.32/300-svip_header.patch b/target/linux/lantiq/patches-2.6.32/300-svip_header.patch diff --git a/target/linux/lantiq/patches-3.3/300-svip_header.patch b/target/linux/lantiq/patches-3.3/300-svip_header.patch new file mode 100644 index 0000000000..6c936134c0 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/300-svip_header.patch @@ -0,0 +1,9518 @@ +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/irq.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/irq.h 2012-07-31 15:46:02.464476159 +0200 +@@ -0,0 +1,36 @@ ++/* ++ * arch/mips/include/asm/mach-lantiq/svip/irq.h ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq ++ * ++ */ ++ ++#ifndef __IRQ_H ++#define __IRQ_H ++ ++#include <svip_irq.h> ++ ++#define NR_IRQS 264 ++ ++#include_next <irq.h> ++ ++/* Functions for EXINT handling */ ++extern int ifx_enable_external_int(u32 exint, u32 mode); ++extern int ifx_disable_external_int(u32 exint); ++extern int ifx_external_int_level(u32 exint); ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h 2012-07-31 15:58:41.312508597 +0200 +@@ -0,0 +1,71 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#ifndef _LTQ_SVIP_H__ ++#define _LTQ_SVIP_H__ ++ ++#ifdef CONFIG_SOC_SVIP ++ ++#include <lantiq.h> ++ ++/* Chip IDs */ ++#define SOC_ID_SVIP 0x169 ++ ++/* SoC Types */ ++#define SOC_TYPE_SVIP 0x01 ++ ++/* ASC0/1 - serial port */ ++#define LTQ_ASC0_BASE_ADDR 0x14100100 ++#define LTQ_ASC1_BASE_ADDR 0x14100200 ++#define LTQ_ASC_SIZE 0x100 ++#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) ++ ++#define LTQ_ASC_TIR(x) (INT_NUM_IM0_IRL0 + (x * 8)) ++#define LTQ_ASC_RIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 2) ++#define LTQ_ASC_EIR(x) (INT_NUM_IM0_IRL0 + (x * 8) + 3) ++ ++/* ICU - interrupt control unit */ ++#define LTQ_ICU_BASE_ADDR 0x14106000 ++#define LTQ_ICU_BASE_ADDR1 0x14106028 ++#define LTQ_ICU_BASE_ADDR2 0x1E016000 ++#define LTQ_ICU_BASE_ADDR3 0x1E016028 ++#define LTQ_ICU_BASE_ADDR4 0x14106050 ++#define LTQ_ICU_BASE_ADDR5 0x14106078 ++#define LTQ_ICU_SIZE 0x100 ++ ++/* WDT */ ++#define LTQ_WDT_BASE_ADDR 0x1F8803F0 ++#define LTQ_WDT_SIZE 0x10 ++ ++/* Status */ ++#define LTQ_STATUS_BASE_ADDR (KSEG1 + 0x1E000500) ++#define LTQ_STATUS_CHIPID ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C)) ++ ++#define LTQ_EIU_BASE_ADDR 0 ++ ++#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) ++#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) ++ ++extern __iomem void *ltq_ebu_membase; ++ ++extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, ++ bool altsel0, bool altsel1); ++extern int ltq_port_get_dir(unsigned int port, unsigned int pin); ++extern int ltq_port_get_puden(unsigned int port, unsigned int pin); ++extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin); ++extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin); ++ ++#define ltq_is_ar9() 0 ++#define ltq_is_vr9() 0 ++#define ltq_is_falcon() 0 ++ ++#define BS_FLASH 0 ++#define LTQ_RST_CAUSE_WDTRST 0x2 ++ ++#endif /* CONFIG_SOC_SVIP */ ++#endif /* _LTQ_SVIP_H__ */ +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_irq.h 2012-07-31 15:46:02.468476160 +0200 +@@ -0,0 +1,35 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2010 Lantiq ++ */ ++#ifndef __SVIP_IRQ_H ++#define __SVIP_IRQ_H ++ ++#define IM_NUM 6 ++ ++#define INT_NUM_IRQ0 8 ++#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) ++#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) ++#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) ++#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) ++#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) ++#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) ++#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) ++ ++#define INT_NUM_IM5_IRL0 (INT_NUM_IRQ0 + 160) ++#define MIPS_CPU_TIMER_IRQ (INT_NUM_IM5_IRL0 + 2) ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/base_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/base_reg.h 2012-07-31 15:46:02.468476160 +0200 +@@ -0,0 +1,56 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __BASE_REG_H ++#define __BASE_REG_H ++ ++#ifndef KSEG1 ++#define KSEG1 0xA0000000 ++#endif ++ ++#define LTQ_EBU_SEG1_BASE (KSEG1 + 0x10000000) ++#define LTQ_EBU_SEG2_BASE (KSEG1 + 0x11000000) ++#define LTQ_EBU_SEG3_BASE (KSEG1 + 0x12000000) ++#define LTQ_EBU_SEG4_BASE (KSEG1 + 0x13000000) ++ ++#define LTQ_ASC0_BASE (KSEG1 + 0x14100100) ++#define LTQ_ASC1_BASE (KSEG1 + 0x14100200) ++ ++#define LTQ_SSC0_BASE (0x14100300) ++#define LTQ_SSC1_BASE (0x14100400) ++ ++#define LTQ_PORT_P0_BASE (KSEG1 + 0x14100600) ++#define LTQ_PORT_P1_BASE (KSEG1 + 0x14108100) ++#define LTQ_PORT_P2_BASE (KSEG1 + 0x14100800) ++#define LTQ_PORT_P3_BASE (KSEG1 + 0x14100900) ++#define LTQ_PORT_P4_BASE (KSEG1 + 0x1E000400) ++ ++#define LTQ_EBU_BASE (KSEG1 + 0x14102000) ++#define LTQ_DMA_BASE (KSEG1 + 0x14104000) ++ ++#define LTQ_ICU0_IM3_IM2_BASE (KSEG1 + 0x1E016000) ++#define LTQ_ICU0_IM5_IM4_IM1_IM0_BASE (KSEG1 + 0x14106000) ++ ++#define LTQ_ES_BASE (KSEG1 + 0x18000000) ++ ++#define LTQ_SYS0_BASE (KSEG1 + 0x1C000000) ++#define LTQ_SYS1_BASE (KSEG1 + 0x1C000800) ++#define LTQ_SYS2_BASE (KSEG1 + 0x1E400000) ++ ++#define LTQ_L2_SPRAM_BASE (KSEG1 + 0x1F1E8000) ++ ++#define LTQ_SWINT_BASE (KSEG1 + 0x1E000100) ++#define LTQ_MBS_BASE (KSEG1 + 0x1E000200) ++ ++#define LTQ_STATUS_BASE (KSEG1 + 0x1E000500) ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys1_reg.h 2012-07-31 15:46:02.468476160 +0200 +@@ -0,0 +1,370 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __SYS1_REG_H ++#define __SYS1_REG_H ++ ++#define sys1_r32(reg) ltq_r32(&sys1->reg) ++#define sys1_w32(val, reg) ltq_w32(val, &sys1->reg) ++#define sys1_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys1->reg) ++ ++/** SYS1 register structure */ ++struct svip_reg_sys1 { ++ unsigned long clksr; /* 0x0000 */ ++ unsigned long clkenr; /* 0x0004 */ ++ unsigned long clkclr; /* 0x0008 */ ++ unsigned long reserved0[1]; ++ unsigned long l2ccr; /* 0x0010 */ ++ unsigned long fpicr; /* 0x0014 */ ++ unsigned long wdtcr; /* 0x0018 */ ++ unsigned long reserved1[1]; ++ unsigned long cpucr[6]; /* 0x0020 */ ++ unsigned long reserved2[2]; ++ unsigned long rsr; /* 0x0040 */ ++ unsigned long rreqr; /* 0x0044 */ ++ unsigned long rrlsr; /* 0x0048 */ ++ unsigned long rbtr; /* 0x004c */ ++ unsigned long irncr; /* 0x0050 */ ++ unsigned long irnicr; /* 0x0054 */ ++ unsigned long irnen; /* 0x0058 */ ++ unsigned long reserved3[1]; ++ unsigned long cpursr[6]; /* 0x0060 */ ++ unsigned long reserved4[2]; ++ unsigned long cpusrssr[6]; /* 0x0080 */ ++ unsigned long reserved5[2]; ++ unsigned long cpuwrssr[6]; /* 0x00a0 */ ++}; ++ ++/******************************************************************************* ++ * SYS1 Clock Status Register ++ ******************************************************************************/ ++/* (r) Clock Enable for L2C */ ++#define SYS1_CLKSR_L2C (0x1 << 31) ++/* (r) Clock Enable for DDR2 */ ++#define SYS1_CLKSR_DDR2 (0x1 << 30) ++/* (r) Clock Enable for SMI2 */ ++#define SYS1_CLKSR_SMI2 (0x1 << 29) ++/* (r) Clock Enable for SMI1 */ ++#define SYS1_CLKSR_SMI1 (0x1 << 28) ++/* (r) Clock Enable for SMI0 */ ++#define SYS1_CLKSR_SMI0 (0x1 << 27) ++/* (r) Clock Enable for FMI0 */ ++#define SYS1_CLKSR_FMI0 (0x1 << 26) ++/* (r) Clock Enable for PORT0 */ ++#define SYS1_CLKSR_PORT0 (0x1 << 0) ++/* (r) Clock Enable for PCM3 */ ++#define SYS1_CLKSR_PCM3 (0x1 << 19) ++/* (r) Clock Enable for PCM2 */ ++#define SYS1_CLKSR_PCM2 (0x1 << 18) ++/* (r) Clock Enable for PCM1 */ ++#define SYS1_CLKSR_PCM1 (0x1 << 17) ++/* (r) Clock Enable for PCM0 */ ++#define SYS1_CLKSR_PCM0 (0x1 << 16) ++/* (r) Clock Enable for ASC1 */ ++#define SYS1_CLKSR_ASC1 (0x1 << 15) ++/* (r) Clock Enable for ASC0 */ ++#define SYS1_CLKSR_ASC0 (0x1 << 14) ++/* (r) Clock Enable for SSC2 */ ++#define SYS1_CLKSR_SSC2 (0x1 << 13) ++/* (r) Clock Enable for SSC1 */ ++#define SYS1_CLKSR_SSC1 (0x1 << 12) ++/* (r) Clock Enable for SSC0 */ ++#define SYS1_CLKSR_SSC0 (0x1 << 11) ++/* (r) Clock Enable for GPTC */ ++#define SYS1_CLKSR_GPTC (0x1 << 10) ++/* (r) Clock Enable for DMA */ ++#define SYS1_CLKSR_DMA (0x1 << 9) ++/* (r) Clock Enable for FSCT */ ++#define SYS1_CLKSR_FSCT (0x1 << 8) ++/* (r) Clock Enable for ETHSW */ ++#define SYS1_CLKSR_ETHSW (0x1 << 7) ++/* (r) Clock Enable for EBU */ ++#define SYS1_CLKSR_EBU (0x1 << 6) ++/* (r) Clock Enable for TRNG */ ++#define SYS1_CLKSR_TRNG (0x1 << 5) ++/* (r) Clock Enable for DEU */ ++#define SYS1_CLKSR_DEU (0x1 << 4) ++/* (r) Clock Enable for PORT3 */ ++#define SYS1_CLKSR_PORT3 (0x1 << 3) ++/* (r) Clock Enable for PORT2 */ ++#define SYS1_CLKSR_PORT2 (0x1 << 2) ++/* (r) Clock Enable for PORT1 */ ++#define SYS1_CLKSR_PORT1 (0x1 << 1) ++ ++/******************************************************************************* ++ * SYS1 Clock Enable Register ++ ******************************************************************************/ ++/* (w) Clock Enable Request for L2C */ ++#define SYS1_CLKENR_L2C (0x1 << 31) ++/* (w) Clock Enable Request for DDR2 */ ++#define SYS1_CLKENR_DDR2 (0x1 << 30) ++/* (w) Clock Enable Request for SMI2 */ ++#define SYS1_CLKENR_SMI2 (0x1 << 29) ++/* (w) Clock Enable Request for SMI1 */ ++#define SYS1_CLKENR_SMI1 (0x1 << 28) ++/* (w) Clock Enable Request for SMI0 */ ++#define SYS1_CLKENR_SMI0 (0x1 << 27) ++/* (w) Clock Enable Request for FMI0 */ ++#define SYS1_CLKENR_FMI0 (0x1 << 26) ++/* (w) Clock Enable Request for PORT0 */ ++#define SYS1_CLKENR_PORT0 (0x1 << 0) ++/* (w) Clock Enable Request for PCM3 */ ++#define SYS1_CLKENR_PCM3 (0x1 << 19) ++/* (w) Clock Enable Request for PCM2 */ ++#define SYS1_CLKENR_PCM2 (0x1 << 18) ++/* (w) Clock Enable Request for PCM1 */ ++#define SYS1_CLKENR_PCM1 (0x1 << 17) ++/* (w) Clock Enable Request for PCM0 */ ++#define SYS1_CLKENR_PCM0 (0x1 << 16) ++/* (w) Clock Enable Request for ASC1 */ ++#define SYS1_CLKENR_ASC1 (0x1 << 15) ++/* (w) Clock Enable Request for ASC0 */ ++#define SYS1_CLKENR_ASC0 (0x1 << 14) ++/* (w) Clock Enable Request for SSC2 */ ++#define SYS1_CLKENR_SSC2 (0x1 << 13) ++/* (w) Clock Enable Request for SSC1 */ ++#define SYS1_CLKENR_SSC1 (0x1 << 12) ++/* (w) Clock Enable Request for SSC0 */ ++#define SYS1_CLKENR_SSC0 (0x1 << 11) ++/* (w) Clock Enable Request for GPTC */ ++#define SYS1_CLKENR_GPTC (0x1 << 10) ++/* (w) Clock Enable Request for DMA */ ++#define SYS1_CLKENR_DMA (0x1 << 9) ++/* (w) Clock Enable Request for FSCT */ ++#define SYS1_CLKENR_FSCT (0x1 << 8) ++/* (w) Clock Enable Request for ETHSW */ ++#define SYS1_CLKENR_ETHSW (0x1 << 7) ++/* (w) Clock Enable Request for EBU */ ++#define SYS1_CLKENR_EBU (0x1 << 6) ++/* (w) Clock Enable Request for TRNG */ ++#define SYS1_CLKENR_TRNG (0x1 << 5) ++/* (w) Clock Enable Request for DEU */ ++#define SYS1_CLKENR_DEU (0x1 << 4) ++/* (w) Clock Enable Request for PORT3 */ ++#define SYS1_CLKENR_PORT3 (0x1 << 3) ++/* (w) Clock Enable Request for PORT2 */ ++#define SYS1_CLKENR_PORT2 (0x1 << 2) ++/* (w) Clock Enable Request for PORT1 */ ++#define SYS1_CLKENR_PORT1 (0x1 << 1) ++ ++/******************************************************************************* ++ * SYS1 Clock Clear Register ++ ******************************************************************************/ ++/* (w) Clock Disable Request for L2C */ ++#define SYS1_CLKCLR_L2C (0x1 << 31) ++/* (w) Clock Disable Request for DDR2 */ ++#define SYS1_CLKCLR_DDR2 (0x1 << 30) ++/* (w) Clock Disable Request for SMI2 */ ++#define SYS1_CLKCLR_SMI2 (0x1 << 29) ++/* (w) Clock Disable Request for SMI1 */ ++#define SYS1_CLKCLR_SMI1 (0x1 << 28) ++/* (w) Clock Disable Request for SMI0 */ ++#define SYS1_CLKCLR_SMI0 (0x1 << 27) ++/* (w) Clock Disable Request for FMI0 */ ++#define SYS1_CLKCLR_FMI0 (0x1 << 26) ++/* (w) Clock Disable Request for PORT0 */ ++#define SYS1_CLKCLR_PORT0 (0x1 << 0) ++/* (w) Clock Disable Request for PCM3 */ ++#define SYS1_CLKCLR_PCM3 (0x1 << 19) ++/* (w) Clock Disable Request for PCM2 */ ++#define SYS1_CLKCLR_PCM2 (0x1 << 18) ++/* (w) Clock Disable Request for PCM1 */ ++#define SYS1_CLKCLR_PCM1 (0x1 << 17) ++/* (w) Clock Disable Request for PCM0 */ ++#define SYS1_CLKCLR_PCM0 (0x1 << 16) ++/* (w) Clock Disable Request for ASC1 */ ++#define SYS1_CLKCLR_ASC1 (0x1 << 15) ++/* (w) Clock Disable Request for ASC0 */ ++#define SYS1_CLKCLR_ASC0 (0x1 << 14) ++/* (w) Clock Disable Request for SSC2 */ ++#define SYS1_CLKCLR_SSC2 (0x1 << 13) ++/* (w) Clock Disable Request for SSC1 */ ++#define SYS1_CLKCLR_SSC1 (0x1 << 12) ++/* (w) Clock Disable Request for SSC0 */ ++#define SYS1_CLKCLR_SSC0 (0x1 << 11) ++/* (w) Clock Disable Request for GPTC */ ++#define SYS1_CLKCLR_GPTC (0x1 << 10) ++/* (w) Clock Disable Request for DMA */ ++#define SYS1_CLKCLR_DMA (0x1 << 9) ++/* (w) Clock Disable Request for FSCT */ ++#define SYS1_CLKCLR_FSCT (0x1 << 8) ++/* (w) Clock Disable Request for ETHSW */ ++#define SYS1_CLKCLR_ETHSW (0x1 << 7) ++/* (w) Clock Disable Request for EBU */ ++#define SYS1_CLKCLR_EBU (0x1 << 6) ++/* (w) Clock Disable Request for TRNG */ ++#define SYS1_CLKCLR_TRNG (0x1 << 5) ++/* (w) Clock Disable Request for DEU */ ++#define SYS1_CLKCLR_DEU (0x1 << 4) ++/* (w) Clock Disable Request for PORT3 */ ++#define SYS1_CLKCLR_PORT3 (0x1 << 3) ++/* (w) Clock Disable Request for PORT2 */ ++#define SYS1_CLKCLR_PORT2 (0x1 << 2) ++/* (w) Clock Disable Request for PORT1 */ ++#define SYS1_CLKCLR_PORT1 (0x1 << 1) ++ ++/******************************************************************************* ++ * SYS1 FPI Control Register ++ ******************************************************************************/ ++ ++/* FPI Bus Clock divider (0) */ ++#define SYS1_FPICR_FPIDIV (0x1) ++#define SYS1_FPICR_FPIDIV_VAL(val) (((val) & 0x1) << 0) ++#define SYS1_FPICR_FPIDIV_GET(val) ((((val) & SYS1_FPICR_FPIDIV) >> 0) & 0x1) ++#define SYS1_FPICR_FPIDIV_SET(reg,val) (reg) = ((reg & ~SYS1_FPICR_FPIDIV) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * SYS1 Clock Control Register for CPUn ++ ******************************************************************************/ ++ ++/* Enable bit for clock of CPUn (1) */ ++#define SYS1_CPUCR_CPUCLKEN (0x1 << 1) ++#define SYS1_CPUCR_CPUCLKEN_VAL(val) (((val) & 0x1) << 1) ++#define SYS1_CPUCR_CPUCLKEN_GET(val) ((((val) & SYS1_CPUCR_CPUCLKEN) >> 1) & 0x1) ++#define SYS1_CPUCR_CPUCLKEN_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUCLKEN) | (((val) & 0x1) << 1)) ++/* Divider factor for clock of CPUn (0) */ ++#define SYS1_CPUCR_CPUDIV (0x1) ++#define SYS1_CPUCR_CPUDIV_VAL(val) (((val) & 0x1) << 0) ++#define SYS1_CPUCR_CPUDIV_GET(val) ((((val) & SYS1_CPUCR_CPUDIV) >> 0) & 0x1) ++#define SYS1_CPUCR_CPUDIV_SET(reg,val) (reg) = ((reg & ~SYS1_CPUCR_CPUDIV) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * SYS1 Reset Request Register ++ ******************************************************************************/ ++ ++/* HRSTOUT Reset Request (18) */ ++#define SYS1_RREQ_HRSTOUT (0x1 << 18) ++#define SYS1_RREQ_HRSTOUT_VAL(val) (((val) & 0x1) << 18) ++#define SYS1_RREQ_HRSTOUT_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_HRSTOUT) | (((val) & 1) << 18)) ++ /* FBS0 Reset Request (17) */ ++#define SYS1_RREQ_FBS0 (0x1 << 17) ++#define SYS1_RREQ_FBS0_VAL(val) (((val) & 0x1) << 17) ++#define SYS1_RREQ_FBS0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_FBS0) | (((val) & 1) << 17)) ++ /* SUBSYS Reset Request (16) */ ++#define SYS1_RREQ_SUBSYS (0x1 << 16) ++#define SYS1_RREQ_SUBSYS_VAL(val) (((val) & 0x1) << 16) ++#define SYS1_RREQ_SUBSYS_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_SUBSYS) | (((val) & 1) << 16)) ++ /* Watchdog5 Reset Request (13) */ ++#define SYS1_RREQ_WDT5 (0x1 << 13) ++#define SYS1_RREQ_WDT5_VAL(val) (((val) & 0x1) << 13) ++#define SYS1_RREQ_WDT5_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT5) | (((val) & 1) << 13)) ++ /* Watchdog4 Reset Request (12) */ ++#define SYS1_RREQ_WDT4 (0x1 << 12) ++#define SYS1_RREQ_WDT4_VAL(val) (((val) & 0x1) << 12) ++#define SYS1_RREQ_WDT4_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT4) | (((val) & 1) << 12)) ++ /* Watchdog3 Reset Request (11) */ ++#define SYS1_RREQ_WDT3 (0x1 << 11) ++#define SYS1_RREQ_WDT3_VAL(val) (((val) & 0x1) << 11) ++#define SYS1_RREQ_WDT3_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT3) | (((val) & 1) << 11)) ++ /* Watchdog2 Reset Request (10) */ ++#define SYS1_RREQ_WDT2 (0x1 << 10) ++#define SYS1_RREQ_WDT2_VAL(val) (((val) & 0x1) << 10) ++#define SYS1_RREQ_WDT2_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT2) | (((val) & 1) << 10)) ++ /* Watchdog1 Reset Request (9) */ ++#define SYS1_RREQ_WDT1 (0x1 << 9) ++#define SYS1_RREQ_WDT1_VAL(val) (((val) & 0x1) << 9) ++#define SYS1_RREQ_WDT1_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT1) | (((val) & 1) << 9)) ++ /* Watchdog0 Reset Request (8) */ ++#define SYS1_RREQ_WDT0 (0x1 << 8) ++#define SYS1_RREQ_WDT0_VAL(val) (((val) & 0x1) << 8) ++#define SYS1_RREQ_WDT0_SET(reg,val) (reg) = (((reg & ~SYS1_RREQ_WDT0) | (((val) & 1) << 8)) ++ /* CPU5 Reset Request (5) */ ++#define SYS1_RREQ_CPU5 (0x1 << 5) ++#define SYS1_RREQ_CPU5_VAL(val) (((val) & 0x1) << 5) ++#define SYS1_RREQ_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU5) | (((val) & 1) << 5)) ++ /* CPU4 Reset Request (4) */ ++#define SYS1_RREQ_CPU4 (0x1 << 4) ++#define SYS1_RREQ_CPU4_VAL(val) (((val) & 0x1) << 4) ++#define SYS1_RREQ_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU4) | (((val) & 1) << 4)) ++ /* CPU3 Reset Request (3) */ ++#define SYS1_RREQ_CPU3 (0x1 << 3) ++#define SYS1_RREQ_CPU3_VAL(val) (((val) & 0x1) << 3) ++#define SYS1_RREQ_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU3) | (((val) & 1) << 3)) ++ /* CPU2 Reset Request (2) */ ++#define SYS1_RREQ_CPU2 (0x1 << 2) ++#define SYS1_RREQ_CPU2_VAL(val) (((val) & 0x1) << 2) ++#define SYS1_RREQ_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU2) | (((val) & 1) << 2)) ++ /* CPU1 Reset Request (1) */ ++#define SYS1_RREQ_CPU1 (0x1 << 1) ++#define SYS1_RREQ_CPU1_VAL(val) (((val) & 0x1) << 1) ++#define SYS1_RREQ_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU1) | (((val) & 1) << 1)) ++/* CPU0 Reset Request (0) */ ++#define SYS1_RREQ_CPU0 (0x1) ++#define SYS1_RREQ_CPU0_VAL(val) (((val) & 0x1) << 0) ++#define SYS1_RREQ_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RREQ_CPU0) | (((val) & 1) << 0)) ++ ++/******************************************************************************* ++ * SYS1 Reset Release Register ++ ******************************************************************************/ ++ ++/* HRSTOUT Reset Release (18) */ ++#define SYS1_RRLSR_HRSTOUT (0x1 << 18) ++#define SYS1_RRLSR_HRSTOUT_VAL(val) (((val) & 0x1) << 18) ++#define SYS1_RRLSR_HRSTOUT_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_HRSTOUT) | (((val) & 1) << 18)) ++/* FBS0 Reset Release (17) */ ++#define SYS1_RRLSR_FBS0 (0x1 << 17) ++#define SYS1_RRLSR_FBS0_VAL(val) (((val) & 0x1) << 17) ++#define SYS1_RRLSR_FBS0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_FBS0) | (((val) & 1) << 17)) ++/* SUBSYS Reset Release (16) */ ++#define SYS1_RRLSR_SUBSYS (0x1 << 16) ++#define SYS1_RRLSR_SUBSYS_VAL(val) (((val) & 0x1) << 16) ++#define SYS1_RRLSR_SUBSYS_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_SUBSYS) | (((val) & 1) << 16)) ++/* Watchdog5 Reset Release (13) */ ++#define SYS1_RRLSR_WDT5 (0x1 << 13) ++#define SYS1_RRLSR_WDT5_VAL(val) (((val) & 0x1) << 13) ++#define SYS1_RRLSR_WDT5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT5) | (((val) & 1) << 13)) ++/* Watchdog4 Reset Release (12) */ ++#define SYS1_RRLSR_WDT4 (0x1 << 12) ++#define SYS1_RRLSR_WDT4_VAL(val) (((val) & 0x1) << 12) ++#define SYS1_RRLSR_WDT4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT4) | (((val) & 1) << 12)) ++/* Watchdog3 Reset Release (11) */ ++#define SYS1_RRLSR_WDT3 (0x1 << 11) ++#define SYS1_RRLSR_WDT3_VAL(val) (((val) & 0x1) << 11) ++#define SYS1_RRLSR_WDT3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT3) | (((val) & 1) << 11)) ++/* Watchdog2 Reset Release (10) */ ++#define SYS1_RRLSR_WDT2 (0x1 << 10) ++#define SYS1_RRLSR_WDT2_VAL(val) (((val) & 0x1) << 10) ++#define SYS1_RRLSR_WDT2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT2) | (((val) & 1) << 10)) ++/* Watchdog1 Reset Release (9) */ ++#define SYS1_RRLSR_WDT1 (0x1 << 9) ++#define SYS1_RRLSR_WDT1_VAL(val) (((val) & 0x1) << 9) ++#define SYS1_RRLSR_WDT1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT1) | (((val) & 1) << 9)) ++/* Watchdog0 Reset Release (8) */ ++#define SYS1_RRLSR_WDT0 (0x1 << 8) ++#define SYS1_RRLSR_WDT0_VAL(val) (((val) & 0x1) << 8) ++#define SYS1_RRLSR_WDT0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_WDT0) | (((val) & 1) << 8)) ++/* CPU5 Reset Release (5) */ ++#define SYS1_RRLSR_CPU5 (0x1 << 5) ++#define SYS1_RRLSR_CPU5_VAL(val) (((val) & 0x1) << 5) ++#define SYS1_RRLSR_CPU5_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU5) | (((val) & 1) << 5)) ++/* CPU4 Reset Release (4) */ ++#define SYS1_RRLSR_CPU4 (0x1 << 4) ++#define SYS1_RRLSR_CPU4_VAL(val) (((val) & 0x1) << 4) ++#define SYS1_RRLSR_CPU4_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU4) | (((val) & 1) << 4)) ++/* CPU3 Reset Release (3) */ ++#define SYS1_RRLSR_CPU3 (0x1 << 3) ++#define SYS1_RRLSR_CPU3_VAL(val) (((val) & 0x1) << 3) ++#define SYS1_RRLSR_CPU3_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU3) | (((val) & 1) << 3)) ++/* CPU2 Reset Release (2) */ ++#define SYS1_RRLSR_CPU2 (0x1 << 2) ++#define SYS1_RRLSR_CPU2_VAL(val) (((val) & 0x1) << 2) ++#define SYS1_RRLSR_CPU2_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU2) | (((val) & 1) << 2)) ++/* CPU1 Reset Release (1) */ ++#define SYS1_RRLSR_CPU1 (0x1 << 1) ++#define SYS1_RRLSR_CPU1_VAL(val) (((val) & 0x1) << 1) ++#define SYS1_RRLSR_CPU1_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU1) | (((val) & 1) << 1)) ++/* CPU0 Reset Release (0) */ ++#define SYS1_RRLSR_CPU0 (0x1) ++#define SYS1_RRLSR_CPU0_VAL(val) (((val) & 0x1) << 0) ++#define SYS1_RRLSR_CPU0_SET(reg,val) (reg) = ((reg & ~SYS1_RRLSR_CPU0) | (((val) & 1) << 0)) ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/es_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/es_reg.h 2012-07-31 15:46:02.476476158 +0200 +@@ -0,0 +1,2098 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __ES_REG_H ++#define __ES_REG_H ++ ++#define es_r32(reg) ltq_r32(&es->reg) ++#define es_w32(val, reg) ltq_w32(val, &es->reg) ++#define es_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &es->reg) ++ ++/** ES register structure */ ++struct svip_reg_es { ++ volatile unsigned long ps; /* 0x0000 */ ++ volatile unsigned long p0_ctl; /* 0x0004 */ ++ volatile unsigned long p1_ctl; /* 0x0008 */ ++ volatile unsigned long p2_ctl; /* 0x000C */ ++ volatile unsigned long p0_vlan; /* 0x0010 */ ++ volatile unsigned long p1_vlan; /* 0x0014 */ ++ volatile unsigned long p2_vlan; /* 0x0018 */ ++ volatile unsigned long reserved1[1]; /* 0x001C */ ++ volatile unsigned long p0_inctl; /* 0x0020 */ ++ volatile unsigned long p1_inctl; /* 0x0024 */ ++ volatile unsigned long p2_inctl; /* 0x0028 */ ++ volatile unsigned long reserved2[1]; /* 0x002C */ ++ volatile unsigned long p0_ecs_q32; /* 0x0030 */ ++ volatile unsigned long p0_ecs_q10; /* 0x0034 */ ++ volatile unsigned long p0_ecw_q32; /* 0x0038 */ ++ volatile unsigned long p0_ecw_q10; /* 0x003C */ ++ volatile unsigned long p1_ecs_q32; /* 0x0040 */ ++ volatile unsigned long p1_ecs_q10; /* 0x0044 */ ++ volatile unsigned long p1_ecw_q32; /* 0x0048 */ ++ volatile unsigned long p1_ecw_q10; /* 0x004C */ ++ volatile unsigned long p2_ecs_q32; /* 0x0050 */ ++ volatile unsigned long p2_ecs_q10; /* 0x0054 */ ++ volatile unsigned long p2_ecw_q32; /* 0x0058 */ ++ volatile unsigned long p2_ecw_q10; /* 0x005C */ ++ volatile unsigned long int_ena; /* 0x0060 */ ++ volatile unsigned long int_st; /* 0x0064 */ ++ volatile unsigned long sw_gctl0; /* 0x0068 */ ++ volatile unsigned long sw_gctl1; /* 0x006C */ ++ volatile unsigned long arp; /* 0x0070 */ ++ volatile unsigned long strm_ctl; /* 0x0074 */ ++ volatile unsigned long rgmii_ctl; /* 0x0078 */ ++ volatile unsigned long prt_1p; /* 0x007C */ ++ volatile unsigned long gbkt_szbs; /* 0x0080 */ ++ volatile unsigned long gbkt_szebs; /* 0x0084 */ ++ volatile unsigned long bf_th; /* 0x0088 */ ++ volatile unsigned long pmac_hd_ctl; /* 0x008C */ ++ volatile unsigned long pmac_sa1; /* 0x0090 */ ++ volatile unsigned long pmac_sa2; /* 0x0094 */ ++ volatile unsigned long pmac_da1; /* 0x0098 */ ++ volatile unsigned long pmac_da2; /* 0x009C */ ++ volatile unsigned long pmac_vlan; /* 0x00A0 */ ++ volatile unsigned long pmac_tx_ipg; /* 0x00A4 */ ++ volatile unsigned long pmac_rx_ipg; /* 0x00A8 */ ++ volatile unsigned long adr_tb_ctl0; /* 0x00AC */ ++ volatile unsigned long adr_tb_ctl1; /* 0x00B0 */ ++ volatile unsigned long adr_tb_ctl2; /* 0x00B4 */ ++ volatile unsigned long adr_tb_st0; /* 0x00B8 */ ++ volatile unsigned long adr_tb_st1; /* 0x00BC */ ++ volatile unsigned long adr_tb_st2; /* 0x00C0 */ ++ volatile unsigned long rmon_ctl; /* 0x00C4 */ ++ volatile unsigned long rmon_st; /* 0x00C8 */ ++ volatile unsigned long mdio_ctl; /* 0x00CC */ ++ volatile unsigned long mdio_data; /* 0x00D0 */ ++ volatile unsigned long tp_flt_act; /* 0x00D4 */ ++ volatile unsigned long prtcl_flt_act; /* 0x00D8 */ ++ volatile unsigned long reserved4[9]; /* 0xdc */ ++ volatile unsigned long vlan_flt0; /* 0x0100 */ ++ volatile unsigned long vlan_flt1; /* 0x0104 */ ++ volatile unsigned long vlan_flt2; /* 0x0108 */ ++ volatile unsigned long vlan_flt3; /* 0x010C */ ++ volatile unsigned long vlan_flt4; /* 0x0110 */ ++ volatile unsigned long vlan_flt5; /* 0x0114 */ ++ volatile unsigned long vlan_flt6; /* 0x0118 */ ++ volatile unsigned long vlan_flt7; /* 0x011C */ ++ volatile unsigned long vlan_flt8; /* 0x0120 */ ++ volatile unsigned long vlan_flt9; /* 0x0124 */ ++ volatile unsigned long vlan_flt10; /* 0x0128 */ ++ volatile unsigned long vlan_flt11; /* 0x012C */ ++ volatile unsigned long vlan_flt12; /* 0x0130 */ ++ volatile unsigned long vlan_flt13; /* 0x0134 */ ++ volatile unsigned long vlan_flt14; /* 0x0138 */ ++ volatile unsigned long vlan_flt15; /* 0x013C */ ++ volatile unsigned long tp_flt10; /* 0x0140 */ ++ volatile unsigned long tp_flt32; /* 0x0144 */ ++ volatile unsigned long tp_flt54; /* 0x0148 */ ++ volatile unsigned long tp_flt76; /* 0x014C */ ++ volatile unsigned long dfsrv_map0; /* 0x0150 */ ++ volatile unsigned long dfsrv_map1; /* 0x0154 */ ++ volatile unsigned long dfsrv_map2; /* 0x0158 */ ++ volatile unsigned long dfsrv_map3; /* 0x015C */ ++ volatile unsigned long tcp_pf0; /* 0x0160 */ ++ volatile unsigned long tcp_pf1; /* 0x0164 */ ++ volatile unsigned long tcp_pf2; /* 0x0168 */ ++ volatile unsigned long tcp_pf3; /* 0x016C */ ++ volatile unsigned long tcp_pf4; /* 0x0170 */ ++ volatile unsigned long tcp_pf5; /* 0x0174 */ ++ volatile unsigned long tcp_pf6; /* 0x0178 */ ++ volatile unsigned long tcp_pf7; /* 0x017C */ ++ volatile unsigned long ra_03_00; /* 0x0180 */ ++ volatile unsigned long ra_07_04; /* 0x0184 */ ++ volatile unsigned long ra_0b_08; /* 0x0188 */ ++ volatile unsigned long ra_0f_0c; /* 0x018C */ ++ volatile unsigned long ra_13_10; /* 0x0190 */ ++ volatile unsigned long ra_17_14; /* 0x0194 */ ++ volatile unsigned long ra_1b_18; /* 0x0198 */ ++ volatile unsigned long ra_1f_1c; /* 0x019C */ ++ volatile unsigned long ra_23_20; /* 0x01A0 */ ++ volatile unsigned long ra_27_24; /* 0x01A4 */ ++ volatile unsigned long ra_2b_28; /* 0x01A8 */ ++ volatile unsigned long ra_2f_2c; /* 0x01AC */ ++ volatile unsigned long prtcl_f0; /* 0x01B0 */ ++ volatile unsigned long prtcl_f1; /* 0x01B4 */ ++}; ++ ++/******************************************************************************* ++ * ES ++ ******************************************************************************/ ++#define LTQ_ES_PS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0000)) ++#define LTQ_ES_P0_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0004)) ++#define LTQ_ES_P1_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0008)) ++#define LTQ_ES_P2_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x000C)) ++#define LTQ_ES_P0_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) ++#define LTQ_ES_P1_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0014)) ++#define LTQ_ES_P2_VLAN_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0010)) ++#define LTQ_ES_P0_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0020)) ++#define LTQ_ES_P1_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0024)) ++#define LTQ_ES_P2_INCTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0028)) ++#define LTQ_ES_P0_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) ++#define LTQ_ES_P0_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) ++#define LTQ_ES_P0_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) ++#define LTQ_ES_P0_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) ++#define LTQ_ES_P1_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) ++#define LTQ_ES_P1_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) ++#define LTQ_ES_P1_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) ++#define LTQ_ES_P1_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) ++#define LTQ_ES_P2_ECS_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0030)) ++#define LTQ_ES_P2_ECS_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0034)) ++#define LTQ_ES_P2_ECW_Q32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0038)) ++#define LTQ_ES_P2_ECW_Q10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x003C)) ++#define LTQ_ES_INT_ENA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0060)) ++#define LTQ_ES_INT_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0064)) ++#define LTQ_ES_SW_GCTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0068)) ++#define LTQ_ES_SW_GCTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x006C)) ++#define LTQ_ES_ARP_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0070)) ++#define LTQ_ES_STRM_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0074)) ++#define LTQ_ES_RGMII_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0078)) ++#define LTQ_ES_PRT_1P_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x007C)) ++#define LTQ_ES_GBKT_SZBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0080)) ++#define LTQ_ES_GBKT_SZEBS_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0084)) ++#define LTQ_ES_BF_TH_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0088)) ++#define LTQ_ES_PMAC_HD_CTL ((volatile unsigned int*)(LTQ_ES_BASE + 0x008C)) ++#define LTQ_ES_PMAC_SA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0090)) ++#define LTQ_ES_PMAC_SA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0094)) ++#define LTQ_ES_PMAC_DA1 ((volatile unsigned int*)(LTQ_ES_BASE + 0x0098)) ++#define LTQ_ES_PMAC_DA2 ((volatile unsigned int*)(LTQ_ES_BASE + 0x009C)) ++#define LTQ_ES_PMAC_VLAN ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A0)) ++#define LTQ_ES_PMAC_TX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A4)) ++#define LTQ_ES_PMAC_RX_IPG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00A8)) ++#define LTQ_ES_ADR_TB_CTL0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00AC)) ++#define LTQ_ES_ADR_TB_CTL1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B0)) ++#define LTQ_ES_ADR_TB_CTL2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B4)) ++#define LTQ_ES_ADR_TB_ST0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00B8)) ++#define LTQ_ES_ADR_TB_ST1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00BC)) ++#define LTQ_ES_ADR_TB_ST2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C0)) ++#define LTQ_ES_RMON_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C4)) ++#define LTQ_ES_RMON_ST_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00C8)) ++#define LTQ_ES_MDIO_CTL_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00CC)) ++#define LTQ_ES_MDIO_DATA_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D0)) ++#define LTQ_ES_TP_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D4)) ++#define LTQ_ES_PRTCL_FLT_ACT_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x00D8)) ++#define LTQ_ES_VLAN_FLT0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0100)) ++#define LTQ_ES_VLAN_FLT1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0104)) ++#define LTQ_ES_VLAN_FLT2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0108)) ++#define LTQ_ES_VLAN_FLT3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x010C)) ++#define LTQ_ES_VLAN_FLT4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0110)) ++#define LTQ_ES_VLAN_FLT5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0114)) ++#define LTQ_ES_VLAN_FLT6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0118)) ++#define LTQ_ES_VLAN_FLT7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x011C)) ++#define LTQ_ES_VLAN_FLT8_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0120)) ++#define LTQ_ES_VLAN_FLT9_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0124)) ++#define LTQ_ES_VLAN_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0128)) ++#define LTQ_ES_VLAN_FLT11_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x012C)) ++#define LTQ_ES_VLAN_FLT12_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0130)) ++#define LTQ_ES_VLAN_FLT13_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0134)) ++#define LTQ_ES_VLAN_FLT14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0138)) ++#define LTQ_ES_VLAN_FLT15_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x013C)) ++#define LTQ_ES_TP_FLT10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0140)) ++#define LTQ_ES_TP_FLT32_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0144)) ++#define LTQ_ES_TP_FLT54_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0148)) ++#define LTQ_ES_TP_FLT76_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x014C)) ++#define LTQ_ES_DFSRV_MAP0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0150)) ++#define LTQ_ES_DFSRV_MAP1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0154)) ++#define LTQ_ES_DFSRV_MAP2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0158)) ++#define LTQ_ES_DFSRV_MAP3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x015C)) ++#define LTQ_ES_TCP_PF0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0160)) ++#define LTQ_ES_TCP_PF1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0164)) ++#define LTQ_ES_TCP_PF2_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0168)) ++#define LTQ_ES_TCP_PF3_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x016C)) ++#define LTQ_ES_TCP_PF4_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0170)) ++#define LTQ_ES_TCP_PF5_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0174)) ++#define LTQ_ES_TCP_PF6_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0178)) ++#define LTQ_ES_TCP_PF7_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x017C)) ++#define LTQ_ES_RA_03_00_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0180)) ++#define LTQ_ES_RA_07_04_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0184)) ++#define LTQ_ES_RA_0B_08_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0188)) ++#define LTQ_ES_RA_0F_0C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x018C)) ++#define LTQ_ES_RA_13_10_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0190)) ++#define LTQ_ES_RA_17_14_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0194)) ++#define LTQ_ES_RA_1B_18_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x0198)) ++#define LTQ_ES_RA_1F_1C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x019C)) ++#define LTQ_ES_RA_23_20_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A0)) ++#define LTQ_ES_RA_27_24_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A4)) ++#define LTQ_ES_RA_2B_28_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01A8)) ++#define LTQ_ES_RA_2F_2C_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01AC)) ++#define LTQ_ES_PRTCL_F0_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B0)) ++#define LTQ_ES_PRTCL_F1_REG ((volatile unsigned int*)(LTQ_ES_BASE + 0x01B4)) ++ ++/******************************************************************************* ++ * Port Status Register ++ ******************************************************************************/ ++ ++/* Port 1 Flow Control Status (12) */ ++#define LTQ_ES_PS_REG_P1FCS (0x1 << 12) ++#define LTQ_ES_PS_REG_P1FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P1FCS) >> 12) & 0x1) ++/* Port 1 Duplex Status (11) */ ++#define LTQ_ES_PS_REG_P1DS (0x1 << 11) ++#define LTQ_ES_PS_REG_P1DS_GET(val) ((((val) & LTQ_ES_PS_REG_P1DS) >> 11) & 0x1) ++/* Port 1 Speed High Status (10) */ ++#define LTQ_ES_PS_REG_P1SHS (0x1 << 10) ++#define LTQ_ES_PS_REG_P1SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SHS) >> 10) & 0x1) ++/* Port 1 Speed Status (9) */ ++#define LTQ_ES_PS_REG_P1SS (0x1 << 9) ++#define LTQ_ES_PS_REG_P1SS_GET(val) ((((val) & LTQ_ES_PS_REG_P1SS) >> 9) & 0x1) ++/* Port 1 Link Status (8) */ ++#define LTQ_ES_PS_REG_P1LS (0x1 << 8) ++#define LTQ_ES_PS_REG_P1LS_GET(val) ((((val) & LTQ_ES_PS_REG_P1LS) >> 8) & 0x1) ++/* Port 0 Flow Control Status (4) */ ++#define LTQ_ES_PS_REG_P0FCS (0x1 << 4) ++#define LTQ_ES_PS_REG_P0FCS_GET(val) ((((val) & LTQ_ES_PS_REG_P0FCS) >> 4) & 0x1) ++/* Port 0 Duplex Status (3) */ ++#define LTQ_ES_PS_REG_P0DS (0x1 << 3) ++#define LTQ_ES_PS_REG_P0DS_GET(val) ((((val) & LTQ_ES_PS_REG_P0DS) >> 3) & 0x1) ++/* Port 0 Speed High Status (2) */ ++#define LTQ_ES_PS_REG_P0SHS (0x1 << 2) ++#define LTQ_ES_PS_REG_P0SHS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SHS) >> 2) & 0x1) ++/* Port 0 Speed Status (1) */ ++#define LTQ_ES_PS_REG_P0SS (0x1 << 1) ++#define LTQ_ES_PS_REG_P0SS_GET(val) ((((val) & LTQ_ES_PS_REG_P0SS) >> 1) & 0x1) ++/* Port 0 Link Status (0) */ ++#define LTQ_ES_PS_REG_P0LS (0x1) ++#define LTQ_ES_PS_REG_P0LS_GET(val) ((((val) & LTQ_ES_PS_REG_P0LS) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * P0 Control Register ++ ******************************************************************************/ ++ ++/* STP/RSTP port state (31:30) */ ++#define LTQ_ES_P0_CTL_REG_SPS (0x3 << 30) ++#define LTQ_ES_P0_CTL_REG_SPS_VAL(val) (((val) & 0x3) << 30) ++#define LTQ_ES_P0_CTL_REG_SPS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPS) >> 30) & 0x3) ++#define LTQ_ES_P0_CTL_REG_SPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPS) | (((val) & 0x3) << 30)) ++/* TCP/UDP PRIEN (29) */ ++#define LTQ_ES_P0_CTL_REG_TCPE (0x1 << 29) ++#define LTQ_ES_P0_CTL_REG_TCPE_VAL(val) (((val) & 0x1) << 29) ++#define LTQ_ES_P0_CTL_REG_TCPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TCPE) >> 29) & 0x1) ++#define LTQ_ES_P0_CTL_REG_TCPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TCPE) | (((val) & 0x1) << 29)) ++/* IP over TCP/UDP (28) */ ++#define LTQ_ES_P0_CTL_REG_IPOVTU (0x1 << 28) ++#define LTQ_ES_P0_CTL_REG_IPOVTU_VAL(val) (((val) & 0x1) << 28) ++#define LTQ_ES_P0_CTL_REG_IPOVTU_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPOVTU) >> 28) & 0x1) ++#define LTQ_ES_P0_CTL_REG_IPOVTU_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPOVTU) | (((val) & 0x1) << 28)) ++/* VLAN Priority Enable (27) */ ++#define LTQ_ES_P0_CTL_REG_VPE (0x1 << 27) ++#define LTQ_ES_P0_CTL_REG_VPE_VAL(val) (((val) & 0x1) << 27) ++#define LTQ_ES_P0_CTL_REG_VPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_VPE) >> 27) & 0x1) ++#define LTQ_ES_P0_CTL_REG_VPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_VPE) | (((val) & 0x1) << 27)) ++/* Service Priority Enable (26) */ ++#define LTQ_ES_P0_CTL_REG_SPE (0x1 << 26) ++#define LTQ_ES_P0_CTL_REG_SPE_VAL(val) (((val) & 0x1) << 26) ++#define LTQ_ES_P0_CTL_REG_SPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_SPE) >> 26) & 0x1) ++#define LTQ_ES_P0_CTL_REG_SPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_SPE) | (((val) & 0x1) << 26)) ++/* IP over VLAN PRI (25) */ ++#define LTQ_ES_P0_CTL_REG_IPVLAN (0x1 << 25) ++#define LTQ_ES_P0_CTL_REG_IPVLAN_VAL(val) (((val) & 0x1) << 25) ++#define LTQ_ES_P0_CTL_REG_IPVLAN_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPVLAN) >> 25) & 0x1) ++#define LTQ_ES_P0_CTL_REG_IPVLAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPVLAN) | (((val) & 0x1) << 25)) ++/* Ether Type Priority Enable (24) */ ++#define LTQ_ES_P0_CTL_REG_TPE (0x1 << 24) ++#define LTQ_ES_P0_CTL_REG_TPE_VAL(val) (((val) & 0x1) << 24) ++#define LTQ_ES_P0_CTL_REG_TPE_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_TPE) >> 24) & 0x1) ++#define LTQ_ES_P0_CTL_REG_TPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_TPE) | (((val) & 0x1) << 24)) ++/* Force Link Up (18) */ ++#define LTQ_ES_P0_CTL_REG_FLP (0x1 << 18) ++#define LTQ_ES_P0_CTL_REG_FLP_VAL(val) (((val) & 0x1) << 18) ++#define LTQ_ES_P0_CTL_REG_FLP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLP) >> 18) & 0x1) ++#define LTQ_ES_P0_CTL_REG_FLP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLP) | (((val) & 0x1) << 18)) ++/* Force Link Down (17) */ ++#define LTQ_ES_P0_CTL_REG_FLD (0x1 << 17) ++#define LTQ_ES_P0_CTL_REG_FLD_VAL(val) (((val) & 0x1) << 17) ++#define LTQ_ES_P0_CTL_REG_FLD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_FLD) >> 17) & 0x1) ++#define LTQ_ES_P0_CTL_REG_FLD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_FLD) | (((val) & 0x1) << 17)) ++/* Ratio Mode for WFQ (16) */ ++#define LTQ_ES_P0_CTL_REG_RMWFQ (0x1 << 16) ++#define LTQ_ES_P0_CTL_REG_RMWFQ_VAL(val) (((val) & 0x1) << 16) ++#define LTQ_ES_P0_CTL_REG_RMWFQ_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_RMWFQ) >> 16) & 0x1) ++#define LTQ_ES_P0_CTL_REG_RMWFQ_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_RMWFQ) | (((val) & 0x1) << 16)) ++/* Aging Disable (15) */ ++#define LTQ_ES_P0_CTL_REG_AD (0x1 << 15) ++#define LTQ_ES_P0_CTL_REG_AD_VAL(val) (((val) & 0x1) << 15) ++#define LTQ_ES_P0_CTL_REG_AD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_AD) >> 15) & 0x1) ++#define LTQ_ES_P0_CTL_REG_AD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_AD) | (((val) & 0x1) << 15)) ++/* Learning Disable (14) */ ++#define LTQ_ES_P0_CTL_REG_LD (0x1 << 14) ++#define LTQ_ES_P0_CTL_REG_LD_VAL(val) (((val) & 0x1) << 14) ++#define LTQ_ES_P0_CTL_REG_LD_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_LD) >> 14) & 0x1) ++#define LTQ_ES_P0_CTL_REG_LD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_LD) | (((val) & 0x1) << 14)) ++/* Maximum Number of Addresses (12:8) */ ++#define LTQ_ES_P0_CTL_REG_MNA024 (0x1f << 8) ++#define LTQ_ES_P0_CTL_REG_MNA024_VAL(val) (((val) & 0x1f) << 8) ++#define LTQ_ES_P0_CTL_REG_MNA024_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_MNA024) >> 8) & 0x1f) ++#define LTQ_ES_P0_CTL_REG_MNA024_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_MNA024) | (((val) & 0x1f) << 8)) ++/* PPPOE Port Only (7) */ ++#define LTQ_ES_P0_CTL_REG_PPPOEP (0x1 << 7) ++#define LTQ_ES_P0_CTL_REG_PPPOEP_VAL(val) (((val) & 0x1) << 7) ++#define LTQ_ES_P0_CTL_REG_PPPOEP_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PPPOEP) >> 7) & 0x1) ++#define LTQ_ES_P0_CTL_REG_PPPOEP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PPPOEP) | (((val) & 0x1) << 7)) ++/* PPPOE Manage (6) */ ++#define LTQ_ES_P0_CTL_REG_PM (0x1 << 6) ++#define LTQ_ES_P0_CTL_REG_PM_VAL(val) (((val) & 0x1) << 6) ++#define LTQ_ES_P0_CTL_REG_PM_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PM) >> 6) & 0x1) ++#define LTQ_ES_P0_CTL_REG_PM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PM) | (((val) & 0x1) << 6)) ++/* Port Mirror Option (5:4) */ ++#define LTQ_ES_P0_CTL_REG_IPMO (0x3 << 4) ++#define LTQ_ES_P0_CTL_REG_IPMO_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_P0_CTL_REG_IPMO_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_IPMO) >> 4) & 0x3) ++#define LTQ_ES_P0_CTL_REG_IPMO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_IPMO) | (((val) & 0x3) << 4)) ++/* 802.1x Port Authorized state (3:2) */ ++#define LTQ_ES_P0_CTL_REG_PAS (0x3 << 2) ++#define LTQ_ES_P0_CTL_REG_PAS_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_P0_CTL_REG_PAS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_PAS) >> 2) & 0x3) ++#define LTQ_ES_P0_CTL_REG_PAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_PAS) | (((val) & 0x3) << 2)) ++/* Drop Scheme for voilation 802.1x (1) */ ++#define LTQ_ES_P0_CTL_REG_DSV8021X (0x1 << 1) ++#define LTQ_ES_P0_CTL_REG_DSV8021X_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_ES_P0_CTL_REG_DSV8021X_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_DSV8021X) >> 1) & 0x1) ++#define LTQ_ES_P0_CTL_REG_DSV8021X_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_DSV8021X) | (((val) & 0x1) << 1)) ++/* ByPass Mode for Output (0) */ ++#define LTQ_ES_P0_CTL_REG_BYPASS (0x1) ++#define LTQ_ES_P0_CTL_REG_BYPASS_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_ES_P0_CTL_REG_BYPASS_GET(val) ((((val) & LTQ_ES_P0_CTL_REG_BYPASS) >> 0) & 0x1) ++#define LTQ_ES_P0_CTL_REG_BYPASS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_CTL_REG_BYPASS) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 0 VLAN Control Register ++ ******************************************************************************/ ++ ++/* Default FID (31:30) */ ++#define LTQ_ES_P0_VLAN_REG_DFID (0x3 << 30) ++#define LTQ_ES_P0_VLAN_REG_DFID_VAL(val) (((val) & 0x3) << 30) ++#define LTQ_ES_P0_VLAN_REG_DFID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DFID) >> 30) & 0x3) ++#define LTQ_ES_P0_VLAN_REG_DFID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DFID) | (((val) & 0x3) << 30)) ++/* Tagged Base VLAN Enable (29) */ ++#define LTQ_ES_P0_VLAN_REG_TBVE (0x1 << 29) ++#define LTQ_ES_P0_VLAN_REG_TBVE_VAL(val) (((val) & 0x1) << 29) ++#define LTQ_ES_P0_VLAN_REG_TBVE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_TBVE) >> 29) & 0x1) ++#define LTQ_ES_P0_VLAN_REG_TBVE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_TBVE) | (((val) & 0x1) << 29)) ++/* Input Force No TAG Enable (28) */ ++#define LTQ_ES_P0_VLAN_REG_IFNTE (0x1 << 28) ++#define LTQ_ES_P0_VLAN_REG_IFNTE_VAL(val) (((val) & 0x1) << 28) ++#define LTQ_ES_P0_VLAN_REG_IFNTE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_IFNTE) >> 28) & 0x1) ++#define LTQ_ES_P0_VLAN_REG_IFNTE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_IFNTE) | (((val) & 0x1) << 28)) ++/* VID Check with the VID table (27) */ ++#define LTQ_ES_P0_VLAN_REG_VC (0x1 << 27) ++#define LTQ_ES_P0_VLAN_REG_VC_VAL(val) (((val) & 0x1) << 27) ++#define LTQ_ES_P0_VLAN_REG_VC_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VC) >> 27) & 0x1) ++#define LTQ_ES_P0_VLAN_REG_VC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VC) | (((val) & 0x1) << 27)) ++/* VLAN Security Disable (26) */ ++#define LTQ_ES_P0_VLAN_REG_VSD (0x1 << 26) ++#define LTQ_ES_P0_VLAN_REG_VSD_VAL(val) (((val) & 0x1) << 26) ++#define LTQ_ES_P0_VLAN_REG_VSD_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VSD) >> 26) & 0x1) ++#define LTQ_ES_P0_VLAN_REG_VSD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VSD) | (((val) & 0x1) << 26)) ++/* Admit Only VLAN_Tagged Packet (25) */ ++#define LTQ_ES_P0_VLAN_REG_AOVTP (0x1 << 25) ++#define LTQ_ES_P0_VLAN_REG_AOVTP_VAL(val) (((val) & 0x1) << 25) ++#define LTQ_ES_P0_VLAN_REG_AOVTP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_AOVTP) >> 25) & 0x1) ++#define LTQ_ES_P0_VLAN_REG_AOVTP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_AOVTP) | (((val) & 0x1) << 25)) ++/* VLAN Member Check Enable (24) */ ++#define LTQ_ES_P0_VLAN_REG_VMCE (0x1 << 24) ++#define LTQ_ES_P0_VLAN_REG_VMCE_VAL(val) (((val) & 0x1) << 24) ++#define LTQ_ES_P0_VLAN_REG_VMCE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_VMCE) >> 24) & 0x1) ++#define LTQ_ES_P0_VLAN_REG_VMCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_VMCE) | (((val) & 0x1) << 24)) ++/* Reserved (23:19) */ ++#define LTQ_ES_P0_VLAN_REG_RES (0x1f << 19) ++#define LTQ_ES_P0_VLAN_REG_RES_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_RES) >> 19) & 0x1f) ++/* Default VLAN Port Map (18:16) */ ++#define LTQ_ES_P0_VLAN_REG_DVPM (0x7 << 16) ++#define LTQ_ES_P0_VLAN_REG_DVPM_VAL(val) (((val) & 0x7) << 16) ++#define LTQ_ES_P0_VLAN_REG_DVPM_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_DVPM) >> 16) & 0x7) ++#define LTQ_ES_P0_VLAN_REG_DVPM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_DVPM) | (((val) & 0x7) << 16)) ++/* Port Priority (15:14) */ ++#define LTQ_ES_P0_VLAN_REG_PP (0x3 << 14) ++#define LTQ_ES_P0_VLAN_REG_PP_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_P0_VLAN_REG_PP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PP) >> 14) & 0x3) ++#define LTQ_ES_P0_VLAN_REG_PP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PP) | (((val) & 0x3) << 14)) ++/* Port Priority Enable (13) */ ++#define LTQ_ES_P0_VLAN_REG_PPE (0x1 << 13) ++#define LTQ_ES_P0_VLAN_REG_PPE_VAL(val) (((val) & 0x1) << 13) ++#define LTQ_ES_P0_VLAN_REG_PPE_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PPE) >> 13) & 0x1) ++#define LTQ_ES_P0_VLAN_REG_PPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PPE) | (((val) & 0x1) << 13)) ++/* Portbase VLAN tag member for Port 0 (12) */ ++#define LTQ_ES_P0_VLAN_REG_PVTAGMP (0x1 << 12) ++#define LTQ_ES_P0_VLAN_REG_PVTAGMP_VAL(val) (((val) & 0x1) << 12) ++#define LTQ_ES_P0_VLAN_REG_PVTAGMP_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVTAGMP) >> 12) & 0x1) ++#define LTQ_ES_P0_VLAN_REG_PVTAGMP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVTAGMP) | (((val) & 0x1) << 12)) ++/* PVID (11:0) */ ++#define LTQ_ES_P0_VLAN_REG_PVID (0xfff) ++#define LTQ_ES_P0_VLAN_REG_PVID_VAL(val) (((val) & 0xfff) << 0) ++#define LTQ_ES_P0_VLAN_REG_PVID_GET(val) ((((val) & LTQ_ES_P0_VLAN_REG_PVID) >> 0) & 0xfff) ++#define LTQ_ES_P0_VLAN_REG_PVID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_VLAN_REG_PVID) | (((val) & 0xfff) << 0)) ++ ++/******************************************************************************* ++ * Port 0 Ingress Control Register ++ ******************************************************************************/ ++ ++/* Reserved (31:13) */ ++#define LTQ_ES_P0_INCTL_REG_RES (0x7ffff << 13) ++#define LTQ_ES_P0_INCTL_REG_RES_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_RES) >> 13) & 0x7ffff) ++/* Port 0 Ingress/Egress Timer Tick T selection (12:11) */ ++#define LTQ_ES_P0_INCTL_REG_P0ITT (0x3 << 11) ++#define LTQ_ES_P0_INCTL_REG_P0ITT_VAL(val) (((val) & 0x3) << 11) ++#define LTQ_ES_P0_INCTL_REG_P0ITT_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITT) >> 11) & 0x3) ++#define LTQ_ES_P0_INCTL_REG_P0ITT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITT) | (((val) & 0x3) << 11)) ++/* Port 0 Igress Token R (10:0) */ ++#define LTQ_ES_P0_INCTL_REG_P0ITR (0x7ff) ++#define LTQ_ES_P0_INCTL_REG_P0ITR_VAL(val) (((val) & 0x7ff) << 0) ++#define LTQ_ES_P0_INCTL_REG_P0ITR_GET(val) ((((val) & LTQ_ES_P0_INCTL_REG_P0ITR) >> 0) & 0x7ff) ++#define LTQ_ES_P0_INCTL_REG_P0ITR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_INCTL_REG_P0ITR) | (((val) & 0x7ff) << 0)) ++ ++/******************************************************************************* ++ * Port 0 Egress Control for Strict Q32 Register ++ ******************************************************************************/ ++ ++/* Port 0 Egress Token R for Strict Priority Q3 (26:16) */ ++#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR (0x7ff << 16) ++#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_VAL(val) (((val) & 0x7ff) << 16) ++#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) >> 16) & 0x7ff) ++#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ3TR) | (((val) & 0x7ff) << 16)) ++/* Port 0 Egress Token R for Strict Priority Q2 (10:0) */ ++#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR (0x7ff) ++#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_VAL(val) (((val) & 0x7ff) << 0) ++#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) >> 0) & 0x7ff) ++#define LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q32_REG_P0SPQ2TR) | (((val) & 0x7ff) << 0)) ++ ++/******************************************************************************* ++ * Port 0 Egress Control for Strict Q10 Register ++ ******************************************************************************/ ++ ++/* Reserved (31:27) */ ++#define LTQ_ES_P0_ECS_Q10_REG_RES (0x1f << 27) ++#define LTQ_ES_P0_ECS_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_RES) >> 27) & 0x1f) ++/* Port 0 Egress Token R for Strict Priority Q1 (26:16) */ ++#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR (0x7ff << 16) ++#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_VAL(val) (((val) & 0x7ff) << 16) ++#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) >> 16) & 0x7ff) ++#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ1TR) | (((val) & 0x7ff) << 16)) ++/* Port 0 Egress Token R for Strict Priority Q0 (10:0) */ ++#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR (0x7ff) ++#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_VAL(val) (((val) & 0x7ff) << 0) ++#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) >> 0) & 0x7ff) ++#define LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECS_Q10_REG_P0SPQ0TR) | (((val) & 0x7ff) << 0)) ++ ++/******************************************************************************* ++ * Port 0 Egress Control for WFQ Q32 Register ++ ******************************************************************************/ ++ ++/* Reserved (31:27) */ ++#define LTQ_ES_P0_ECW_Q32_REG_RES (0x1f << 27) ++#define LTQ_ES_P0_ECW_Q32_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_RES) >> 27) & 0x1f) ++/* Port 0 Egress Token R for WFQ Q3 (26:16) */ ++#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR (0x7ff << 16) ++#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_VAL(val) (((val) & 0x7ff) << 16) ++#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) >> 16) & 0x7ff) ++#define LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ3TR) | (((val) & 0x7ff) << 16)) ++/* Port 0 Egress Token R for WFQ Q2 (10:0) */ ++#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR (0x7ff) ++#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_VAL(val) (((val) & 0x7ff) << 0) ++#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) >> 0) & 0x7ff) ++#define LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q32_REG_P0WQ2TR) | (((val) & 0x7ff) << 0)) ++ ++/******************************************************************************* ++ * Port 0 Egress Control for WFQ Q10 Register ++ ******************************************************************************/ ++ ++/* Reserved (31:27) */ ++#define LTQ_ES_P0_ECW_Q10_REG_RES (0x1f << 27) ++#define LTQ_ES_P0_ECW_Q10_REG_RES_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_RES) >> 27) & 0x1f) ++/* Port 0 Egress Token R for WFQ Q1 (26:16) */ ++#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR (0x7ff << 16) ++#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_VAL(val) (((val) & 0x7ff) << 16) ++#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) >> 16) & 0x7ff) ++#define LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ1TR) | (((val) & 0x7ff) << 16)) ++/* Port 0 Egress Token R for WFQ Q0 (10:0) */ ++#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR (0x7ff) ++#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_VAL(val) (((val) & 0x7ff) << 0) ++#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_GET(val) ((((val) & LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) >> 0) & 0x7ff) ++#define LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_P0_ECW_Q10_REG_P0WQ0TR) | (((val) & 0x7ff) << 0)) ++ ++/******************************************************************************* ++ * Interrupt Enable Register ++ ******************************************************************************/ ++ ++/* Reserved (31:8) */ ++#define LTQ_ES_INT_ENA_REG_RES (0xffffff << 8) ++#define LTQ_ES_INT_ENA_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_RES) >> 8) & 0xffffff) ++/* Data Buffer is Full Interrupt Enable (7) */ ++#define LTQ_ES_INT_ENA_REG_DBFIE (0x1 << 7) ++#define LTQ_ES_INT_ENA_REG_DBFIE_VAL(val) (((val) & 0x1) << 7) ++#define LTQ_ES_INT_ENA_REG_DBFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBFIE) >> 7) & 0x1) ++#define LTQ_ES_INT_ENA_REG_DBFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBFIE) | (((val) & 0x1) << 7)) ++/* Data Buffer is nearly Full Interrupt Enable (6) */ ++#define LTQ_ES_INT_ENA_REG_DBNFIE (0x1 << 6) ++#define LTQ_ES_INT_ENA_REG_DBNFIE_VAL(val) (((val) & 0x1) << 6) ++#define LTQ_ES_INT_ENA_REG_DBNFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_DBNFIE) >> 6) & 0x1) ++#define LTQ_ES_INT_ENA_REG_DBNFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_DBNFIE) | (((val) & 0x1) << 6)) ++/* Learning Table Full Interrupt Enable (5) */ ++#define LTQ_ES_INT_ENA_REG_LTFIE (0x1 << 5) ++#define LTQ_ES_INT_ENA_REG_LTFIE_VAL(val) (((val) & 0x1) << 5) ++#define LTQ_ES_INT_ENA_REG_LTFIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTFIE) >> 5) & 0x1) ++#define LTQ_ES_INT_ENA_REG_LTFIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTFIE) | (((val) & 0x1) << 5)) ++/* Leaning Table Access Done Interrupt Enable (4) */ ++#define LTQ_ES_INT_ENA_REG_LTADIE (0x1 << 4) ++#define LTQ_ES_INT_ENA_REG_LTADIE_VAL(val) (((val) & 0x1) << 4) ++#define LTQ_ES_INT_ENA_REG_LTADIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_LTADIE) >> 4) & 0x1) ++#define LTQ_ES_INT_ENA_REG_LTADIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_LTADIE) | (((val) & 0x1) << 4)) ++/* Port Security Violation Interrupt Enable (3:1) */ ++#define LTQ_ES_INT_ENA_REG_PSVIE (0x7 << 1) ++#define LTQ_ES_INT_ENA_REG_PSVIE_VAL(val) (((val) & 0x7) << 1) ++#define LTQ_ES_INT_ENA_REG_PSVIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSVIE) >> 1) & 0x7) ++#define LTQ_ES_INT_ENA_REG_PSVIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSVIE) | (((val) & 0x7) << 1)) ++/* Port Status Change Interrupt Enable (0) */ ++#define LTQ_ES_INT_ENA_REG_PSCIE (0x1) ++#define LTQ_ES_INT_ENA_REG_PSCIE_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_ES_INT_ENA_REG_PSCIE_GET(val) ((((val) & LTQ_ES_INT_ENA_REG_PSCIE) >> 0) & 0x1) ++#define LTQ_ES_INT_ENA_REG_PSCIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_INT_ENA_REG_PSCIE) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Interrupt Status Register ++ ******************************************************************************/ ++ ++/* Reserved (31:8) */ ++#define LTQ_ES_INT_ST_REG_RES (0xffffff << 8) ++#define LTQ_ES_INT_ST_REG_RES_GET(val) ((((val) & LTQ_ES_INT_ST_REG_RES) >> 8) & 0xffffff) ++/* Data Buffer is Full (7) */ ++#define LTQ_ES_INT_ST_REG_DBF (0x1 << 7) ++#define LTQ_ES_INT_ST_REG_DBF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBF) >> 7) & 0x1) ++/* Data Buffer is nearly Full (6) */ ++#define LTQ_ES_INT_ST_REG_DBNF (0x1 << 6) ++#define LTQ_ES_INT_ST_REG_DBNF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_DBNF) >> 6) & 0x1) ++/* Learning Table Full (5) */ ++#define LTQ_ES_INT_ST_REG_LTF (0x1 << 5) ++#define LTQ_ES_INT_ST_REG_LTF_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTF) >> 5) & 0x1) ++/* Leaning Table Access Done (4) */ ++#define LTQ_ES_INT_ST_REG_LTAD (0x1 << 4) ++#define LTQ_ES_INT_ST_REG_LTAD_GET(val) ((((val) & LTQ_ES_INT_ST_REG_LTAD) >> 4) & 0x1) ++/* Port Security Violation (3:1) */ ++#define LTQ_ES_INT_ST_REG_PSV (0x7 << 1) ++#define LTQ_ES_INT_ST_REG_PSV_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSV) >> 1) & 0x7) ++/* Port Status Change (0) */ ++#define LTQ_ES_INT_ST_REG_PSC (0x1) ++#define LTQ_ES_INT_ST_REG_PSC_GET(val) ((((val) & LTQ_ES_INT_ST_REG_PSC) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Switch Global Control Register 0 ++ ******************************************************************************/ ++ ++/* Switch Enable (31) */ ++#define LTQ_ES_SW_GCTL0_REG_SE (0x1 << 31) ++#define LTQ_ES_SW_GCTL0_REG_SE_VAL(val) (((val) & 0x1) << 31) ++#define LTQ_ES_SW_GCTL0_REG_SE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SE) >> 31) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_SE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SE) | (((val) & 0x1) << 31)) ++/* CRC Check Disable (30) */ ++#define LTQ_ES_SW_GCTL0_REG_ICRCCD (0x1 << 30) ++#define LTQ_ES_SW_GCTL0_REG_ICRCCD_VAL(val) (((val) & 0x1) << 30) ++#define LTQ_ES_SW_GCTL0_REG_ICRCCD_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ICRCCD) >> 30) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_ICRCCD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ICRCCD) | (((val) & 0x1) << 30)) ++/* Replace VID0 (28) */ ++#define LTQ_ES_SW_GCTL0_REG_RVID0 (0x1 << 28) ++#define LTQ_ES_SW_GCTL0_REG_RVID0_VAL(val) (((val) & 0x1) << 28) ++#define LTQ_ES_SW_GCTL0_REG_RVID0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID0) >> 28) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_RVID0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID0) | (((val) & 0x1) << 28)) ++/* Replace VID1 (27) */ ++#define LTQ_ES_SW_GCTL0_REG_RVID1 (0x1 << 27) ++#define LTQ_ES_SW_GCTL0_REG_RVID1_VAL(val) (((val) & 0x1) << 27) ++#define LTQ_ES_SW_GCTL0_REG_RVID1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVID1) >> 27) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_RVID1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVID1) | (((val) & 0x1) << 27)) ++/* Replace VIDFFF (26) */ ++#define LTQ_ES_SW_GCTL0_REG_RVIDFFF (0x1 << 26) ++#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_VAL(val) (((val) & 0x1) << 26) ++#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_RVIDFFF) >> 26) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_RVIDFFF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_RVIDFFF) | (((val) & 0x1) << 26)) ++/* Priority Change Rule (25) */ ++#define LTQ_ES_SW_GCTL0_REG_PCR (0x1 << 25) ++#define LTQ_ES_SW_GCTL0_REG_PCR_VAL(val) (((val) & 0x1) << 25) ++#define LTQ_ES_SW_GCTL0_REG_PCR_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCR) >> 25) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_PCR_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCR) | (((val) & 0x1) << 25)) ++/* Priority Change Enable (24) */ ++#define LTQ_ES_SW_GCTL0_REG_PCE (0x1 << 24) ++#define LTQ_ES_SW_GCTL0_REG_PCE_VAL(val) (((val) & 0x1) << 24) ++#define LTQ_ES_SW_GCTL0_REG_PCE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PCE) >> 24) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_PCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PCE) | (((val) & 0x1) << 24)) ++/* Transmit Short IPG Enable (23) */ ++#define LTQ_ES_SW_GCTL0_REG_TSIPGE (0x1 << 23) ++#define LTQ_ES_SW_GCTL0_REG_TSIPGE_VAL(val) (((val) & 0x1) << 23) ++#define LTQ_ES_SW_GCTL0_REG_TSIPGE_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_TSIPGE) >> 23) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_TSIPGE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_TSIPGE) | (((val) & 0x1) << 23)) ++/* PHY Base Address (22) */ ++#define LTQ_ES_SW_GCTL0_REG_PHYBA (0x1 << 22) ++#define LTQ_ES_SW_GCTL0_REG_PHYBA_VAL(val) (((val) & 0x1) << 22) ++#define LTQ_ES_SW_GCTL0_REG_PHYBA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_PHYBA) >> 22) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_PHYBA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_PHYBA) | (((val) & 0x1) << 22)) ++/* Drop Packet When Excessive Collision Happen (21) */ ++#define LTQ_ES_SW_GCTL0_REG_DPWECH (0x1 << 21) ++#define LTQ_ES_SW_GCTL0_REG_DPWECH_VAL(val) (((val) & 0x1) << 21) ++#define LTQ_ES_SW_GCTL0_REG_DPWECH_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DPWECH) >> 21) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_DPWECH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DPWECH) | (((val) & 0x1) << 21)) ++/* Aging Timer Select (20:18) */ ++#define LTQ_ES_SW_GCTL0_REG_ATS (0x7 << 18) ++#define LTQ_ES_SW_GCTL0_REG_ATS_VAL(val) (((val) & 0x7) << 18) ++#define LTQ_ES_SW_GCTL0_REG_ATS_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_ATS) >> 18) & 0x7) ++#define LTQ_ES_SW_GCTL0_REG_ATS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_ATS) | (((val) & 0x7) << 18)) ++/* Mirror CRC Also (17) */ ++#define LTQ_ES_SW_GCTL0_REG_MCA (0x1 << 17) ++#define LTQ_ES_SW_GCTL0_REG_MCA_VAL(val) (((val) & 0x1) << 17) ++#define LTQ_ES_SW_GCTL0_REG_MCA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MCA) >> 17) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_MCA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MCA) | (((val) & 0x1) << 17)) ++/* Mirror RXER Also (16) */ ++#define LTQ_ES_SW_GCTL0_REG_MRA (0x1 << 16) ++#define LTQ_ES_SW_GCTL0_REG_MRA_VAL(val) (((val) & 0x1) << 16) ++#define LTQ_ES_SW_GCTL0_REG_MRA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MRA) >> 16) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_MRA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MRA) | (((val) & 0x1) << 16)) ++/* Mirror PAUSE Also (15) */ ++#define LTQ_ES_SW_GCTL0_REG_MPA (0x1 << 15) ++#define LTQ_ES_SW_GCTL0_REG_MPA_VAL(val) (((val) & 0x1) << 15) ++#define LTQ_ES_SW_GCTL0_REG_MPA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPA) >> 15) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_MPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPA) | (((val) & 0x1) << 15)) ++/* Mirror Long Also (14) */ ++#define LTQ_ES_SW_GCTL0_REG_MLA (0x1 << 14) ++#define LTQ_ES_SW_GCTL0_REG_MLA_VAL(val) (((val) & 0x1) << 14) ++#define LTQ_ES_SW_GCTL0_REG_MLA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MLA) >> 14) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_MLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MLA) | (((val) & 0x1) << 14)) ++/* Mirror Short Also (13) */ ++#define LTQ_ES_SW_GCTL0_REG_MSA (0x1 << 13) ++#define LTQ_ES_SW_GCTL0_REG_MSA_VAL(val) (((val) & 0x1) << 13) ++#define LTQ_ES_SW_GCTL0_REG_MSA_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MSA) >> 13) & 0x1) ++#define LTQ_ES_SW_GCTL0_REG_MSA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MSA) | (((val) & 0x1) << 13)) ++/* Sniffer port number (12:11) */ ++#define LTQ_ES_SW_GCTL0_REG_SNIFFPN (0x3 << 11) ++#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(val) (((val) & 0x3) << 11) ++#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_SNIFFPN) >> 11) & 0x3) ++#define LTQ_ES_SW_GCTL0_REG_SNIFFPN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_SNIFFPN) | (((val) & 0x3) << 11)) ++/* Max Packet Length (MAXPKTLEN) (9:8) */ ++#define LTQ_ES_SW_GCTL0_REG_MPL (0x3 << 8) ++#define LTQ_ES_SW_GCTL0_REG_MPL_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_SW_GCTL0_REG_MPL_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_MPL) >> 8) & 0x3) ++#define LTQ_ES_SW_GCTL0_REG_MPL_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_MPL) | (((val) & 0x3) << 8)) ++/* Discard Mode (Drop scheme for Packets Classified as Q3) (7:6) */ ++#define LTQ_ES_SW_GCTL0_REG_DMQ3 (0x3 << 6) ++#define LTQ_ES_SW_GCTL0_REG_DMQ3_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_SW_GCTL0_REG_DMQ3_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ3) >> 6) & 0x3) ++#define LTQ_ES_SW_GCTL0_REG_DMQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ3) | (((val) & 0x3) << 6)) ++/* Discard Mode (Drop scheme for Packets Classified as Q2) (5:4) */ ++#define LTQ_ES_SW_GCTL0_REG_DMQ2 (0x3 << 4) ++#define LTQ_ES_SW_GCTL0_REG_DMQ2_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_SW_GCTL0_REG_DMQ2_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ2) >> 4) & 0x3) ++#define LTQ_ES_SW_GCTL0_REG_DMQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ2) | (((val) & 0x3) << 4)) ++/* Discard Mode (Drop scheme for Packets Classified as Q1) (3:2) */ ++#define LTQ_ES_SW_GCTL0_REG_DMQ1 (0x3 << 2) ++#define LTQ_ES_SW_GCTL0_REG_DMQ1_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_SW_GCTL0_REG_DMQ1_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ1) >> 2) & 0x3) ++#define LTQ_ES_SW_GCTL0_REG_DMQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ1) | (((val) & 0x3) << 2)) ++/* Discard Mode (Drop scheme for Packets Classified as Q0) (1:0) */ ++#define LTQ_ES_SW_GCTL0_REG_DMQ0 (0x3) ++#define LTQ_ES_SW_GCTL0_REG_DMQ0_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_SW_GCTL0_REG_DMQ0_GET(val) ((((val) & LTQ_ES_SW_GCTL0_REG_DMQ0) >> 0) & 0x3) ++#define LTQ_ES_SW_GCTL0_REG_DMQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL0_REG_DMQ0) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * Switch Global Control Register 1 ++ ******************************************************************************/ ++ ++/* BIST Done (27) */ ++#define LTQ_ES_SW_GCTL1_REG_BISTDN (0x1 << 27) ++#define LTQ_ES_SW_GCTL1_REG_BISTDN_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BISTDN) >> 27) & 0x1) ++/* Enable drop scheme of TX and RX (26) */ ++#define LTQ_ES_SW_GCTL1_REG_EDSTX (0x1 << 26) ++#define LTQ_ES_SW_GCTL1_REG_EDSTX_VAL(val) (((val) & 0x1) << 26) ++#define LTQ_ES_SW_GCTL1_REG_EDSTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_EDSTX) >> 26) & 0x1) ++#define LTQ_ES_SW_GCTL1_REG_EDSTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_EDSTX) | (((val) & 0x1) << 26)) ++/* Congestion threshold for TX queue (25:24) */ ++#define LTQ_ES_SW_GCTL1_REG_CTTX (0x3 << 24) ++#define LTQ_ES_SW_GCTL1_REG_CTTX_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_SW_GCTL1_REG_CTTX_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_CTTX) >> 24) & 0x3) ++#define LTQ_ES_SW_GCTL1_REG_CTTX_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_CTTX) | (((val) & 0x3) << 24)) ++/* Input Jam Threshold (23:21) */ ++#define LTQ_ES_SW_GCTL1_REG_IJT (0x7 << 21) ++#define LTQ_ES_SW_GCTL1_REG_IJT_VAL(val) (((val) & 0x7) << 21) ++#define LTQ_ES_SW_GCTL1_REG_IJT_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_IJT) >> 21) & 0x7) ++#define LTQ_ES_SW_GCTL1_REG_IJT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_IJT) | (((val) & 0x7) << 21)) ++/* Do not Identify VLAN after SNAP (20) */ ++#define LTQ_ES_SW_GCTL1_REG_DIVS (0x1 << 20) ++#define LTQ_ES_SW_GCTL1_REG_DIVS_VAL(val) (((val) & 0x1) << 20) ++#define LTQ_ES_SW_GCTL1_REG_DIVS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIVS) >> 20) & 0x1) ++#define LTQ_ES_SW_GCTL1_REG_DIVS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIVS) | (((val) & 0x1) << 20)) ++/* Do not Identify IPV6 in PPPOE (19) */ ++#define LTQ_ES_SW_GCTL1_REG_DII6P (0x1 << 19) ++#define LTQ_ES_SW_GCTL1_REG_DII6P_VAL(val) (((val) & 0x1) << 19) ++#define LTQ_ES_SW_GCTL1_REG_DII6P_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DII6P) >> 19) & 0x1) ++#define LTQ_ES_SW_GCTL1_REG_DII6P_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DII6P) | (((val) & 0x1) << 19)) ++/* Do not Identify IP in PPPOE after SNAP (18) */ ++#define LTQ_ES_SW_GCTL1_REG_DIIPS (0x1 << 18) ++#define LTQ_ES_SW_GCTL1_REG_DIIPS_VAL(val) (((val) & 0x1) << 18) ++#define LTQ_ES_SW_GCTL1_REG_DIIPS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIPS) >> 18) & 0x1) ++#define LTQ_ES_SW_GCTL1_REG_DIIPS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIPS) | (((val) & 0x1) << 18)) ++/* Do not Identify Ether-Type = 0x0800, IP VER = 6 as IPV6 packets (17) */ ++#define LTQ_ES_SW_GCTL1_REG_DIE (0x1 << 17) ++#define LTQ_ES_SW_GCTL1_REG_DIE_VAL(val) (((val) & 0x1) << 17) ++#define LTQ_ES_SW_GCTL1_REG_DIE_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIE) >> 17) & 0x1) ++#define LTQ_ES_SW_GCTL1_REG_DIE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIE) | (((val) & 0x1) << 17)) ++/* Do not Identify IP in PPPOE (16) */ ++#define LTQ_ES_SW_GCTL1_REG_DIIP (0x1 << 16) ++#define LTQ_ES_SW_GCTL1_REG_DIIP_VAL(val) (((val) & 0x1) << 16) ++#define LTQ_ES_SW_GCTL1_REG_DIIP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIIP) >> 16) & 0x1) ++#define LTQ_ES_SW_GCTL1_REG_DIIP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIIP) | (((val) & 0x1) << 16)) ++/* Do not Identify SNAP (15) */ ++#define LTQ_ES_SW_GCTL1_REG_DIS (0x1 << 15) ++#define LTQ_ES_SW_GCTL1_REG_DIS_VAL(val) (((val) & 0x1) << 15) ++#define LTQ_ES_SW_GCTL1_REG_DIS_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_DIS) >> 15) & 0x1) ++#define LTQ_ES_SW_GCTL1_REG_DIS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_DIS) | (((val) & 0x1) << 15)) ++/* Unicast Portmap (14:12) */ ++#define LTQ_ES_SW_GCTL1_REG_UP (0x7 << 12) ++#define LTQ_ES_SW_GCTL1_REG_UP_VAL(val) (((val) & 0x7) << 12) ++#define LTQ_ES_SW_GCTL1_REG_UP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_UP) >> 12) & 0x7) ++#define LTQ_ES_SW_GCTL1_REG_UP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_UP) | (((val) & 0x7) << 12)) ++/* Broadcast Portmap (10:8) */ ++#define LTQ_ES_SW_GCTL1_REG_BP (0x7 << 8) ++#define LTQ_ES_SW_GCTL1_REG_BP_VAL(val) (((val) & 0x7) << 8) ++#define LTQ_ES_SW_GCTL1_REG_BP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_BP) >> 8) & 0x7) ++#define LTQ_ES_SW_GCTL1_REG_BP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_BP) | (((val) & 0x7) << 8)) ++/* Multicast Portmap (6:4) */ ++#define LTQ_ES_SW_GCTL1_REG_MP (0x7 << 4) ++#define LTQ_ES_SW_GCTL1_REG_MP_VAL(val) (((val) & 0x7) << 4) ++#define LTQ_ES_SW_GCTL1_REG_MP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_MP) >> 4) & 0x7) ++#define LTQ_ES_SW_GCTL1_REG_MP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_MP) | (((val) & 0x7) << 4)) ++/* Reserve Portmap (2:0) */ ++#define LTQ_ES_SW_GCTL1_REG_RP (0x7) ++#define LTQ_ES_SW_GCTL1_REG_RP_VAL(val) (((val) & 0x7) << 0) ++#define LTQ_ES_SW_GCTL1_REG_RP_GET(val) ((((val) & LTQ_ES_SW_GCTL1_REG_RP) >> 0) & 0x7) ++#define LTQ_ES_SW_GCTL1_REG_RP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_SW_GCTL1_REG_RP) | (((val) & 0x7) << 0)) ++ ++/******************************************************************************* ++ * ARP/RARP Register ++ ******************************************************************************/ ++ ++/* MAC Control Action (15:14) */ ++#define LTQ_ES_ARP_REG_MACA (0x3 << 14) ++#define LTQ_ES_ARP_REG_MACA_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_ARP_REG_MACA_GET(val) ((((val) & LTQ_ES_ARP_REG_MACA) >> 14) & 0x3) ++#define LTQ_ES_ARP_REG_MACA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_MACA) | (((val) & 0x3) << 14)) ++/* Unicast packet Treated as Cross_VLAN packet (13) */ ++#define LTQ_ES_ARP_REG_UPT (0x1 << 13) ++#define LTQ_ES_ARP_REG_UPT_VAL(val) (((val) & 0x1) << 13) ++#define LTQ_ES_ARP_REG_UPT_GET(val) ((((val) & LTQ_ES_ARP_REG_UPT) >> 13) & 0x1) ++#define LTQ_ES_ARP_REG_UPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_UPT) | (((val) & 0x1) << 13)) ++/* RARP Packet Treated as Cross_VLAN Packet (12) */ ++#define LTQ_ES_ARP_REG_RPT (0x1 << 12) ++#define LTQ_ES_ARP_REG_RPT_VAL(val) (((val) & 0x1) << 12) ++#define LTQ_ES_ARP_REG_RPT_GET(val) ((((val) & LTQ_ES_ARP_REG_RPT) >> 12) & 0x1) ++#define LTQ_ES_ARP_REG_RPT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RPT) | (((val) & 0x1) << 12)) ++/* RARP/ARP Packet Action (11:10) */ ++#define LTQ_ES_ARP_REG_RAPA (0x3 << 10) ++#define LTQ_ES_ARP_REG_RAPA_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_ARP_REG_RAPA_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPA) >> 10) & 0x3) ++#define LTQ_ES_ARP_REG_RAPA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPA) | (((val) & 0x3) << 10)) ++/* RARP/ARP Packet Priority Enable (9) */ ++#define LTQ_ES_ARP_REG_RAPPE (0x1 << 9) ++#define LTQ_ES_ARP_REG_RAPPE_VAL(val) (((val) & 0x1) << 9) ++#define LTQ_ES_ARP_REG_RAPPE_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPPE) >> 9) & 0x1) ++#define LTQ_ES_ARP_REG_RAPPE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPPE) | (((val) & 0x1) << 9)) ++/* RARP/ARP Packet Priority (8:7) */ ++#define LTQ_ES_ARP_REG_RAPP (0x3 << 7) ++#define LTQ_ES_ARP_REG_RAPP_VAL(val) (((val) & 0x3) << 7) ++#define LTQ_ES_ARP_REG_RAPP_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPP) >> 7) & 0x3) ++#define LTQ_ES_ARP_REG_RAPP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPP) | (((val) & 0x3) << 7)) ++/* RARP/ARP Packet Output Tag Handle (6:5) */ ++#define LTQ_ES_ARP_REG_RAPOTH (0x3 << 5) ++#define LTQ_ES_ARP_REG_RAPOTH_VAL(val) (((val) & 0x3) << 5) ++#define LTQ_ES_ARP_REG_RAPOTH_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPOTH) >> 5) & 0x3) ++#define LTQ_ES_ARP_REG_RAPOTH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPOTH) | (((val) & 0x3) << 5)) ++/* ARP Packet Treated as Cross _ VLAN Packet (4) */ ++#define LTQ_ES_ARP_REG_APT (0x1 << 4) ++#define LTQ_ES_ARP_REG_APT_VAL(val) (((val) & 0x1) << 4) ++#define LTQ_ES_ARP_REG_APT_GET(val) ((((val) & LTQ_ES_ARP_REG_APT) >> 4) & 0x1) ++#define LTQ_ES_ARP_REG_APT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_APT) | (((val) & 0x1) << 4)) ++/* RARP/ARP Packet Treated as Management Packet (3) */ ++#define LTQ_ES_ARP_REG_RAPTM (0x1 << 3) ++#define LTQ_ES_ARP_REG_RAPTM_VAL(val) (((val) & 0x1) << 3) ++#define LTQ_ES_ARP_REG_RAPTM_GET(val) ((((val) & LTQ_ES_ARP_REG_RAPTM) >> 3) & 0x1) ++#define LTQ_ES_ARP_REG_RAPTM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_RAPTM) | (((val) & 0x1) << 3)) ++/* RARP/ARP Packet Treated as Span Packet (2) */ ++#define LTQ_ES_ARP_REG_TAPTS (0x1 << 2) ++#define LTQ_ES_ARP_REG_TAPTS_VAL(val) (((val) & 0x1) << 2) ++#define LTQ_ES_ARP_REG_TAPTS_GET(val) ((((val) & LTQ_ES_ARP_REG_TAPTS) >> 2) & 0x1) ++#define LTQ_ES_ARP_REG_TAPTS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAPTS) | (((val) & 0x1) << 2)) ++/* Trap ARP Packet (1) */ ++#define LTQ_ES_ARP_REG_TAP (0x1 << 1) ++#define LTQ_ES_ARP_REG_TAP_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_ES_ARP_REG_TAP_GET(val) ((((val) & LTQ_ES_ARP_REG_TAP) >> 1) & 0x1) ++#define LTQ_ES_ARP_REG_TAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TAP) | (((val) & 0x1) << 1)) ++/* Trap RARP Packet (0) */ ++#define LTQ_ES_ARP_REG_TRP (0x1) ++#define LTQ_ES_ARP_REG_TRP_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_ES_ARP_REG_TRP_GET(val) ((((val) & LTQ_ES_ARP_REG_TRP) >> 0) & 0x1) ++#define LTQ_ES_ARP_REG_TRP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ARP_REG_TRP) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Storm control Register ++ ******************************************************************************/ ++ ++/* Reserved (31:29) */ ++#define LTQ_ES_STRM_CTL_REG_RES (0x7 << 29) ++#define LTQ_ES_STRM_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_RES) >> 29) & 0x7) ++/* 10M Threshold (28:16) */ ++#define LTQ_ES_STRM_CTL_REG_STORM_10_TH (0x1fff << 16) ++#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_VAL(val) (((val) & 0x1fff) << 16) ++#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_10_TH) >> 16) & 0x1fff) ++#define LTQ_ES_STRM_CTL_REG_STORM_10_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_10_TH) | (((val) & 0x1fff) << 16)) ++/* Storm Enable for Broadcast Packets (15) */ ++#define LTQ_ES_STRM_CTL_REG_STORM_B (0x1 << 15) ++#define LTQ_ES_STRM_CTL_REG_STORM_B_VAL(val) (((val) & 0x1) << 15) ++#define LTQ_ES_STRM_CTL_REG_STORM_B_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_B) >> 15) & 0x1) ++#define LTQ_ES_STRM_CTL_REG_STORM_B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_B) | (((val) & 0x1) << 15)) ++/* Storm Enable for Multicast Packets (14) */ ++#define LTQ_ES_STRM_CTL_REG_STORM_M (0x1 << 14) ++#define LTQ_ES_STRM_CTL_REG_STORM_M_VAL(val) (((val) & 0x1) << 14) ++#define LTQ_ES_STRM_CTL_REG_STORM_M_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_M) >> 14) & 0x1) ++#define LTQ_ES_STRM_CTL_REG_STORM_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_M) | (((val) & 0x1) << 14)) ++/* Storm Enable for Un-learned Unicast Packets (13) */ ++#define LTQ_ES_STRM_CTL_REG_STORM_U (0x1 << 13) ++#define LTQ_ES_STRM_CTL_REG_STORM_U_VAL(val) (((val) & 0x1) << 13) ++#define LTQ_ES_STRM_CTL_REG_STORM_U_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_U) >> 13) & 0x1) ++#define LTQ_ES_STRM_CTL_REG_STORM_U_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_U) | (((val) & 0x1) << 13)) ++/* 100M Threshold (12:0) */ ++#define LTQ_ES_STRM_CTL_REG_STORM_100_TH (0x1fff) ++#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_VAL(val) (((val) & 0x1fff) << 0) ++#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_GET(val) ((((val) & LTQ_ES_STRM_CTL_REG_STORM_100_TH) >> 0) & 0x1fff) ++#define LTQ_ES_STRM_CTL_REG_STORM_100_TH_SET(reg,val) (reg) = ((reg & ~LTQ_ES_STRM_CTL_REG_STORM_100_TH) | (((val) & 0x1fff) << 0)) ++ ++/******************************************************************************* ++ * RGMII/GMII Port Control Register ++ ******************************************************************************/ ++ ++/* Management Clock Select (31:24) */ ++#define LTQ_ES_RGMII_CTL_REG_MCS (0xff << 24) ++#define LTQ_ES_RGMII_CTL_REG_MCS_VAL(val) (((val) & 0xff) << 24) ++#define LTQ_ES_RGMII_CTL_REG_MCS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_MCS) >> 24) & 0xff) ++#define LTQ_ES_RGMII_CTL_REG_MCS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_MCS) | (((val) & 0xff) << 24)) ++/* Interface Selection (19:18) */ ++#define LTQ_ES_RGMII_CTL_REG_IS (0x3 << 18) ++#define LTQ_ES_RGMII_CTL_REG_IS_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_IS) >> 18) & 0x3) ++/* Port 1 RGMII Rx Clock Delay (17:16) */ ++#define LTQ_ES_RGMII_CTL_REG_P1RDLY (0x3 << 16) ++#define LTQ_ES_RGMII_CTL_REG_P1RDLY_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_RGMII_CTL_REG_P1RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1RDLY) >> 16) & 0x3) ++#define LTQ_ES_RGMII_CTL_REG_P1RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1RDLY) | (((val) & 0x3) << 16)) ++/* Port 1 RGMII Tx Clock Delay (15:14) */ ++#define LTQ_ES_RGMII_CTL_REG_P1TDLY (0x3 << 14) ++#define LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_RGMII_CTL_REG_P1TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1TDLY) >> 14) & 0x3) ++#define LTQ_ES_RGMII_CTL_REG_P1TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1TDLY) | (((val) & 0x3) << 14)) ++/* Port 1 Speed (13:12) */ ++#define LTQ_ES_RGMII_CTL_REG_P1SPD (0x3 << 12) ++#define LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_ES_RGMII_CTL_REG_P1SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1SPD) >> 12) & 0x3) ++#define LTQ_ES_RGMII_CTL_REG_P1SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1SPD) | (((val) & 0x3) << 12)) ++/* Port 1 Duplex mode (11) */ ++#define LTQ_ES_RGMII_CTL_REG_P1DUP (0x1 << 11) ++#define LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(val) (((val) & 0x1) << 11) ++#define LTQ_ES_RGMII_CTL_REG_P1DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1DUP) >> 11) & 0x1) ++#define LTQ_ES_RGMII_CTL_REG_P1DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1DUP) | (((val) & 0x1) << 11)) ++/* Port 1 Flow Control Enable (10) */ ++#define LTQ_ES_RGMII_CTL_REG_P1FCE (0x1 << 10) ++#define LTQ_ES_RGMII_CTL_REG_P1FCE_VAL(val) (((val) & 0x1) << 10) ++#define LTQ_ES_RGMII_CTL_REG_P1FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P1FCE) >> 10) & 0x1) ++#define LTQ_ES_RGMII_CTL_REG_P1FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P1FCE) | (((val) & 0x1) << 10)) ++/* Port 0 RGMII Rx Clock Delay (7:6) */ ++#define LTQ_ES_RGMII_CTL_REG_P0RDLY (0x3 << 6) ++#define LTQ_ES_RGMII_CTL_REG_P0RDLY_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_RGMII_CTL_REG_P0RDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0RDLY) >> 6) & 0x3) ++#define LTQ_ES_RGMII_CTL_REG_P0RDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0RDLY) | (((val) & 0x3) << 6)) ++/* Port 0 RGMII Tx Clock Delay (5:4) */ ++#define LTQ_ES_RGMII_CTL_REG_P0TDLY (0x3 << 4) ++#define LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_RGMII_CTL_REG_P0TDLY_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0TDLY) >> 4) & 0x3) ++#define LTQ_ES_RGMII_CTL_REG_P0TDLY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0TDLY) | (((val) & 0x3) << 4)) ++/* Port 0 Speed (3:2) */ ++#define LTQ_ES_RGMII_CTL_REG_P0SPD (0x3 << 2) ++#define LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_RGMII_CTL_REG_P0SPD_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0SPD) >> 2) & 0x3) ++#define LTQ_ES_RGMII_CTL_REG_P0SPD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0SPD) | (((val) & 0x3) << 2)) ++/* Port 0 Duplex mode (1) */ ++#define LTQ_ES_RGMII_CTL_REG_P0DUP (0x1 << 1) ++#define LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_ES_RGMII_CTL_REG_P0DUP_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0DUP) >> 1) & 0x1) ++#define LTQ_ES_RGMII_CTL_REG_P0DUP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0DUP) | (((val) & 0x1) << 1)) ++/* Port 0 Flow Control Enable (0) */ ++#define LTQ_ES_RGMII_CTL_REG_P0FCE (0x1) ++#define LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_ES_RGMII_CTL_REG_P0FCE_GET(val) ((((val) & LTQ_ES_RGMII_CTL_REG_P0FCE) >> 0) & 0x1) ++#define LTQ_ES_RGMII_CTL_REG_P0FCE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RGMII_CTL_REG_P0FCE) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * 802.1p Priority Map Register ++ ******************************************************************************/ ++ ++/* Priority Queue 7 (15:14) */ ++#define LTQ_ES_PRT_1P_REG_1PPQ7 (0x3 << 14) ++#define LTQ_ES_PRT_1P_REG_1PPQ7_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_PRT_1P_REG_1PPQ7_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ7) >> 14) & 0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ7) | (((val) & 0x3) << 14)) ++/* Priority Queue 6 (13:12) */ ++#define LTQ_ES_PRT_1P_REG_1PPQ6 (0x3 << 12) ++#define LTQ_ES_PRT_1P_REG_1PPQ6_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_ES_PRT_1P_REG_1PPQ6_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ6) >> 12) & 0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ6) | (((val) & 0x3) << 12)) ++/* Priority Queue 5 (11:10) */ ++#define LTQ_ES_PRT_1P_REG_1PPQ5 (0x3 << 10) ++#define LTQ_ES_PRT_1P_REG_1PPQ5_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_PRT_1P_REG_1PPQ5_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ5) >> 10) & 0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ5) | (((val) & 0x3) << 10)) ++/* Priority Queue 4 (9:8) */ ++#define LTQ_ES_PRT_1P_REG_1PPQ4 (0x3 << 8) ++#define LTQ_ES_PRT_1P_REG_1PPQ4_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_PRT_1P_REG_1PPQ4_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ4) >> 8) & 0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ4) | (((val) & 0x3) << 8)) ++/* Priority Queue 3 (7:6) */ ++#define LTQ_ES_PRT_1P_REG_1PPQ3 (0x3 << 6) ++#define LTQ_ES_PRT_1P_REG_1PPQ3_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_PRT_1P_REG_1PPQ3_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ3) >> 6) & 0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ3) | (((val) & 0x3) << 6)) ++/* Priority Queue 2 (5:4) */ ++#define LTQ_ES_PRT_1P_REG_1PPQ2 (0x3 << 4) ++#define LTQ_ES_PRT_1P_REG_1PPQ2_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_PRT_1P_REG_1PPQ2_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ2) >> 4) & 0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ2) | (((val) & 0x3) << 4)) ++/* Priority Queue 1 (3:2) */ ++#define LTQ_ES_PRT_1P_REG_1PPQ1 (0x3 << 2) ++#define LTQ_ES_PRT_1P_REG_1PPQ1_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_PRT_1P_REG_1PPQ1_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ1) >> 2) & 0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ1) | (((val) & 0x3) << 2)) ++/* Priority Queue 0 (1:0) */ ++#define LTQ_ES_PRT_1P_REG_1PPQ0 (0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ0_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_PRT_1P_REG_1PPQ0_GET(val) ((((val) & LTQ_ES_PRT_1P_REG_1PPQ0) >> 0) & 0x3) ++#define LTQ_ES_PRT_1P_REG_1PPQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRT_1P_REG_1PPQ0) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * Global Bucket Size Base counter ++ ******************************************************************************/ ++ ++/* Reserved (31:18) */ ++#define LTQ_ES_GBKT_SZBS_REG_REV (0x3fff << 18) ++#define LTQ_ES_GBKT_SZBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_REV) >> 18) & 0x3fff) ++/* Base[17:0] (17:0) */ ++#define LTQ_ES_GBKT_SZBS_REG_BASE17_0 (0x3ffff) ++#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_VAL(val) (((val) & 0x3ffff) << 0) ++#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZBS_REG_BASE17_0) >> 0) & 0x3ffff) ++#define LTQ_ES_GBKT_SZBS_REG_BASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZBS_REG_BASE17_0) | (((val) & 0x3ffff) << 0)) ++ ++/******************************************************************************* ++ * Global Bucket Size Extend Base Counter ++ ******************************************************************************/ ++ ++/* Reserved (31:18) */ ++#define LTQ_ES_GBKT_SZEBS_REG_REV (0x3fff << 18) ++#define LTQ_ES_GBKT_SZEBS_REG_REV_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_REV) >> 18) & 0x3fff) ++/* Extend Base[17:0] (17:0) */ ++#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0 (0x3ffff) ++#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_VAL(val) (((val) & 0x3ffff) << 0) ++#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_GET(val) ((((val) & LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) >> 0) & 0x3ffff) ++#define LTQ_ES_GBKT_SZEBS_REG_EBASE17_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_GBKT_SZEBS_REG_EBASE17_0) | (((val) & 0x3ffff) << 0)) ++ ++/******************************************************************************* ++ * Buffer Threshold Register ++ ******************************************************************************/ ++ ++/* Port Unfull Offset 3 (31:30) */ ++#define LTQ_ES_BF_TH_REG_PUO3 (0x3 << 30) ++#define LTQ_ES_BF_TH_REG_PUO3_VAL(val) (((val) & 0x3) << 30) ++#define LTQ_ES_BF_TH_REG_PUO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO3) >> 30) & 0x3) ++#define LTQ_ES_BF_TH_REG_PUO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO3) | (((val) & 0x3) << 30)) ++/* Port Unfull Offset 2 (29:28) */ ++#define LTQ_ES_BF_TH_REG_PUO2 (0x3 << 28) ++#define LTQ_ES_BF_TH_REG_PUO2_VAL(val) (((val) & 0x3) << 28) ++#define LTQ_ES_BF_TH_REG_PUO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO2) >> 28) & 0x3) ++#define LTQ_ES_BF_TH_REG_PUO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO2) | (((val) & 0x3) << 28)) ++/* Port Unfull Offset 1 (27:26) */ ++#define LTQ_ES_BF_TH_REG_PUO1 (0x3 << 26) ++#define LTQ_ES_BF_TH_REG_PUO1_VAL(val) (((val) & 0x3) << 26) ++#define LTQ_ES_BF_TH_REG_PUO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO1) >> 26) & 0x3) ++#define LTQ_ES_BF_TH_REG_PUO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO1) | (((val) & 0x3) << 26)) ++/* Port Unfull Offset 0 (25:24) */ ++#define LTQ_ES_BF_TH_REG_PUO0 (0x3 << 24) ++#define LTQ_ES_BF_TH_REG_PUO0_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_BF_TH_REG_PUO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUO0) >> 24) & 0x3) ++#define LTQ_ES_BF_TH_REG_PUO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUO0) | (((val) & 0x3) << 24)) ++/* Port Full Offset 3 (23:22) */ ++#define LTQ_ES_BF_TH_REG_PFO3 (0x3 << 22) ++#define LTQ_ES_BF_TH_REG_PFO3_VAL(val) (((val) & 0x3) << 22) ++#define LTQ_ES_BF_TH_REG_PFO3_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO3) >> 22) & 0x3) ++#define LTQ_ES_BF_TH_REG_PFO3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO3) | (((val) & 0x3) << 22)) ++/* Port Full Offset 2 (21:20) */ ++#define LTQ_ES_BF_TH_REG_PFO2 (0x3 << 20) ++#define LTQ_ES_BF_TH_REG_PFO2_VAL(val) (((val) & 0x3) << 20) ++#define LTQ_ES_BF_TH_REG_PFO2_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO2) >> 20) & 0x3) ++#define LTQ_ES_BF_TH_REG_PFO2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO2) | (((val) & 0x3) << 20)) ++/* Port Full Offset 1 (19:18) */ ++#define LTQ_ES_BF_TH_REG_PFO1 (0x3 << 18) ++#define LTQ_ES_BF_TH_REG_PFO1_VAL(val) (((val) & 0x3) << 18) ++#define LTQ_ES_BF_TH_REG_PFO1_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO1) >> 18) & 0x3) ++#define LTQ_ES_BF_TH_REG_PFO1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO1) | (((val) & 0x3) << 18)) ++/* Port Full Offset 0 (17:16) */ ++#define LTQ_ES_BF_TH_REG_PFO0 (0x3 << 16) ++#define LTQ_ES_BF_TH_REG_PFO0_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_BF_TH_REG_PFO0_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFO0) >> 16) & 0x3) ++#define LTQ_ES_BF_TH_REG_PFO0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFO0) | (((val) & 0x3) << 16)) ++/* Reserved (15:14) */ ++#define LTQ_ES_BF_TH_REG_RES (0x3 << 14) ++#define LTQ_ES_BF_TH_REG_RES_GET(val) ((((val) & LTQ_ES_BF_TH_REG_RES) >> 14) & 0x3) ++/* Total Low Add (13) */ ++#define LTQ_ES_BF_TH_REG_TLA (0x1 << 13) ++#define LTQ_ES_BF_TH_REG_TLA_VAL(val) (((val) & 0x1) << 13) ++#define LTQ_ES_BF_TH_REG_TLA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLA) >> 13) & 0x1) ++#define LTQ_ES_BF_TH_REG_TLA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLA) | (((val) & 0x1) << 13)) ++/* Total High Add (12) */ ++#define LTQ_ES_BF_TH_REG_THA (0x1 << 12) ++#define LTQ_ES_BF_TH_REG_THA_VAL(val) (((val) & 0x1) << 12) ++#define LTQ_ES_BF_TH_REG_THA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THA) >> 12) & 0x1) ++#define LTQ_ES_BF_TH_REG_THA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THA) | (((val) & 0x1) << 12)) ++/* Total Low Offset (11:10) */ ++#define LTQ_ES_BF_TH_REG_TLO (0x3 << 10) ++#define LTQ_ES_BF_TH_REG_TLO_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_BF_TH_REG_TLO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_TLO) >> 10) & 0x3) ++#define LTQ_ES_BF_TH_REG_TLO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_TLO) | (((val) & 0x3) << 10)) ++/* Total High Offset (9:8) */ ++#define LTQ_ES_BF_TH_REG_THO (0x3 << 8) ++#define LTQ_ES_BF_TH_REG_THO_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_BF_TH_REG_THO_GET(val) ((((val) & LTQ_ES_BF_TH_REG_THO) >> 8) & 0x3) ++#define LTQ_ES_BF_TH_REG_THO_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_THO) | (((val) & 0x3) << 8)) ++/* Port Unfull Add (7:4) */ ++#define LTQ_ES_BF_TH_REG_PUA (0xf << 4) ++#define LTQ_ES_BF_TH_REG_PUA_VAL(val) (((val) & 0xf) << 4) ++#define LTQ_ES_BF_TH_REG_PUA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PUA) >> 4) & 0xf) ++#define LTQ_ES_BF_TH_REG_PUA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PUA) | (((val) & 0xf) << 4)) ++/* Port Full Add (3:0) */ ++#define LTQ_ES_BF_TH_REG_PFA (0xf) ++#define LTQ_ES_BF_TH_REG_PFA_VAL(val) (((val) & 0xf) << 0) ++#define LTQ_ES_BF_TH_REG_PFA_GET(val) ((((val) & LTQ_ES_BF_TH_REG_PFA) >> 0) & 0xf) ++#define LTQ_ES_BF_TH_REG_PFA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_BF_TH_REG_PFA) | (((val) & 0xf) << 0)) ++ ++/******************************************************************************* ++ * PMAC Header Control Register ++ ******************************************************************************/ ++ ++/* Reserved (31:22) */ ++#define LTQ_ES_PMAC_HD_CTL_RES (0x3ff << 22) ++#define LTQ_ES_PMAC_HD_CTL_RES_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RES) >> 22) & 0x3ff) ++/* Remove Layer-2 Header from Packets Going from PMAC to DMA (21) */ ++#define LTQ_ES_PMAC_HD_CTL_RL2 (0x1 << 21) ++#define LTQ_ES_PMAC_HD_CTL_RL2_VAL(val) (((val) & 0x1) << 21) ++#define LTQ_ES_PMAC_HD_CTL_RL2_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RL2) >> 21) & 0x1) ++#define LTQ_ES_PMAC_HD_CTL_RL2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RL2) | (((val) & 0x1) << 21)) ++/* Remove CRC from Packets Going from PMAC to DMA (20) */ ++#define LTQ_ES_PMAC_HD_CTL_RC (0x1 << 20) ++#define LTQ_ES_PMAC_HD_CTL_RC_VAL(val) (((val) & 0x1) << 20) ++#define LTQ_ES_PMAC_HD_CTL_RC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_RC) >> 20) & 0x1) ++#define LTQ_ES_PMAC_HD_CTL_RC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_RC) | (((val) & 0x1) << 20)) ++/* Status Header for Packets from PMAC to DMA (19) */ ++#define LTQ_ES_PMAC_HD_CTL_AS (0x1 << 19) ++#define LTQ_ES_PMAC_HD_CTL_AS_VAL(val) (((val) & 0x1) << 19) ++#define LTQ_ES_PMAC_HD_CTL_AS_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AS) >> 19) & 0x1) ++#define LTQ_ES_PMAC_HD_CTL_AS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AS) | (((val) & 0x1) << 19)) ++/* Add CRC for packets from DMA to PMAC (18) */ ++#define LTQ_ES_PMAC_HD_CTL_AC (0x1 << 18) ++#define LTQ_ES_PMAC_HD_CTL_AC_VAL(val) (((val) & 0x1) << 18) ++#define LTQ_ES_PMAC_HD_CTL_AC_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_AC) >> 18) & 0x1) ++#define LTQ_ES_PMAC_HD_CTL_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_AC) | (((val) & 0x1) << 18)) ++/* Contains the length/type value to the added to packets from DMA to PMAC (17:2) */ ++#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN (0xffff << 2) ++#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_VAL(val) (((val) & 0xffff) << 2) ++#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TYPE_LEN) >> 2) & 0xffff) ++#define LTQ_ES_PMAC_HD_CTL_TYPE_LEN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TYPE_LEN) | (((val) & 0xffff) << 2)) ++/* Add TAG to Packets from DMA to PMAC (1) */ ++#define LTQ_ES_PMAC_HD_CTL_TAG (0x1 << 1) ++#define LTQ_ES_PMAC_HD_CTL_TAG_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_ES_PMAC_HD_CTL_TAG_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_TAG) >> 1) & 0x1) ++#define LTQ_ES_PMAC_HD_CTL_TAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_TAG) | (((val) & 0x1) << 1)) ++/* ADD Header to Packets from DMA to PMAC (0) */ ++#define LTQ_ES_PMAC_HD_CTL_ADD (0x1) ++#define LTQ_ES_PMAC_HD_CTL_ADD_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_ES_PMAC_HD_CTL_ADD_GET(val) ((((val) & LTQ_ES_PMAC_HD_CTL_ADD) >> 0) & 0x1) ++#define LTQ_ES_PMAC_HD_CTL_ADD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_HD_CTL_ADD) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * PMAC Source Address Register 1 ++ ******************************************************************************/ ++ ++/* Source Address to be inserted as a part of the Ethernet header. (15:0) */ ++#define LTQ_ES_PMAC_SA1_SA_47_32 (0xffff) ++#define LTQ_ES_PMAC_SA1_SA_47_32_VAL(val) (((val) & 0xffff) << 0) ++#define LTQ_ES_PMAC_SA1_SA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_SA1_SA_47_32) >> 0) & 0xffff) ++#define LTQ_ES_PMAC_SA1_SA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA1_SA_47_32) | (((val) & 0xffff) << 0)) ++ ++/******************************************************************************* ++ * PMAC Source Address Register 2 ++ ******************************************************************************/ ++ ++/* Source Address (31:0) */ ++#define LTQ_ES_PMAC_SA2_SA_31_0 (0xFFFFFFFFL) ++#define LTQ_ES_PMAC_SA2_SA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) ++#define LTQ_ES_PMAC_SA2_SA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_SA2_SA_31_0) >> 0) & 0xFFFFFFFFL) ++#define LTQ_ES_PMAC_SA2_SA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_SA2_SA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) ++ ++/******************************************************************************* ++ * PMAC Destination Address Register 1 ++ ******************************************************************************/ ++ ++/* Destination Address (15:0) */ ++#define LTQ_ES_PMAC_DA1_DA_47_32 (0xffff) ++#define LTQ_ES_PMAC_DA1_DA_47_32_VAL(val) (((val) & 0xffff) << 0) ++#define LTQ_ES_PMAC_DA1_DA_47_32_GET(val) ((((val) & LTQ_ES_PMAC_DA1_DA_47_32) >> 0) & 0xffff) ++#define LTQ_ES_PMAC_DA1_DA_47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA1_DA_47_32) | (((val) & 0xffff) << 0)) ++ ++/******************************************************************************* ++ * PMAC Destination Address Register 2 ++ ******************************************************************************/ ++ ++/* Destination Address to be inserted as a part of the Ethernet header. (31:0) */ ++#define LTQ_ES_PMAC_DA2_DA_31_0 (0xFFFFFFFFL) ++#define LTQ_ES_PMAC_DA2_DA_31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) ++#define LTQ_ES_PMAC_DA2_DA_31_0_GET(val) ((((val) & LTQ_ES_PMAC_DA2_DA_31_0) >> 0) & 0xFFFFFFFFL) ++#define LTQ_ES_PMAC_DA2_DA_31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_DA2_DA_31_0) | (((val) & 0xFFFFFFFFL) << 0)) ++ ++/******************************************************************************* ++ * PMAC VLAN Register ++ ******************************************************************************/ ++ ++/* Priority to be inserted as a part of VLAN tag (15:13) */ ++#define LTQ_ES_PMAC_VLAN_PRI (0x7 << 13) ++#define LTQ_ES_PMAC_VLAN_PRI_VAL(val) (((val) & 0x7) << 13) ++#define LTQ_ES_PMAC_VLAN_PRI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_PRI) >> 13) & 0x7) ++#define LTQ_ES_PMAC_VLAN_PRI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_PRI) | (((val) & 0x7) << 13)) ++/* CFI bit to be inserted as a part of VLAN tag (12) */ ++#define LTQ_ES_PMAC_VLAN_CFI (0x1 << 12) ++#define LTQ_ES_PMAC_VLAN_CFI_VAL(val) (((val) & 0x1) << 12) ++#define LTQ_ES_PMAC_VLAN_CFI_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_CFI) >> 12) & 0x1) ++#define LTQ_ES_PMAC_VLAN_CFI_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_CFI) | (((val) & 0x1) << 12)) ++/* VLAN ID to be inserted as a part of VLAN tag (11:0) */ ++#define LTQ_ES_PMAC_VLAN_VLAN_ID (0xfff) ++#define LTQ_ES_PMAC_VLAN_VLAN_ID_VAL(val) (((val) & 0xfff) << 0) ++#define LTQ_ES_PMAC_VLAN_VLAN_ID_GET(val) ((((val) & LTQ_ES_PMAC_VLAN_VLAN_ID) >> 0) & 0xfff) ++#define LTQ_ES_PMAC_VLAN_VLAN_ID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_VLAN_VLAN ID) | (((val) & 0xfff) << 0)) ++ ++/******************************************************************************* ++ * PMAC TX IPG Counter Register ++ ******************************************************************************/ ++ ++/* IPG Counter (7:0) */ ++#define LTQ_ES_PMAC_TX_IPG_IPG_CNT (0xff) ++#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) ++#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_TX_IPG_IPG_CNT) >> 0) & 0xff) ++#define LTQ_ES_PMAC_TX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_TX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) ++ ++/******************************************************************************* ++ * PMAC RX IPG Counter Register ++ ******************************************************************************/ ++ ++/* IPG Counter (7:0) */ ++#define LTQ_ES_PMAC_RX_IPG_IPG_CNT (0xff) ++#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_VAL(val) (((val) & 0xff) << 0) ++#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_GET(val) ((((val) & LTQ_ES_PMAC_RX_IPG_IPG_CNT) >> 0) & 0xff) ++#define LTQ_ES_PMAC_RX_IPG_IPG_CNT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PMAC_RX_IPG_IPG_CNT) | (((val) & 0xff) << 0)) ++ ++/******************************************************************************* ++ * Address Table Control 0 Register ++ ******************************************************************************/ ++ ++/* Address [31:0] (31:0) */ ++#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0 (0xFFFFFFFFL) ++#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_VAL(val) (((val) & 0xFFFFFFFFL) << 0) ++#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) >> 0) & 0xFFFFFFFFL) ++#define LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL0_REG_ADDR31_0) | (((val) & 0xFFFFFFFFL) << 0)) ++ ++/******************************************************************************* ++ * Address Table Control 1 Register ++ ******************************************************************************/ ++ ++/* Port Map (22:20) */ ++#define LTQ_ES_ADR_TB_CTL1_REG_PMAP (0x7 << 20) ++#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(val) (((val) & 0x7) << 20) ++#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_PMAP) >> 20) & 0x7) ++#define LTQ_ES_ADR_TB_CTL1_REG_PMAP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_PMAP) | (((val) & 0x7) << 20)) ++/* FID group (17:16) */ ++#define LTQ_ES_ADR_TB_CTL1_REG_FID (0x3 << 16) ++#define LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_ADR_TB_CTL1_REG_FID_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_FID) >> 16) & 0x3) ++#define LTQ_ES_ADR_TB_CTL1_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_FID) | (((val) & 0x3) << 16)) ++/* Address [47:32] (15:0) */ ++#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32 (0xffff) ++#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_VAL(val) (((val) & 0xffff) << 0) ++#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) >> 0) & 0xffff) ++#define LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL1_REG_ADDR47_32) | (((val) & 0xffff) << 0)) ++ ++/******************************************************************************* ++ * Address Table Control 2 Register ++ ******************************************************************************/ ++ ++/* Command (22:20) */ ++#define LTQ_ES_ADR_TB_CTL2_REG_CMD (0x7 << 20) ++#define LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(val) (((val) & 0x7) << 20) ++#define LTQ_ES_ADR_TB_CTL2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_CMD) >> 20) & 0x7) ++#define LTQ_ES_ADR_TB_CTL2_REG_CMD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_CMD) | (((val) & 0x7) << 20)) ++/* Access Control (19:16) */ ++#define LTQ_ES_ADR_TB_CTL2_REG_AC (0xf << 16) ++#define LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(val) (((val) & 0xf) << 16) ++#define LTQ_ES_ADR_TB_CTL2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_AC) >> 16) & 0xf) ++#define LTQ_ES_ADR_TB_CTL2_REG_AC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_AC) | (((val) & 0xf) << 16)) ++/* Info Type: Static address (12) */ ++#define LTQ_ES_ADR_TB_CTL2_REG_INFOT (0x1 << 12) ++#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_VAL(val) (((val) & 0x1) << 12) ++#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_INFOT) >> 12) & 0x1) ++#define LTQ_ES_ADR_TB_CTL2_REG_INFOT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_INFOT) | (((val) & 0x1) << 12)) ++/* Info_Ctrl/Age Timer (10:0) */ ++#define LTQ_ES_ADR_TB_CTL2_REG_ITAT (0x7ff) ++#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_VAL(val) (((val) & 0x7ff) << 0) ++#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_GET(val) ((((val) & LTQ_ES_ADR_TB_CTL2_REG_ITAT) >> 0) & 0x7ff) ++#define LTQ_ES_ADR_TB_CTL2_REG_ITAT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_ADR_TB_CTL2_REG_ITAT) | (((val) & 0x7ff) << 0)) ++ ++/******************************************************************************* ++ * Address Table Status 0 Register ++ ******************************************************************************/ ++ ++/* Address [31:0] (31:0) */ ++#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0 (0xFFFFFFFFL) ++#define LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0_GET(val) ((((val) & LTQ_ES_ADR_TB_ST0_REG_ADDRS31_0) >> 0) & 0xFFFFFFFFL) ++ ++/******************************************************************************* ++ * Address Table Status 1 Register ++ ******************************************************************************/ ++ ++/* Port Map (22:20) */ ++#define LTQ_ES_ADR_TB_ST1_REG_PMAPS (0x7 << 20) ++#define LTQ_ES_ADR_TB_ST1_REG_PMAPS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_PMAPS) >> 20) & 0x7) ++/* FID group (17:16) */ ++#define LTQ_ES_ADR_TB_ST1_REG_FIDS (0x3 << 16) ++#define LTQ_ES_ADR_TB_ST1_REG_FIDS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_FIDS) >> 16) & 0x3) ++/* Address [47:32] (15:0) */ ++#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32 (0xffff) ++#define LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32_GET(val) ((((val) & LTQ_ES_ADR_TB_ST1_REG_ADDRS47_32) >> 0) & 0xffff) ++ ++/******************************************************************************* ++ * Address Table Status 2 Register ++ ******************************************************************************/ ++ ++/* Busy (31) */ ++#define LTQ_ES_ADR_TB_ST2_REG_BUSY (0x1 << 31) ++#define LTQ_ES_ADR_TB_ST2_REG_BUSY_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BUSY) >> 31) & 0x1) ++/* Result (30:28) */ ++#define LTQ_ES_ADR_TB_ST2_REG_RSLT (0x7 << 28) ++#define LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_RSLT) >> 28) & 0x7) ++/* Command (22:20) */ ++#define LTQ_ES_ADR_TB_ST2_REG_CMD (0x7 << 20) ++#define LTQ_ES_ADR_TB_ST2_REG_CMD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_CMD) >> 20) & 0x7) ++/* Access Control (19:16) */ ++#define LTQ_ES_ADR_TB_ST2_REG_AC (0xf << 16) ++#define LTQ_ES_ADR_TB_ST2_REG_AC_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_AC) >> 16) & 0xf) ++/* Bad Status (14) */ ++#define LTQ_ES_ADR_TB_ST2_REG_BAD (0x1 << 14) ++#define LTQ_ES_ADR_TB_ST2_REG_BAD_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_BAD) >> 14) & 0x1) ++/* Occupy (13) */ ++#define LTQ_ES_ADR_TB_ST2_REG_OCP (0x1 << 13) ++#define LTQ_ES_ADR_TB_ST2_REG_OCP_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_OCP) >> 13) & 0x1) ++/* Info Type: Static address (12) */ ++#define LTQ_ES_ADR_TB_ST2_REG_INFOTS (0x1 << 12) ++#define LTQ_ES_ADR_TB_ST2_REG_INFOTS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_INFOTS) >> 12) & 0x1) ++/* Info_Ctrl/Age Timer Status (10:0) */ ++#define LTQ_ES_ADR_TB_ST2_REG_ITATS (0x7ff) ++#define LTQ_ES_ADR_TB_ST2_REG_ITATS_GET(val) ((((val) & LTQ_ES_ADR_TB_ST2_REG_ITATS) >> 0) & 0x7ff) ++ ++/******************************************************************************* ++ * RMON Counter Control Register ++ ******************************************************************************/ ++ ++/* Reserved (31:12) */ ++#define LTQ_ES_RMON_CTL_REG_RES (0xfffff << 12) ++#define LTQ_ES_RMON_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_RES) >> 12) & 0xfffff) ++/* Busy/Access Start (11) */ ++#define LTQ_ES_RMON_CTL_REG_BAS (0x1 << 11) ++#define LTQ_ES_RMON_CTL_REG_BAS_VAL(val) (((val) & 0x1) << 11) ++#define LTQ_ES_RMON_CTL_REG_BAS_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_BAS) >> 11) & 0x1) ++#define LTQ_ES_RMON_CTL_REG_BAS_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_BAS) | (((val) & 0x1) << 11)) ++/* Command for access counter (10:9) */ ++#define LTQ_ES_RMON_CTL_REG_CAC (0x3 << 9) ++#define LTQ_ES_RMON_CTL_REG_CAC_VAL(val) (((val) & 0x3) << 9) ++#define LTQ_ES_RMON_CTL_REG_CAC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_CAC) >> 9) & 0x3) ++#define LTQ_ES_RMON_CTL_REG_CAC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_CAC) | (((val) & 0x3) << 9)) ++/* Port (8:6) */ ++#define LTQ_ES_RMON_CTL_REG_PORTC (0x7 << 6) ++#define LTQ_ES_RMON_CTL_REG_PORTC_VAL(val) (((val) & 0x7) << 6) ++#define LTQ_ES_RMON_CTL_REG_PORTC_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_PORTC) >> 6) & 0x7) ++#define LTQ_ES_RMON_CTL_REG_PORTC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_PORTC) | (((val) & 0x7) << 6)) ++/* Counter Offset (5:0) */ ++#define LTQ_ES_RMON_CTL_REG_OFFSET (0x3f) ++#define LTQ_ES_RMON_CTL_REG_OFFSET_VAL(val) (((val) & 0x3f) << 0) ++#define LTQ_ES_RMON_CTL_REG_OFFSET_GET(val) ((((val) & LTQ_ES_RMON_CTL_REG_OFFSET) >> 0) & 0x3f) ++#define LTQ_ES_RMON_CTL_REG_OFFSET_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RMON_CTL_REG_OFFSET) | (((val) & 0x3f) << 0)) ++ ++/******************************************************************************* ++ * RMON Counter Status Register ++ ******************************************************************************/ ++ ++/* Counter [31:0] or Counter[63:32] for byte count (31:0) */ ++#define LTQ_ES_RMON_ST_REG_COUNTER (0xFFFFFFFFL) ++#define LTQ_ES_RMON_ST_REG_COUNTER_GET(val) ((((val) & LTQ_ES_RMON_ST_REG_COUNTER) >> 0) & 0xFFFFFFFFL) ++ ++/******************************************************************************* ++ * MDIO Indirect Access Control ++ ******************************************************************************/ ++ ++/* The Write Data to the MDIO register (31:16) */ ++#define LTQ_ES_MDIO_CTL_REG_WD (0xffff << 16) ++#define LTQ_ES_MDIO_CTL_REG_WD_VAL(val) (((val) & 0xffff) << 16) ++#define LTQ_ES_MDIO_CTL_REG_WD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_WD) >> 16) & 0xffff) ++#define LTQ_ES_MDIO_CTL_REG_WD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_WD) | (((val) & 0xffff) << 16)) ++/* Busy state (15) */ ++#define LTQ_ES_MDIO_CTL_REG_MBUSY (0x1 << 15) ++#define LTQ_ES_MDIO_CTL_REG_MBUSY_VAL(val) (((val) & 0x1) << 15) ++#define LTQ_ES_MDIO_CTL_REG_MBUSY_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_MBUSY) >> 15) & 0x1) ++#define LTQ_ES_MDIO_CTL_REG_MBUSY_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_MBUSY) | (((val) & 0x1) << 15)) ++/* Reserved (14:12) */ ++#define LTQ_ES_MDIO_CTL_REG_RES (0x7 << 12) ++#define LTQ_ES_MDIO_CTL_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_RES) >> 12) & 0x7) ++/* Operation Code (11:10) */ ++#define LTQ_ES_MDIO_CTL_REG_OP (0x3 << 10) ++#define LTQ_ES_MDIO_CTL_REG_OP_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_MDIO_CTL_REG_OP_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_OP) >> 10) & 0x3) ++#define LTQ_ES_MDIO_CTL_REG_OP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_OP) | (((val) & 0x3) << 10)) ++/* PHY Address (9:5) */ ++#define LTQ_ES_MDIO_CTL_REG_PHYAD (0x1f << 5) ++#define LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(val) (((val) & 0x1f) << 5) ++#define LTQ_ES_MDIO_CTL_REG_PHYAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_PHYAD) >> 5) & 0x1f) ++#define LTQ_ES_MDIO_CTL_REG_PHYAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_PHYAD) | (((val) & 0x1f) << 5)) ++/* Register Address (4:0) */ ++#define LTQ_ES_MDIO_CTL_REG_REGAD (0x1f) ++#define LTQ_ES_MDIO_CTL_REG_REGAD_VAL(val) (((val) & 0x1f) << 0) ++#define LTQ_ES_MDIO_CTL_REG_REGAD_GET(val) ((((val) & LTQ_ES_MDIO_CTL_REG_REGAD) >> 0) & 0x1f) ++#define LTQ_ES_MDIO_CTL_REG_REGAD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_MDIO_CTL_REG_REGAD) | (((val) & 0x1f) << 0)) ++ ++/******************************************************************************* ++ * MDIO Indirect Read Data ++ ******************************************************************************/ ++ ++/* Reserved (31:16) */ ++#define LTQ_ES_MDIO_DATA_REG_RES (0xffff << 16) ++#define LTQ_ES_MDIO_DATA_REG_RES_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RES) >> 16) & 0xffff) ++/* The Read Data (15:0) */ ++#define LTQ_ES_MDIO_DATA_REG_RD (0xffff) ++#define LTQ_ES_MDIO_DATA_REG_RD_GET(val) ((((val) & LTQ_ES_MDIO_DATA_REG_RD) >> 0) & 0xffff) ++ ++/******************************************************************************* ++ * Type Filter Action ++ ******************************************************************************/ ++ ++/* Destination Queue for Type Filter 7 (31:30) */ ++#define LTQ_ES_TP_FLT_ACT_REG_QATF7 (0x3 << 30) ++#define LTQ_ES_TP_FLT_ACT_REG_QATF7_VAL(val) (((val) & 0x3) << 30) ++#define LTQ_ES_TP_FLT_ACT_REG_QATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF7) >> 30) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_QATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF7) | (((val) & 0x3) << 30)) ++/* Destination Queue for Type Filter 6 (29:28) */ ++#define LTQ_ES_TP_FLT_ACT_REG_QATF6 (0x3 << 28) ++#define LTQ_ES_TP_FLT_ACT_REG_QATF6_VAL(val) (((val) & 0x3) << 28) ++#define LTQ_ES_TP_FLT_ACT_REG_QATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QATF6) >> 28) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_QATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QATF6) | (((val) & 0x3) << 28)) ++/* Destination Queue for Type Filter 5 (27:26) */ ++#define LTQ_ES_TP_FLT_ACT_REG_QTF5 (0x3 << 26) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF5_VAL(val) (((val) & 0x3) << 26) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF5) >> 26) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF5) | (((val) & 0x3) << 26)) ++/* Destination Queue for Type Filter 4 (25:24) */ ++#define LTQ_ES_TP_FLT_ACT_REG_QTF4 (0x3 << 24) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF4_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF4) >> 24) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF4) | (((val) & 0x3) << 24)) ++/* Destination Queue for Type Filter 3 (23:22) */ ++#define LTQ_ES_TP_FLT_ACT_REG_QTF3 (0x3 << 22) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF3_VAL(val) (((val) & 0x3) << 22) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF3) >> 22) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF3) | (((val) & 0x3) << 22)) ++/* Destination Queue for Type Filter 2 (21:20) */ ++#define LTQ_ES_TP_FLT_ACT_REG_QTF2 (0x3 << 20) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF2_VAL(val) (((val) & 0x3) << 20) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF2) >> 20) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF2) | (((val) & 0x3) << 20)) ++/* Destination Queue for Type Filter 1 (19:18) */ ++#define LTQ_ES_TP_FLT_ACT_REG_QTF1 (0x3 << 18) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF1_VAL(val) (((val) & 0x3) << 18) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF1) >> 18) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF1) | (((val) & 0x3) << 18)) ++/* Destination Queue for Type Filter 0 (17:16) */ ++#define LTQ_ES_TP_FLT_ACT_REG_QTF0 (0x3 << 16) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF0_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_QTF0) >> 16) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_QTF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_QTF0) | (((val) & 0x3) << 16)) ++/* Action for Type Filter 7 (15:14) */ ++#define LTQ_ES_TP_FLT_ACT_REG_ATF7 (0x3 << 14) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF7_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF7_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF7) >> 14) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF7) | (((val) & 0x3) << 14)) ++/* Action for Type Filter 6 (13:12) */ ++#define LTQ_ES_TP_FLT_ACT_REG_ATF6 (0x3 << 12) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF6_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF6_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF6) >> 12) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF6) | (((val) & 0x3) << 12)) ++/* Action for Type Filter 5 (11:10) */ ++#define LTQ_ES_TP_FLT_ACT_REG_ATF5 (0x3 << 10) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF5_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF5_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF5) >> 10) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF5) | (((val) & 0x3) << 10)) ++/* Action for Type Filter 4 (9:8) */ ++#define LTQ_ES_TP_FLT_ACT_REG_ATF4 (0x3 << 8) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF4_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF4_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF4) >> 8) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF4) | (((val) & 0x3) << 8)) ++/* Action for Type Filter 3 (7:6) */ ++#define LTQ_ES_TP_FLT_ACT_REG_ATF3 (0x3 << 6) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF3_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF3_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF3) >> 6) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF3) | (((val) & 0x3) << 6)) ++/* Action for Type Filter 2 (5:4) */ ++#define LTQ_ES_TP_FLT_ACT_REG_ATF2 (0x3 << 4) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF2_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF2_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF2) >> 4) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF2) | (((val) & 0x3) << 4)) ++/* Action for Type Filter 1 (3:2) */ ++#define LTQ_ES_TP_FLT_ACT_REG_ATF1 (0x3 << 2) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF1_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF1_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF1) >> 2) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF1) | (((val) & 0x3) << 2)) ++/* Action for Type Filter 0 (1:0) */ ++#define LTQ_ES_TP_FLT_ACT_REG_ATF0 (0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF0_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF0_GET(val) ((((val) & LTQ_ES_TP_FLT_ACT_REG_ATF0) >> 0) & 0x3) ++#define LTQ_ES_TP_FLT_ACT_REG_ATF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT_ACT_REG_ATF0) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * Protocol Filter Action ++ ******************************************************************************/ ++ ++/* Action for Protocol Filter 7 (15:14) */ ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7 (0x3 << 14) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF7) >> 14) & 0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF7) | (((val) & 0x3) << 14)) ++/* Action for Protocol Filter 6 (13:12) */ ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6 (0x3 << 12) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF6) >> 12) & 0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF6) | (((val) & 0x3) << 12)) ++/* Action for Protocol Filter 5 (11:10) */ ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5 (0x3 << 10) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF5) >> 10) & 0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF5) | (((val) & 0x3) << 10)) ++/* Action for Protocol Filter 4 (9:8) */ ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4 (0x3 << 8) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF4) >> 8) & 0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF4) | (((val) & 0x3) << 8)) ++/* Action for Protocol Filter 3 (7:6) */ ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3 (0x3 << 6) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF3) >> 6) & 0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF3) | (((val) & 0x3) << 6)) ++/* Action for Protocol Filter 2 (5:4) */ ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2 (0x3 << 4) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF2) >> 4) & 0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF2) | (((val) & 0x3) << 4)) ++/* Action for Protocol Filter 1 (3:2) */ ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1 (0x3 << 2) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF1) >> 2) & 0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF1) | (((val) & 0x3) << 2)) ++/* Action for Protocol Filter 0 (1:0) */ ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0 (0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_GET(val) ((((val) & LTQ_ES_PRTCL_FLT_ACT_REG_APF0) >> 0) & 0x3) ++#define LTQ_ES_PRTCL_FLT_ACT_REG_APF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_FLT_ACT_REG_APF0) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * VLAN Filter 0 ++ ******************************************************************************/ ++ ++/* Res (31:24) */ ++#define LTQ_ES_VLAN_FLT0_REG_RES (0xff << 24) ++#define LTQ_ES_VLAN_FLT0_REG_RES_VAL(val) (((val) & 0xff) << 24) ++#define LTQ_ES_VLAN_FLT0_REG_RES_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_RES) >> 24) & 0xff) ++#define LTQ_ES_VLAN_FLT0_REG_RES_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_RES) | (((val) & 0xff) << 24)) ++/* FID (23:22) */ ++#define LTQ_ES_VLAN_FLT0_REG_FID (0x3 << 22) ++#define LTQ_ES_VLAN_FLT0_REG_FID_VAL(val) (((val) & 0x3) << 22) ++#define LTQ_ES_VLAN_FLT0_REG_FID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_FID) >> 22) & 0x3) ++#define LTQ_ES_VLAN_FLT0_REG_FID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_FID) | (((val) & 0x3) << 22)) ++/* Tagged Member (21:19) */ ++#define LTQ_ES_VLAN_FLT0_REG_TM (0x7 << 19) ++#define LTQ_ES_VLAN_FLT0_REG_TM_VAL(val) (((val) & 0x7) << 19) ++#define LTQ_ES_VLAN_FLT0_REG_TM_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_TM) >> 19) & 0x7) ++#define LTQ_ES_VLAN_FLT0_REG_TM_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_TM) | (((val) & 0x7) << 19)) ++/* Member (18:16) */ ++#define LTQ_ES_VLAN_FLT0_REG_M (0x7 << 16) ++#define LTQ_ES_VLAN_FLT0_REG_M_VAL(val) (((val) & 0x7) << 16) ++#define LTQ_ES_VLAN_FLT0_REG_M_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_M) >> 16) & 0x7) ++#define LTQ_ES_VLAN_FLT0_REG_M_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_M) | (((val) & 0x7) << 16)) ++/* VLAN_Valid (15) */ ++#define LTQ_ES_VLAN_FLT0_REG_VV (0x1 << 15) ++#define LTQ_ES_VLAN_FLT0_REG_VV_VAL(val) (((val) & 0x1) << 15) ++#define LTQ_ES_VLAN_FLT0_REG_VV_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VV) >> 15) & 0x1) ++#define LTQ_ES_VLAN_FLT0_REG_VV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VV) | (((val) & 0x1) << 15)) ++/* VLAN PRI (14:12) */ ++#define LTQ_ES_VLAN_FLT0_REG_VP (0x7 << 12) ++#define LTQ_ES_VLAN_FLT0_REG_VP_VAL(val) (((val) & 0x7) << 12) ++#define LTQ_ES_VLAN_FLT0_REG_VP_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VP) >> 12) & 0x7) ++#define LTQ_ES_VLAN_FLT0_REG_VP_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VP) | (((val) & 0x7) << 12)) ++/* VID (11:0) */ ++#define LTQ_ES_VLAN_FLT0_REG_VID (0xfff) ++#define LTQ_ES_VLAN_FLT0_REG_VID_VAL(val) (((val) & 0xfff) << 0) ++#define LTQ_ES_VLAN_FLT0_REG_VID_GET(val) ((((val) & LTQ_ES_VLAN_FLT0_REG_VID) >> 0) & 0xfff) ++#define LTQ_ES_VLAN_FLT0_REG_VID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_VLAN_FLT0_REG_VID) | (((val) & 0xfff) << 0)) ++ ++/******************************************************************************* ++ * Type Filter 10 ++ ******************************************************************************/ ++ ++/* Value 1 Compared with Ether-Type (31:16) */ ++#define LTQ_ES_TP_FLT10_REG_VCET1 (0xffff << 16) ++#define LTQ_ES_TP_FLT10_REG_VCET1_VAL(val) (((val) & 0xffff) << 16) ++#define LTQ_ES_TP_FLT10_REG_VCET1_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET1) >> 16) & 0xffff) ++#define LTQ_ES_TP_FLT10_REG_VCET1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET1) | (((val) & 0xffff) << 16)) ++/* Value 0 Compared with Ether-Type (15:0) */ ++#define LTQ_ES_TP_FLT10_REG_VCET0 (0xffff) ++#define LTQ_ES_TP_FLT10_REG_VCET0_VAL(val) (((val) & 0xffff) << 0) ++#define LTQ_ES_TP_FLT10_REG_VCET0_GET(val) ((((val) & LTQ_ES_TP_FLT10_REG_VCET0) >> 0) & 0xffff) ++#define LTQ_ES_TP_FLT10_REG_VCET0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TP_FLT10_REG_VCET0) | (((val) & 0xffff) << 0)) ++ ++/******************************************************************************* ++ * DiffServMapping 0 ++ ******************************************************************************/ ++ ++/* Priority Queue F (31:30) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQF (0x3 << 30) ++#define LTQ_ES_DFSRV_MAP0_REG_PQF_VAL(val) (((val) & 0x3) << 30) ++#define LTQ_ES_DFSRV_MAP0_REG_PQF_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQF) >> 30) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQF_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQF) | (((val) & 0x3) << 30)) ++/* Priority Queue E (29:28) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQE (0x3 << 28) ++#define LTQ_ES_DFSRV_MAP0_REG_PQE_VAL(val) (((val) & 0x3) << 28) ++#define LTQ_ES_DFSRV_MAP0_REG_PQE_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQE) >> 28) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQE_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQE) | (((val) & 0x3) << 28)) ++/* Priority Queue D (27:26) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQD (0x3 << 26) ++#define LTQ_ES_DFSRV_MAP0_REG_PQD_VAL(val) (((val) & 0x3) << 26) ++#define LTQ_ES_DFSRV_MAP0_REG_PQD_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQD) >> 26) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQD_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQD) | (((val) & 0x3) << 26)) ++/* Priority Queue C (25:24) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQC (0x3 << 24) ++#define LTQ_ES_DFSRV_MAP0_REG_PQC_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_DFSRV_MAP0_REG_PQC_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQC) >> 24) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQC_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQC) | (((val) & 0x3) << 24)) ++/* Priority Queue B (23:22) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQB (0x3 << 22) ++#define LTQ_ES_DFSRV_MAP0_REG_PQB_VAL(val) (((val) & 0x3) << 22) ++#define LTQ_ES_DFSRV_MAP0_REG_PQB_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQB) >> 22) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQB_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQB) | (((val) & 0x3) << 22)) ++/* Priority Queue A (21:20) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQA (0x3 << 20) ++#define LTQ_ES_DFSRV_MAP0_REG_PQA_VAL(val) (((val) & 0x3) << 20) ++#define LTQ_ES_DFSRV_MAP0_REG_PQA_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQA) >> 20) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQA_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQA) | (((val) & 0x3) << 20)) ++/* Priority Queue 9 (19:18) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ9 (0x3 << 18) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ9_VAL(val) (((val) & 0x3) << 18) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ9_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ9) >> 18) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ9_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ9) | (((val) & 0x3) << 18)) ++/* Priority Queue 8 (17:16) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ8 (0x3 << 16) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ8_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ8_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ8) >> 16) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ8_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ8) | (((val) & 0x3) << 16)) ++/* Priority Queue 7 (15:14) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ7 (0x3 << 14) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ7_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ7_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ7) >> 14) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ7_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ7) | (((val) & 0x3) << 14)) ++/* Priority Queue 6 (13:12) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ6 (0x3 << 12) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ6_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ6_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ6) >> 12) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ6_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ6) | (((val) & 0x3) << 12)) ++/* Priority Queue 5 (11:10) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ5 (0x3 << 10) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ5_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ5_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ5) >> 10) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ5_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ5) | (((val) & 0x3) << 10)) ++/* Priority Queue 4 (9:8) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ4 (0x3 << 8) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ4_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ4_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ4) >> 8) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ4_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ4) | (((val) & 0x3) << 8)) ++/* Priority Queue 3 (7:6) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ3 (0x3 << 6) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ3_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ3_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ3) >> 6) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ3) | (((val) & 0x3) << 6)) ++/* Priority Queue 2 (5:4) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ2 (0x3 << 4) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ2_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ2_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ2) >> 4) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ2) | (((val) & 0x3) << 4)) ++/* Priority Queue 1 (3:2) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ1 (0x3 << 2) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ1_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ1_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ1) >> 2) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ1) | (((val) & 0x3) << 2)) ++/* Priority Queue 0 (1:0) */ ++#define LTQ_ES_DFSRV_MAP0_REG_PQ0 (0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ0_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ0_GET(val) ((((val) & LTQ_ES_DFSRV_MAP0_REG_PQ0) >> 0) & 0x3) ++#define LTQ_ES_DFSRV_MAP0_REG_PQ0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP0_REG_PQ0) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * DiffServMapping 1 ++ ******************************************************************************/ ++ ++/* Priority Queue 1F (31:30) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1F (0x3 << 30) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_VAL(val) (((val) & 0x3) << 30) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1F) >> 30) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1F) | (((val) & 0x3) << 30)) ++/* Priority Queue 1E (29:28) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1E (0x3 << 28) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_VAL(val) (((val) & 0x3) << 28) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1E) >> 28) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1E) | (((val) & 0x3) << 28)) ++/* Priority Queue 1D (27:26) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1D (0x3 << 26) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_VAL(val) (((val) & 0x3) << 26) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1D) >> 26) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1D) | (((val) & 0x3) << 26)) ++/* Priority Queue 1C (25:24) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1C (0x3 << 24) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1C) >> 24) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1C) | (((val) & 0x3) << 24)) ++/* Priority Queue 1B (23:22) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1B (0x3 << 22) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_VAL(val) (((val) & 0x3) << 22) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1B) >> 22) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1B) | (((val) & 0x3) << 22)) ++/* Priority Queue 1A (21:20) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1A (0x3 << 20) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_VAL(val) (((val) & 0x3) << 20) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ1A) >> 20) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ1A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ1A) | (((val) & 0x3) << 20)) ++/* Priority Queue 19 (19:18) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ19 (0x3 << 18) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ19_VAL(val) (((val) & 0x3) << 18) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ19_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ19) >> 18) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ19_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ19) | (((val) & 0x3) << 18)) ++/* Priority Queue 18 (17:16) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ18 (0x3 << 16) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ18_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ18_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ18) >> 16) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ18_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ18) | (((val) & 0x3) << 16)) ++/* Priority Queue 17 (15:14) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ17 (0x3 << 14) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ17_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ17_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ17) >> 14) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ17_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ17) | (((val) & 0x3) << 14)) ++/* Priority Queue 16 (13:12) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ16 (0x3 << 12) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ16_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ16_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ16) >> 12) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ16_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ16) | (((val) & 0x3) << 12)) ++/* Priority Queue 15 (11:10) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ15 (0x3 << 10) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ15_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ15_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ15) >> 10) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ15_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ15) | (((val) & 0x3) << 10)) ++/* Priority Queue 14 (9:8) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ14 (0x3 << 8) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ14_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ14_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ14) >> 8) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ14_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ14) | (((val) & 0x3) << 8)) ++/* Priority Queue 13 (7:6) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ13 (0x3 << 6) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ13_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ13_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ13) >> 6) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ13_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ13) | (((val) & 0x3) << 6)) ++/* Priority Queue 12 (5:4) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ12 (0x3 << 4) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ12_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ12_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ12) >> 4) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ12_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ12) | (((val) & 0x3) << 4)) ++/* Priority Queue 11 (3:2) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ11 (0x3 << 2) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ11_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ11_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ11) >> 2) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ11_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ11) | (((val) & 0x3) << 2)) ++/* Priority Queue 10 (1:0) */ ++#define LTQ_ES_DFSRV_MAP1_REG_PQ10 (0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ10_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ10_GET(val) ((((val) & LTQ_ES_DFSRV_MAP1_REG_PQ10) >> 0) & 0x3) ++#define LTQ_ES_DFSRV_MAP1_REG_PQ10_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP1_REG_PQ10) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * DiffServMapping 2 ++ ******************************************************************************/ ++ ++/* Priority Queue 2F (31:30) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2F (0x3 << 30) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_VAL(val) (((val) & 0x3) << 30) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2F) >> 30) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2F) | (((val) & 0x3) << 30)) ++/* Priority Queue 2E (29:28) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2E (0x3 << 28) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_VAL(val) (((val) & 0x3) << 28) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2E) >> 28) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2E) | (((val) & 0x3) << 28)) ++/* Priority Queue 2D (27:26) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2D (0x3 << 26) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_VAL(val) (((val) & 0x3) << 26) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2D) >> 26) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2D) | (((val) & 0x3) << 26)) ++/* Priority Queue 2C (25:24) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2C (0x3 << 24) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2C) >> 24) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2C) | (((val) & 0x3) << 24)) ++/* Priority Queue 2B (23:22) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2B (0x3 << 22) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_VAL(val) (((val) & 0x3) << 22) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2B) >> 22) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2B) | (((val) & 0x3) << 22)) ++/* Priority Queue 2A (21:20) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2A (0x3 << 20) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_VAL(val) (((val) & 0x3) << 20) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ2A) >> 20) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ2A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ2A) | (((val) & 0x3) << 20)) ++/* Priority Queue 29 (19:18) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ29 (0x3 << 18) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ29_VAL(val) (((val) & 0x3) << 18) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ29_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ29) >> 18) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ29_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ29) | (((val) & 0x3) << 18)) ++/* Priority Queue 28 (17:16) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ28 (0x3 << 16) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ28_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ28_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ28) >> 16) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ28_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ28) | (((val) & 0x3) << 16)) ++/* Priority Queue 27 (15:14) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ27 (0x3 << 14) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ27_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ27_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ27) >> 14) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ27_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ27) | (((val) & 0x3) << 14)) ++/* Priority Queue 26 (13:12) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ26 (0x3 << 12) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ26_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ26_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ26) >> 12) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ26_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ26) | (((val) & 0x3) << 12)) ++/* Priority Queue 25 (11:10) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ25 (0x3 << 10) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ25_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ25_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ25) >> 10) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ25_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ25) | (((val) & 0x3) << 10)) ++/* Priority Queue 24 (9:8) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ24 (0x3 << 8) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ24_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ24_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ24) >> 8) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ24_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ24) | (((val) & 0x3) << 8)) ++/* Priority Queue 23 (7:6) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ23 (0x3 << 6) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ23_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ23_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ23) >> 6) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ23_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ23) | (((val) & 0x3) << 6)) ++/* Priority Queue 22 (5:4) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ22 (0x3 << 4) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ22_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ22_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ22) >> 4) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ22_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ22) | (((val) & 0x3) << 4)) ++/* Priority Queue 21 (3:2) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ21 (0x3 << 2) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ21_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ21_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ21) >> 2) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ21_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ21) | (((val) & 0x3) << 2)) ++/* Priority Queue 20 (1:0) */ ++#define LTQ_ES_DFSRV_MAP2_REG_PQ20 (0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ20_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ20_GET(val) ((((val) & LTQ_ES_DFSRV_MAP2_REG_PQ20) >> 0) & 0x3) ++#define LTQ_ES_DFSRV_MAP2_REG_PQ20_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP2_REG_PQ20) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * DiffServMapping 3 ++ ******************************************************************************/ ++ ++/* Priority Queue 3F (31:30) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3F (0x3 << 30) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_VAL(val) (((val) & 0x3) << 30) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3F) >> 30) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3F_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3F) | (((val) & 0x3) << 30)) ++/* Priority Queue 3E (29:28) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3E (0x3 << 28) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_VAL(val) (((val) & 0x3) << 28) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3E) >> 28) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3E_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3E) | (((val) & 0x3) << 28)) ++/* Priority Queue 3D (27:26) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3D (0x3 << 26) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_VAL(val) (((val) & 0x3) << 26) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3D) >> 26) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3D_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3D) | (((val) & 0x3) << 26)) ++/* Priority Queue 3C (25:24) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3C (0x3 << 24) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3C) >> 24) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3C_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3C) | (((val) & 0x3) << 24)) ++/* Priority Queue 3B (23:22) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3B (0x3 << 22) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_VAL(val) (((val) & 0x3) << 22) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3B) >> 22) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3B_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3B) | (((val) & 0x3) << 22)) ++/* Priority Queue 3A (21:20) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3A (0x3 << 20) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_VAL(val) (((val) & 0x3) << 20) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ3A) >> 20) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ3A_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ3A) | (((val) & 0x3) << 20)) ++/* Priority Queue 39 (19:18) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ39 (0x3 << 18) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ39_VAL(val) (((val) & 0x3) << 18) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ39_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ39) >> 18) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ39_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ39) | (((val) & 0x3) << 18)) ++/* Priority Queue 38 (17:16) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ38 (0x3 << 16) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ38_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ38_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ38) >> 16) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ38_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ38) | (((val) & 0x3) << 16)) ++/* Priority Queue 37 (15:14) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ37 (0x3 << 14) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ37_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ37_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ37) >> 14) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ37_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ37) | (((val) & 0x3) << 14)) ++/* Priority Queue 36 (13:12) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ36 (0x3 << 12) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ36_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ36_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ36) >> 12) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ36_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ36) | (((val) & 0x3) << 12)) ++/* Priority Queue 35 (11:10) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ35 (0x3 << 10) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ35_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ35_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ35) >> 10) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ35_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ35) | (((val) & 0x3) << 10)) ++/* Priority Queue 34 (9:8) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ34 (0x3 << 8) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ34_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ34_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ34) >> 8) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ34_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ34) | (((val) & 0x3) << 8)) ++/* Priority Queue 33 (7:6) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ33 (0x3 << 6) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ33_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ33_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ33) >> 6) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ33_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ33) | (((val) & 0x3) << 6)) ++/* Priority Queue 32 (5:4) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ32 (0x3 << 4) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ32_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ32_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ32) >> 4) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ32_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ32) | (((val) & 0x3) << 4)) ++/* Priority Queue 31 (3:2) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ31 (0x3 << 2) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ31_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ31_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ31) >> 2) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ31_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ31) | (((val) & 0x3) << 2)) ++/* Priority Queue 30 (1:0) */ ++#define LTQ_ES_DFSRV_MAP3_REG_PQ30 (0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ30_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ30_GET(val) ((((val) & LTQ_ES_DFSRV_MAP3_REG_PQ30) >> 0) & 0x3) ++#define LTQ_ES_DFSRV_MAP3_REG_PQ30_SET(reg,val) (reg) = ((reg & ~LTQ_ES_DFSRV_MAP3_REG_PQ30) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * TCP/UDP Port Filter 0 ++ ******************************************************************************/ ++ ++/* Reserved (31:30) */ ++#define LTQ_ES_TCP_PF0_REG_RES (0x3 << 30) ++#define LTQ_ES_TCP_PF0_REG_RES_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_RES) >> 30) & 0x3) ++/* Action for TCP/UDP Port Filter 0 (29:28) */ ++#define LTQ_ES_TCP_PF0_REG_ATUF0 (0x3 << 28) ++#define LTQ_ES_TCP_PF0_REG_ATUF0_VAL(val) (((val) & 0x3) << 28) ++#define LTQ_ES_TCP_PF0_REG_ATUF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_ATUF0) >> 28) & 0x3) ++#define LTQ_ES_TCP_PF0_REG_ATUF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_ATUF0) | (((val) & 0x3) << 28)) ++/* TCP/UDP PRI for TCP/UDP Port Filter 0 (27:26) */ ++#define LTQ_ES_TCP_PF0_REG_TUPF0 (0x3 << 26) ++#define LTQ_ES_TCP_PF0_REG_TUPF0_VAL(val) (((val) & 0x3) << 26) ++#define LTQ_ES_TCP_PF0_REG_TUPF0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_TUPF0) >> 26) & 0x3) ++#define LTQ_ES_TCP_PF0_REG_TUPF0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_TUPF0) | (((val) & 0x3) << 26)) ++/* Compare TCP/UDP Source Port or Destination Port (25:24) */ ++#define LTQ_ES_TCP_PF0_REG_COMP0 (0x3 << 24) ++#define LTQ_ES_TCP_PF0_REG_COMP0_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_TCP_PF0_REG_COMP0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_COMP0) >> 24) & 0x3) ++#define LTQ_ES_TCP_PF0_REG_COMP0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_COMP0) | (((val) & 0x3) << 24)) ++/* Port Range in TCP/UDP (23:16) */ ++#define LTQ_ES_TCP_PF0_REG_PRANGE0 (0xff << 16) ++#define LTQ_ES_TCP_PF0_REG_PRANGE0_VAL(val) (((val) & 0xff) << 16) ++#define LTQ_ES_TCP_PF0_REG_PRANGE0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_PRANGE0) >> 16) & 0xff) ++#define LTQ_ES_TCP_PF0_REG_PRANGE0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_PRANGE0) | (((val) & 0xff) << 16)) ++/* Base Port number 0 (15:0) */ ++#define LTQ_ES_TCP_PF0_REG_BASEPT0 (0xffff) ++#define LTQ_ES_TCP_PF0_REG_BASEPT0_VAL(val) (((val) & 0xffff) << 0) ++#define LTQ_ES_TCP_PF0_REG_BASEPT0_GET(val) ((((val) & LTQ_ES_TCP_PF0_REG_BASEPT0) >> 0) & 0xffff) ++#define LTQ_ES_TCP_PF0_REG_BASEPT0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_TCP_PF0_REG_BASEPT0) | (((val) & 0xffff) << 0)) ++ ++/******************************************************************************* ++ * Reserved DA(0180C2000003~0180C2000000) control register ++ ******************************************************************************/ ++ ++/* Valid bit for 0180C2000003 (31) */ ++#define LTQ_ES_RA_03_00_REG_RA03_VALID (0x1 << 31) ++#define LTQ_ES_RA_03_00_REG_RA03_VALID_VAL(val) (((val) & 0x1) << 31) ++#define LTQ_ES_RA_03_00_REG_RA03_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_VALID) >> 31) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA03_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_VALID) | (((val) & 0x1) << 31)) ++/* Span bit for 0180C2000003 (30) */ ++#define LTQ_ES_RA_03_00_REG_RA03_SPAN (0x1 << 30) ++#define LTQ_ES_RA_03_00_REG_RA03_SPAN_VAL(val) (((val) & 0x1) << 30) ++#define LTQ_ES_RA_03_00_REG_RA03_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_SPAN) >> 30) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA03_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_SPAN) | (((val) & 0x1) << 30)) ++/* Management bit for 0180C2000003 (29) */ ++#define LTQ_ES_RA_03_00_REG_RA03_MG (0x1 << 29) ++#define LTQ_ES_RA_03_00_REG_RA03_MG_VAL(val) (((val) & 0x1) << 29) ++#define LTQ_ES_RA_03_00_REG_RA03_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_MG) >> 29) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA03_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_MG) | (((val) & 0x1) << 29)) ++/* Cross_VLAN bit for 0180C2000003 (28) */ ++#define LTQ_ES_RA_03_00_REG_RA03_CV (0x1 << 28) ++#define LTQ_ES_RA_03_00_REG_RA03_CV_VAL(val) (((val) & 0x1) << 28) ++#define LTQ_ES_RA_03_00_REG_RA03_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_CV) >> 28) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA03_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_CV) | (((val) & 0x1) << 28)) ++/* TXTAG bit for 0180C2000003 (27:26) */ ++#define LTQ_ES_RA_03_00_REG_RA03_TXTAG (0x3 << 26) ++#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_VAL(val) (((val) & 0x3) << 26) ++#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_TXTAG) >> 26) & 0x3) ++#define LTQ_ES_RA_03_00_REG_RA03_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_TXTAG) | (((val) & 0x3) << 26)) ++/* Action bit for 0180C2000003 (25:24) */ ++#define LTQ_ES_RA_03_00_REG_RA03_ACT (0x3 << 24) ++#define LTQ_ES_RA_03_00_REG_RA03_ACT_VAL(val) (((val) & 0x3) << 24) ++#define LTQ_ES_RA_03_00_REG_RA03_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA03_ACT) >> 24) & 0x3) ++#define LTQ_ES_RA_03_00_REG_RA03_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA03_ACT) | (((val) & 0x3) << 24)) ++/* Valid bit for 0180C2000002 (23) */ ++#define LTQ_ES_RA_03_00_REG_RA02_VALID (0x1 << 23) ++#define LTQ_ES_RA_03_00_REG_RA02_VALID_VAL(val) (((val) & 0x1) << 23) ++#define LTQ_ES_RA_03_00_REG_RA02_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_VALID) >> 23) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA02_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_VALID) | (((val) & 0x1) << 23)) ++/* Span bit for 0180C2000002 (22) */ ++#define LTQ_ES_RA_03_00_REG_RA02_SPAN (0x1 << 22) ++#define LTQ_ES_RA_03_00_REG_RA02_SPAN_VAL(val) (((val) & 0x1) << 22) ++#define LTQ_ES_RA_03_00_REG_RA02_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_SPAN) >> 22) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA02_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_SPAN) | (((val) & 0x1) << 22)) ++/* Management bit for 0180C2000002 (21) */ ++#define LTQ_ES_RA_03_00_REG_RA02_MG (0x1 << 21) ++#define LTQ_ES_RA_03_00_REG_RA02_MG_VAL(val) (((val) & 0x1) << 21) ++#define LTQ_ES_RA_03_00_REG_RA02_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_MG) >> 21) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA02_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_MG) | (((val) & 0x1) << 21)) ++/* Cross_VLAN bit for 0180C2000002 (20) */ ++#define LTQ_ES_RA_03_00_REG_RA02_CV (0x1 << 20) ++#define LTQ_ES_RA_03_00_REG_RA02_CV_VAL(val) (((val) & 0x1) << 20) ++#define LTQ_ES_RA_03_00_REG_RA02_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_CV) >> 20) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA02_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_CV) | (((val) & 0x1) << 20)) ++/* TXTAG bit for 0180C2000002 (19:18) */ ++#define LTQ_ES_RA_03_00_REG_RA02_TXTAG (0x3 << 18) ++#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_VAL(val) (((val) & 0x3) << 18) ++#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_TXTAG) >> 18) & 0x3) ++#define LTQ_ES_RA_03_00_REG_RA02_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_TXTAG) | (((val) & 0x3) << 18)) ++/* Action bit for 0180C2000002 (17:16) */ ++#define LTQ_ES_RA_03_00_REG_RA02_ACT (0x3 << 16) ++#define LTQ_ES_RA_03_00_REG_RA02_ACT_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_ES_RA_03_00_REG_RA02_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA02_ACT) >> 16) & 0x3) ++#define LTQ_ES_RA_03_00_REG_RA02_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA02_ACT) | (((val) & 0x3) << 16)) ++/* Valid bit for 0180C2000001 (15) */ ++#define LTQ_ES_RA_03_00_REG_RA01_VALID (0x1 << 15) ++#define LTQ_ES_RA_03_00_REG_RA01_VALID_VAL(val) (((val) & 0x1) << 15) ++#define LTQ_ES_RA_03_00_REG_RA01_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_VALID) >> 15) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA01_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_VALID) | (((val) & 0x1) << 15)) ++/* Span bit for 0180C2000001 (14) */ ++#define LTQ_ES_RA_03_00_REG_RA01_SPAN (0x1 << 14) ++#define LTQ_ES_RA_03_00_REG_RA01_SPAN_VAL(val) (((val) & 0x1) << 14) ++#define LTQ_ES_RA_03_00_REG_RA01_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_SPAN) >> 14) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA01_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_SPAN) | (((val) & 0x1) << 14)) ++/* Management bit for 0180C2000001 (13) */ ++#define LTQ_ES_RA_03_00_REG_RA01_MG (0x1 << 13) ++#define LTQ_ES_RA_03_00_REG_RA01_MG_VAL(val) (((val) & 0x1) << 13) ++#define LTQ_ES_RA_03_00_REG_RA01_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_MG) >> 13) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA01_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_MG) | (((val) & 0x1) << 13)) ++/* Cross_VLAN bit for 0180C2000001 (12) */ ++#define LTQ_ES_RA_03_00_REG_RA01_CV (0x1 << 12) ++#define LTQ_ES_RA_03_00_REG_RA01_CV_VAL(val) (((val) & 0x1) << 12) ++#define LTQ_ES_RA_03_00_REG_RA01_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_CV) >> 12) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA01_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_CV) | (((val) & 0x1) << 12)) ++/* TXTAG bit for 0180C2000001 (11:10) */ ++#define LTQ_ES_RA_03_00_REG_RA01_TXTAG (0x3 << 10) ++#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_TXTAG) >> 10) & 0x3) ++#define LTQ_ES_RA_03_00_REG_RA01_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_TXTAG) | (((val) & 0x3) << 10)) ++/* Action bit for 0180C2000001 (9:8) */ ++#define LTQ_ES_RA_03_00_REG_RA01_ACT (0x3 << 8) ++#define LTQ_ES_RA_03_00_REG_RA01_ACT_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_ES_RA_03_00_REG_RA01_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA01_ACT) >> 8) & 0x3) ++#define LTQ_ES_RA_03_00_REG_RA01_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA01_ACT) | (((val) & 0x3) << 8)) ++/* Valid bit for 0180C2000000 (7) */ ++#define LTQ_ES_RA_03_00_REG_RA00_VALID (0x1 << 7) ++#define LTQ_ES_RA_03_00_REG_RA00_VALID_VAL(val) (((val) & 0x1) << 7) ++#define LTQ_ES_RA_03_00_REG_RA00_VALID_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_VALID) >> 7) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA00_VALID_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_VALID) | (((val) & 0x1) << 7)) ++/* Span bit for 0180C2000000 (6) */ ++#define LTQ_ES_RA_03_00_REG_RA00_SPAN (0x1 << 6) ++#define LTQ_ES_RA_03_00_REG_RA00_SPAN_VAL(val) (((val) & 0x1) << 6) ++#define LTQ_ES_RA_03_00_REG_RA00_SPAN_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_SPAN) >> 6) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA00_SPAN_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_SPAN) | (((val) & 0x1) << 6)) ++/* Management bit for 0180C2000000 (5) */ ++#define LTQ_ES_RA_03_00_REG_RA00_MG (0x1 << 5) ++#define LTQ_ES_RA_03_00_REG_RA00_MG_VAL(val) (((val) & 0x1) << 5) ++#define LTQ_ES_RA_03_00_REG_RA00_MG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_MG) >> 5) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA00_MG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_MG) | (((val) & 0x1) << 5)) ++/* Cross_VLAN bit for 0180C2000000 (4) */ ++#define LTQ_ES_RA_03_00_REG_RA00_CV (0x1 << 4) ++#define LTQ_ES_RA_03_00_REG_RA00_CV_VAL(val) (((val) & 0x1) << 4) ++#define LTQ_ES_RA_03_00_REG_RA00_CV_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_CV) >> 4) & 0x1) ++#define LTQ_ES_RA_03_00_REG_RA00_CV_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_CV) | (((val) & 0x1) << 4)) ++/* TXTAG bit for 0180C2000000 (3:2) */ ++#define LTQ_ES_RA_03_00_REG_RA00_TXTAG (0x3 << 2) ++#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_TXTAG) >> 2) & 0x3) ++#define LTQ_ES_RA_03_00_REG_RA00_TXTAG_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_TXTAG) | (((val) & 0x3) << 2)) ++/* Action bit for 0180C2000000 (1:0) */ ++#define LTQ_ES_RA_03_00_REG_RA00_ACT (0x3) ++#define LTQ_ES_RA_03_00_REG_RA00_ACT_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_ES_RA_03_00_REG_RA00_ACT_GET(val) ((((val) & LTQ_ES_RA_03_00_REG_RA00_ACT) >> 0) & 0x3) ++#define LTQ_ES_RA_03_00_REG_RA00_ACT_SET(reg,val) (reg) = ((reg & ~LTQ_ES_RA_03_00_REG_RA00_ACT) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * Protocol Filter 0 ++ ******************************************************************************/ ++ ++/* Value Compared with Protocol in IP Header (31:24) */ ++#define LTQ_ES_PRTCL_F0_REG_PFR3 (0xff << 24) ++#define LTQ_ES_PRTCL_F0_REG_PFR3_VAL(val) (((val) & 0xff) << 24) ++#define LTQ_ES_PRTCL_F0_REG_PFR3_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR3) >> 24) & 0xff) ++#define LTQ_ES_PRTCL_F0_REG_PFR3_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR3) | (((val) & 0xff) << 24)) ++/* Value Compared with Protocol in IP Header (23:16) */ ++#define LTQ_ES_PRTCL_F0_REG_PFR2 (0xff << 16) ++#define LTQ_ES_PRTCL_F0_REG_PFR2_VAL(val) (((val) & 0xff) << 16) ++#define LTQ_ES_PRTCL_F0_REG_PFR2_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR2) >> 16) & 0xff) ++#define LTQ_ES_PRTCL_F0_REG_PFR2_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR2) | (((val) & 0xff) << 16)) ++/* Value Compared with Protocol in IP Header (15:8) */ ++#define LTQ_ES_PRTCL_F0_REG_PFR1 (0xff << 8) ++#define LTQ_ES_PRTCL_F0_REG_PFR1_VAL(val) (((val) & 0xff) << 8) ++#define LTQ_ES_PRTCL_F0_REG_PFR1_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR1) >> 8) & 0xff) ++#define LTQ_ES_PRTCL_F0_REG_PFR1_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR1) | (((val) & 0xff) << 8)) ++/* Value Compared with Protocol in IP Header (7:0) */ ++#define LTQ_ES_PRTCL_F0_REG_PFR0 (0xff) ++#define LTQ_ES_PRTCL_F0_REG_PFR0_VAL(val) (((val) & 0xff) << 0) ++#define LTQ_ES_PRTCL_F0_REG_PFR0_GET(val) ((((val) & LTQ_ES_PRTCL_F0_REG_PFR0) >> 0) & 0xff) ++#define LTQ_ES_PRTCL_F0_REG_PFR0_SET(reg,val) (reg) = ((reg & ~LTQ_ES_PRTCL_F0_REG_PFR0) | (((val) & 0xff) << 0)) ++ ++#endif +Index: linux-3.3.8/include/linux/svip_nat.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/include/linux/svip_nat.h 2012-07-31 15:46:02.476476158 +0200 +@@ -0,0 +1,37 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ Am Campeon 1-12; 81726 Munich, Germany ++ ++ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, ++ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS ++ SOFTWARE IS FREE OF CHARGE. ++ ++ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS ++ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING ++ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE ++ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD ++ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL ++ PROPERTY INFRINGEMENT. ++ ++ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT ++ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM ++ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ DEALINGS IN THE SOFTWARE. ++*******************************************************************************/ ++#ifndef _SVIP_NAT_H ++#define _SVIP_NAT_H ++ ++/* The declarations here have to be in a header file, because ++ * they need to be known both to the kernel module ++ * (in chardev.c) and the process calling ioctl (ioctl.c) ++ */ ++#include <linux/svip_nat_io.h> ++ ++#define SVIP_NAT_VERSION "3.1" ++extern int do_SVIP_NAT(struct sk_buff *); ++ ++#endif +Index: linux-3.3.8/include/linux/svip_nat_io.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/include/linux/svip_nat_io.h 2012-07-31 15:46:02.476476158 +0200 +@@ -0,0 +1,103 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ Am Campeon 1-12; 81726 Munich, Germany ++ ++ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, ++ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS ++ SOFTWARE IS FREE OF CHARGE. ++ ++ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS ++ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING ++ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE ++ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD ++ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL ++ PROPERTY INFRINGEMENT. ++ ++ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT ++ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM ++ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ DEALINGS IN THE SOFTWARE. ++ *******************************************************************************/ ++#ifndef _SVIP_NAT_IO_H_ ++#define _SVIP_NAT_IO_H_ ++ ++#include <asm/ioctl.h> ++ ++#define SVIP_NAT_DEVICE_NAME "svip_nat" ++#define PATH_SVIP_NAT_DEVICE_NAME "/dev/"SVIP_NAT_DEVICE_NAME ++ ++#define MAJOR_NUM_SVIP_NAT 10 ++#define MINOR_NUM_SVIP_NAT 120 ++ ++/** maximum SVIP devices supported on a Line card system */ ++#define SVIP_SYS_NUM 12 ++ ++/** maximum voice packet channels possible per SVIP device */ ++#define SVIP_CODEC_NUM 16 ++ ++/** start UDP port number of the SVIP Linecard System */ ++#define SVIP_UDP_FROM 50000 ++ ++/** @defgroup SVIP_NATAPI SVIP Custom NAT ioctl interface. ++ An ioctl interface is provided to add a rule into the SVIP NAT table and ++ to respectively remove the rule form it. The ioctl interface is accessible ++ using the fd issued upon opening the special device node /dev/svip_nat. ++ @{ */ ++ ++/** Used to add a new rule to the SVIP Custom NAT table. If a rule already ++ exists for the target UDP port, that rule shall be overwritten. ++ ++ \param SVIP_NAT_IO_Rule_t* The parameter points to a ++ \ref SVIP_NAT_IO_Rule_t structure. ++ */ ++#define FIO_SVIP_NAT_RULE_ADD \ ++ _IOW(MAJOR_NUM_SVIP_NAT, 1, SVIP_NAT_IO_Rule_t) ++ ++/** Used to remove a rule from the SVIP Custom NAT table. No check is ++ performed whether the rule already exists or not. The remove operation is ++ performed as long as the target UDP port is within the defined port range. ++ ++ \param SVIP_NAT_IO_Rule_t* The parameter points to a ++ \ref SVIP_NAT_IO_Rule_t structure. ++ */ ++#define FIO_SVIP_NAT_RULE_REMOVE \ ++ _IOW(MAJOR_NUM_SVIP_NAT, 2, SVIP_NAT_IO_Rule_t) ++ ++/** Used to list all rules in the SVIP Custom NAT table. ++ ++ \param <none> ++ */ ++#define FIO_SVIP_NAT_RULE_LIST \ ++ _IO(MAJOR_NUM_SVIP_NAT, 3) ++ ++/** IP address in network-byte order */ ++typedef u32 SVIP_IP_ADDR_t; ++/** UDP port in network-byte order */ ++typedef u16 SVIP_UDP_PORT_t; ++ ++#ifndef ETH_ALEN ++#define ETH_ALEN 6 /* Octets in one ethernet address */ ++#endif ++ ++/** NAT parameters part of the NAT table. ++ These paramters are configurable through the NAT API. */ ++typedef struct SVIP_NAT_IO_Rule ++{ ++ /** Remote peer, IP address */ ++ SVIP_IP_ADDR_t remIP; ++ /** Remote peer, MAC address */ ++ u8 remMAC[ETH_ALEN]; ++ /** Target SVIP, IP address (local peer) */ ++ SVIP_IP_ADDR_t locIP; ++ /** Target SVIP, MAC address */ ++ u8 locMAC[ETH_ALEN]; ++ /** Target SVIP, UDP port number */ ++ SVIP_UDP_PORT_t locUDP; ++} SVIP_NAT_IO_Rule_t; ++ ++/** @} */ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/mps_reg.h 2012-07-31 15:46:02.476476158 +0200 +@@ -0,0 +1,242 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __MPS_REG_H ++#define __MPS_REG_H ++ ++#define mbs_r32(reg) ltq_r32(&mbs->reg) ++#define mbs_w32(val, reg) ltq_w32(val, &mbs->reg) ++#define mbs_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &mbs->reg) ++ ++/** MBS register structure */ ++struct svip_reg_mbs { ++ unsigned long reserved0[4]; ++ unsigned long mbsr0; /* 0x0010 */ ++ unsigned long mbsr1; /* 0x0014 */ ++ unsigned long mbsr2; /* 0x0018 */ ++ unsigned long mbsr3; /* 0x001c */ ++ unsigned long mbsr4; /* 0x0020 */ ++ unsigned long mbsr5; /* 0x0024 */ ++ unsigned long mbsr6; /* 0x0028 */ ++ unsigned long mbsr7; /* 0x002c */ ++ unsigned long mbsr8; /* 0x0030 */ ++ unsigned long mbsr9; /* 0x0034 */ ++ unsigned long mbsr10; /* 0x0038 */ ++ unsigned long mbsr11; /* 0x003c */ ++ unsigned long mbsr12; /* 0x0040 */ ++ unsigned long mbsr13; /* 0x0044 */ ++ unsigned long mbsr14; /* 0x0048 */ ++ unsigned long mbsr15; /* 0x004c */ ++ unsigned long mbsr16; /* 0x0050 */ ++ unsigned long mbsr17; /* 0x0054 */ ++ unsigned long mbsr18; /* 0x0058 */ ++ unsigned long mbsr19; /* 0x005c */ ++ unsigned long mbsr20; /* 0x0060 */ ++ unsigned long mbsr21; /* 0x0064 */ ++ unsigned long mbsr22; /* 0x0068 */ ++ unsigned long mbsr23; /* 0x006c */ ++ unsigned long mbsr24; /* 0x0070 */ ++ unsigned long mbsr25; /* 0x0074 */ ++ unsigned long mbsr26; /* 0x0078 */ ++ unsigned long mbsr27; /* 0x007c */ ++ unsigned long mbsr28; /* 0x0080 */ ++}; ++ ++/** MPS register structure */ ++struct svip_reg_mps { ++ volatile unsigned long mps_swirn0set; /* 0x0000 */ ++ volatile unsigned long mps_swirn0en; /* 0x0004 */ ++ volatile unsigned long mps_swirn0cr; /* 0x0008 */ ++ volatile unsigned long mps_swirn0icr; /* 0x000C */ ++ volatile unsigned long mps_swirn1set; /* 0x0010 */ ++ volatile unsigned long mps_swirn1en; /* 0x0014 */ ++ volatile unsigned long mps_swirn1cr; /* 0x0018 */ ++ volatile unsigned long mps_swirn1icr; /* 0x001C */ ++ volatile unsigned long mps_swirn2set; /* 0x0020 */ ++ volatile unsigned long mps_swirn2en; /* 0x0024 */ ++ volatile unsigned long mps_swirn2cr; /* 0x0028 */ ++ volatile unsigned long mps_swirn2icr; /* 0x002C */ ++ volatile unsigned long mps_swirn3set; /* 0x0030 */ ++ volatile unsigned long mps_swirn3en; /* 0x0034 */ ++ volatile unsigned long mps_swirn3cr; /* 0x0038 */ ++ volatile unsigned long mps_swirn3icr; /* 0x003C */ ++ volatile unsigned long mps_swirn4set; /* 0x0040 */ ++ volatile unsigned long mps_swirn4en; /* 0x0044 */ ++ volatile unsigned long mps_swirn4cr; /* 0x0048 */ ++ volatile unsigned long mps_swirn4icr; /* 0x004C */ ++ volatile unsigned long mps_swirn5set; /* 0x0050 */ ++ volatile unsigned long mps_swirn5en; /* 0x0054 */ ++ volatile unsigned long mps_swirn5cr; /* 0x0058 */ ++ volatile unsigned long mps_swirn5icr; /* 0x005C */ ++ volatile unsigned long mps_swirn6set; /* 0x0060 */ ++ volatile unsigned long mps_swirn6en; /* 0x0064 */ ++ volatile unsigned long mps_swirn6cr; /* 0x0068 */ ++ volatile unsigned long mps_swirn6icr; /* 0x006C */ ++ volatile unsigned long mps_swirn7set; /* 0x0070 */ ++ volatile unsigned long mps_swirn7en; /* 0x0074 */ ++ volatile unsigned long mps_swirn7cr; /* 0x0078 */ ++ volatile unsigned long mps_swirn7icr; /* 0x007C */ ++ volatile unsigned long mps_swirn8set; /* 0x0080 */ ++ volatile unsigned long mps_swirn8en; /* 0x0084 */ ++ volatile unsigned long mps_swirn8cr; /* 0x0088 */ ++ volatile unsigned long mps_swirn8icr; /* 0x008C */ ++}; ++ ++/* Software Interrupt */ ++#define IFX_MPS_SWIRN0SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0000)) ++#define IFX_MPS_SWIRN0EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0004)) ++#define IFX_MPS_SWIRN0CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0008)) ++#define IFX_MPS_SWIRN0ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x000C)) ++#define IFX_MPS_SWIRN1SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0010)) ++#define IFX_MPS_SWIRN1EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0014)) ++#define IFX_MPS_SWIRN1CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0018)) ++#define IFX_MPS_SWIRN1ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x001C)) ++#define IFX_MPS_SWIRN2SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0020)) ++#define IFX_MPS_SWIRN2EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0024)) ++#define IFX_MPS_SWIRN2CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0028)) ++#define IFX_MPS_SWIRN2ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x002C)) ++#define IFX_MPS_SWIRN3SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0030)) ++#define IFX_MPS_SWIRN3EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0034)) ++#define IFX_MPS_SWIRN3CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0038)) ++#define IFX_MPS_SWIRN3ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x003C)) ++#define IFX_MPS_SWIRN4SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0040)) ++#define IFX_MPS_SWIRN4EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0044)) ++#define IFX_MPS_SWIRN4CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0048)) ++#define IFX_MPS_SWIRN4ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x004C)) ++#define IFX_MPS_SWIRN5SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0050)) ++#define IFX_MPS_SWIRN5EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0054)) ++#define IFX_MPS_SWIRN5CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0058)) ++#define IFX_MPS_SWIRN5ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x005C)) ++#define IFX_MPS_SWIRN6SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0060)) ++#define IFX_MPS_SWIRN6EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0064)) ++#define IFX_MPS_SWIRN6CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0068)) ++#define IFX_MPS_SWIRN6ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x006C)) ++#define IFX_MPS_SWIRN7SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0070)) ++#define IFX_MPS_SWIRN7EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0074)) ++#define IFX_MPS_SWIRN7CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0078)) ++#define IFX_MPS_SWIRN7ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x007C)) ++#define IFX_MPS_SWIRN8SET ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0080)) ++#define IFX_MPS_SWIRN8EN ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0084)) ++#define IFX_MPS_SWIRN8ICR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x008C)) ++#define IFX_MPS_SWIRN8CR ((volatile unsigned int*)(LTQ_SWINT_BASE + 0x0088)) ++ ++/******************************************************************************* ++ * MPS_SWIRNSET Register ++ ******************************************************************************/ ++ ++/* Software Interrupt Request IR5 (5) */ ++#define IFX_MPS_SWIRNSET_IR5 (0x1 << 5) ++#define IFX_MPS_SWIRNSET_IR5_VAL(val) (((val) & 0x1) << 5) ++#define IFX_MPS_SWIRNSET_IR5_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR5) | (val) & 1) << 5) ++/* Software Interrupt Request IR4 (4) */ ++#define IFX_MPS_SWIRNSET_IR4 (0x1 << 4) ++#define IFX_MPS_SWIRNSET_IR4_VAL(val) (((val) & 0x1) << 4) ++#define IFX_MPS_SWIRNSET_IR4_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR4) | (val) & 1) << 4) ++/* Software Interrupt Request IR3 (3) */ ++#define IFX_MPS_SWIRNSET_IR3 (0x1 << 3) ++#define IFX_MPS_SWIRNSET_IR3_VAL(val) (((val) & 0x1) << 3) ++#define IFX_MPS_SWIRNSET_IR3_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR3) | (val) & 1) << 3) ++/* Software Interrupt Request IR2 (2) */ ++#define IFX_MPS_SWIRNSET_IR2 (0x1 << 2) ++#define IFX_MPS_SWIRNSET_IR2_VAL(val) (((val) & 0x1) << 2) ++#define IFX_MPS_SWIRNSET_IR2_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR2) | (val) & 1) << 2) ++/* Software Interrupt Request IR1 (1) */ ++#define IFX_MPS_SWIRNSET_IR1 (0x1 << 1) ++#define IFX_MPS_SWIRNSET_IR1_VAL(val) (((val) & 0x1) << 1) ++#define IFX_MPS_SWIRNSET_IR1_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR1) | (val) & 1) << 1) ++/* Software Interrupt Request IR0 (0) */ ++#define IFX_MPS_SWIRNSET_IR0 (0x1) ++#define IFX_MPS_SWIRNSET_IR0_VAL(val) (((val) & 0x1) << 0) ++#define IFX_MPS_SWIRNSET_IR0_SET(reg,val) (reg) = (((reg & ~IFX_MPS_SWIRNSET_IR0) | (val) & 1) << 0) ++ ++/******************************************************************************* ++ * MPS_SWIRNEN Register ++ ******************************************************************************/ ++ ++/* Software Interrupt Request IR5 (5) */ ++#define IFX_MPS_SWIRNEN_IR5 (0x1 << 5) ++#define IFX_MPS_SWIRNEN_IR5_VAL(val) (((val) & 0x1) << 5) ++#define IFX_MPS_SWIRNEN_IR5_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR5) >> 5) & 0x1) ++#define IFX_MPS_SWIRNEN_IR5_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR5) | (((val) & 0x1) << 5)) ++/* Software Interrupt Request IR4 (4) */ ++#define IFX_MPS_SWIRNEN_IR4 (0x1 << 4) ++#define IFX_MPS_SWIRNEN_IR4_VAL(val) (((val) & 0x1) << 4) ++#define IFX_MPS_SWIRNEN_IR4_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR4) >> 4) & 0x1) ++#define IFX_MPS_SWIRNEN_IR4_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR4) | (((val) & 0x1) << 4)) ++/* Software Interrupt Request IR3 (3) */ ++#define IFX_MPS_SWIRNEN_IR3 (0x1 << 3) ++#define IFX_MPS_SWIRNEN_IR3_VAL(val) (((val) & 0x1) << 3) ++#define IFX_MPS_SWIRNEN_IR3_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR3) >> 3) & 0x1) ++#define IFX_MPS_SWIRNEN_IR3_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR3) | (((val) & 0x1) << 3)) ++/* Software Interrupt Request IR2 (2) */ ++#define IFX_MPS_SWIRNEN_IR2 (0x1 << 2) ++#define IFX_MPS_SWIRNEN_IR2_VAL(val) (((val) & 0x1) << 2) ++#define IFX_MPS_SWIRNEN_IR2_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR2) >> 2) & 0x1) ++#define IFX_MPS_SWIRNEN_IR2_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR2) | (((val) & 0x1) << 2)) ++/* Software Interrupt Request IR1 (1) */ ++#define IFX_MPS_SWIRNEN_IR1 (0x1 << 1) ++#define IFX_MPS_SWIRNEN_IR1_VAL(val) (((val) & 0x1) << 1) ++#define IFX_MPS_SWIRNEN_IR1_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR1) >> 1) & 0x1) ++#define IFX_MPS_SWIRNEN_IR1_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR1) | (((val) & 0x1) << 1)) ++/* Software Interrupt Request IR0 (0) */ ++#define IFX_MPS_SWIRNEN_IR0 (0x1) ++#define IFX_MPS_SWIRNEN_IR0_VAL(val) (((val) & 0x1) << 0) ++#define IFX_MPS_SWIRNEN_IR0_GET(val) ((((val) & IFX_MPS_SWIRNEN_IR0) >> 0) & 0x1) ++#define IFX_MPS_SWIRNEN_IR0_SET(reg,val) (reg) = ((reg & ~IFX_MPS_SWIRNEN_IR0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * MPS_SWIRNICR Register ++ ******************************************************************************/ ++ ++/* Software Interrupt Request IR5 (5) */ ++#define IFX_MPS_SWIRNICR_IR5 (0x1 << 5) ++#define IFX_MPS_SWIRNICR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR5) >> 5) & 0x1) ++/* Software Interrupt Request IR4 (4) */ ++#define IFX_MPS_SWIRNICR_IR4 (0x1 << 4) ++#define IFX_MPS_SWIRNICR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR4) >> 4) & 0x1) ++/* Software Interrupt Request IR3 (3) */ ++#define IFX_MPS_SWIRNICR_IR3 (0x1 << 3) ++#define IFX_MPS_SWIRNICR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR3) >> 3) & 0x1) ++/* Software Interrupt Request IR2 (2) */ ++#define IFX_MPS_SWIRNICR_IR2 (0x1 << 2) ++#define IFX_MPS_SWIRNICR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR2) >> 2) & 0x1) ++/* Software Interrupt Request IR1 (1) */ ++#define IFX_MPS_SWIRNICR_IR1 (0x1 << 1) ++#define IFX_MPS_SWIRNICR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR1) >> 1) & 0x1) ++/* Software Interrupt Request IR0 (0) */ ++#define IFX_MPS_SWIRNICR_IR0 (0x1) ++#define IFX_MPS_SWIRNICR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNICR_IR0) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * MPS_SWIRNCR Register ++ ******************************************************************************/ ++ ++/* Software Interrupt Request IR5 (5) */ ++#define IFX_MPS_SWIRNCR_IR5 (0x1 << 5) ++#define IFX_MPS_SWIRNCR_IR5_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR5) >> 5) & 0x1) ++/* Software Interrupt Request IR4 (4) */ ++#define IFX_MPS_SWIRNCR_IR4 (0x1 << 4) ++#define IFX_MPS_SWIRNCR_IR4_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR4) >> 4) & 0x1) ++/* Software Interrupt Request IR3 (3) */ ++#define IFX_MPS_SWIRNCR_IR3 (0x1 << 3) ++#define IFX_MPS_SWIRNCR_IR3_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR3) >> 3) & 0x1) ++/* Software Interrupt Request IR2 (2) */ ++#define IFX_MPS_SWIRNCR_IR2 (0x1 << 2) ++#define IFX_MPS_SWIRNCR_IR2_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR2) >> 2) & 0x1) ++/* Software Interrupt Request IR1 (1) */ ++#define IFX_MPS_SWIRNCR_IR1 (0x1 << 1) ++#define IFX_MPS_SWIRNCR_IR1_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR1) >> 1) & 0x1) ++/* Software Interrupt Request IR0 (0) */ ++#define IFX_MPS_SWIRNCR_IR0 (0x1) ++#define IFX_MPS_SWIRNCR_IR0_GET(val) ((((val) & IFX_MPS_SWIRNCR_IR0) >> 0) & 0x1) ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/status_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/status_reg.h 2012-07-31 15:46:02.476476158 +0200 +@@ -0,0 +1,130 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __STATUS_REG_H ++#define __STATUS_REG_H ++ ++#define status_r32(reg) ltq_r32(&status->reg) ++#define status_w32(val, reg) ltq_w32(val, &status->reg) ++#define status_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &status->reg) ++ ++/** STATUS register structure */ ++struct svip_reg_status { ++ unsigned long fuse_deu; /* 0x0000 */ ++ unsigned long fuse_cpu; /* 0x0004 */ ++ unsigned long fuse_pll; /* 0x0008 */ ++ unsigned long chipid; /* 0x000C */ ++ unsigned long config; /* 0x0010 */ ++ unsigned long chip_loc; /* 0x0014 */ ++ unsigned long fuse_spare; /* 0x0018 */ ++}; ++ ++/******************************************************************************* ++ * Fuse for DEU Settings ++ ******************************************************************************/ ++ ++/* Fuse for Enabling the TRNG (6) */ ++#define STATUS_FUSE_DEU_TRNG (0x1 << 6) ++#define STATUS_FUSE_DEU_TRNG_GET(val) ((((val) & STATUS_FUSE_DEU_TRNG) >> 6) & 0x1) ++/* Fuse for Enabling the DES Submodule (5) */ ++#define STATUS_FUSE_DEU_DES (0x1 << 5) ++#define STATUS_FUSE_DEU_DES_GET(val) ((((val) & STATUS_FUSE_DEU_DES) >> 5) & 0x1) ++/* Fuse for Enabling the 3DES Submodule (4) */ ++#define STATUS_FUSE_DEU_3DES (0x1 << 4) ++#define STATUS_FUSE_DEU_3DES_GET(val) ((((val) & STATUS_FUSE_DEU_3DES) >> 4) & 0x1) ++/* Fuse for Enabling the AES Submodule (3) */ ++#define STATUS_FUSE_DEU_AES (0x1 << 3) ++#define STATUS_FUSE_DEU_AES_GET(val) ((((val) & STATUS_FUSE_DEU_AES) >> 3) & 0x1) ++/* Fuse for Enabling the HASH Submodule (2) */ ++#define STATUS_FUSE_DEU_HASH (0x1 << 2) ++#define STATUS_FUSE_DEU_HASH_GET(val) ((((val) & STATUS_FUSE_DEU_HASH) >> 2) & 0x1) ++/* Fuse for Enabling the ARC4 Submodule (1) */ ++#define STATUS_FUSE_DEU_ARC4 (0x1 << 1) ++#define STATUS_FUSE_DEU_ARC4_GET(val) ((((val) & STATUS_FUSE_DEU_ARC4) >> 1) & 0x1) ++/* Fuse for Enabling the DEU Module (0) */ ++#define STATUS_FUSE_DEU_DEU (0x1) ++#define STATUS_FUSE_DEU_DEU_GET(val) ((((val) & STATUS_FUSE_DEU_DEU) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Fuse for CPU Settings ++ ******************************************************************************/ ++ ++/* Fuse for Enabling CPU5 (5) */ ++#define STATUS_FUSE_CPU_CPU5 (0x1 << 5) ++#define STATUS_FUSE_CPU_CPU5_GET(val) ((((val) & STATUS_FUSE_CPU_CPU5) >> 5) & 0x1) ++/* Fuse for Enabling the CPU4 (4) */ ++#define STATUS_FUSE_CPU_CPU4 (0x1 << 4) ++#define STATUS_FUSE_CPU_CPU4_GET(val) ((((val) & STATUS_FUSE_CPU_CPU4) >> 4) & 0x1) ++/* Fuse for Enabling the CPU3 (3) */ ++#define STATUS_FUSE_CPU_CPU3 (0x1 << 3) ++#define STATUS_FUSE_CPU_CPU3_GET(val) ((((val) & STATUS_FUSE_CPU_CPU3) >> 3) & 0x1) ++/* Fuse for Enabling the CPU2 (2) */ ++#define STATUS_FUSE_CPU_CPU2 (0x1 << 2) ++#define STATUS_FUSE_CPU_CPU2_GET(val) ((((val) & STATUS_FUSE_CPU_CPU2) >> 2) & 0x1) ++/* Fuse for Enabling the CPU1 (1) */ ++#define STATUS_FUSE_CPU_CPU1 (0x1 << 1) ++#define STATUS_FUSE_CPU_CPU1_GET(val) ((((val) & STATUS_FUSE_CPU_CPU1) >> 1) & 0x1) ++/* Fuse for Enabling the CPU0 (0) */ ++#define STATUS_FUSE_CPU_CPU0 (0x1) ++#define STATUS_FUSE_CPU_CPU0_GET(val) ((((val) & STATUS_FUSE_CPU_CPU0) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Fuse for PLL Settings ++ ******************************************************************************/ ++ ++/* Fuse for Enabling PLL (7:0) */ ++#define STATUS_FUSE_PLL_PLL (0xff) ++#define STATUS_FUSE_PLL_PLL_GET(val) ((((val) & STATUS_FUSE_PLL_PLL) >> 0) & 0xff) ++ ++/******************************************************************************* ++ * Chip Identification Register ++ ******************************************************************************/ ++ ++/* Chip Version Number (31:28) */ ++#define STATUS_CHIPID_VERSION (0xf << 28) ++#define STATUS_CHIPID_VERSION_GET(val) ((((val) & STATUS_CHIPID_VERSION) >> 28) & 0xf) ++/* Part Number (27:12) */ ++#define STATUS_CHIPID_PART_NUMBER (0xffff << 12) ++#define STATUS_CHIPID_PART_NUMBER_GET(val) ((((val) & STATUS_CHIPID_PART_NUMBER) >> 12) & 0xffff) ++/* Manufacturer ID (11:1) */ ++#define STATUS_CHIPID_MANID (0x7ff << 1) ++#define STATUS_CHIPID_MANID_GET(val) ((((val) & STATUS_CHIPID_MANID) >> 1) & 0x7ff) ++ ++/******************************************************************************* ++ * Chip Configuration Register ++ ******************************************************************************/ ++ ++/* Number of Analog Channels (8:5) */ ++#define STATUS_CONFIG_ANA_CHAN (0xf << 5) ++#define STATUS_CONFIG_ANA_CHAN_GET(val) ((((val) & STATUS_CONFIG_ANA_CHAN) >> 5) & 0xf) ++/* Clock Mode (4) */ ++#define STATUS_CONFIG_CLK_MODE (0x1 << 1) ++#define STATUS_CONFIG_CLK_MODE_GET(val) ((((val) & STATUS_CONFIG_CLK_MODE) >> 4) & 0x1) ++/* Subversion Number (3:0) */ ++#define STATUS_CONFIG_SUB_VERS (0xF) ++#define STATUS_CONFIG_SUB_VERS_GET(val) ((((val) & STATUS_SUBVER_SUB_VERS) >> 0) & 0xF) ++ ++/******************************************************************************* ++ * Chip Location Register ++ ******************************************************************************/ ++ ++/* Chip Lot ID (31:16) */ ++#define STATUS_CHIP_LOC_CHIP_LOT (0xffff << 16) ++#define STATUS_CHIP_LOC_CHIP_LOT_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_LOT) >> 16) & 0xffff) ++/* Chip X Coordinate (15:8) */ ++#define STATUS_CHIP_LOC_CHIP_X (0xff << 8) ++#define STATUS_CHIP_LOC_CHIP_X_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_X) >> 8) & 0xff) ++/* Chip Y Coordinate (7:0) */ ++#define STATUS_CHIP_LOC_CHIP_Y (0xff) ++#define STATUS_CHIP_LOC_CHIP_Y_GET(val) ((((val) & STATUS_CHIP_LOC_CHIP_Y) >> 0) & 0xff) ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/boot_reg.h 2012-07-31 15:46:02.476476158 +0200 +@@ -0,0 +1,37 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++******************************************************************************/ ++ ++#ifndef __BOOT_REG_H ++#define __BOOT_REG_H ++ ++#define LTQ_BOOT_CPU_OFFSET 0x20 ++ ++#define LTQ_BOOT_RVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x00) ++#define LTQ_BOOT_NVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x04) ++#define LTQ_BOOT_EVEC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x08) ++#define LTQ_BOOT_CP0_STATUS(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x0C) ++#define LTQ_BOOT_CP0_EPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x10) ++#define LTQ_BOOT_CP0_EEPC(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x14) ++#define LTQ_BOOT_SIZE(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP1 */ ++#define LTQ_BOOT_RCU_SR(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x18) /* only for CP0 */ ++#define LTQ_BOOT_CFG_STAT(cpu) (volatile u32*)(LTQ_L2_SPRAM_BASE + \ ++ (cpu * LTQ_BOOT_CPU_OFFSET) + 0x1C) ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys0_reg.h 2012-07-31 15:46:02.480476158 +0200 +@@ -0,0 +1,165 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __SYS0_REG_H ++#define __SYS0_REG_H ++ ++#define sys0_r32(reg) ltq_r32(&sys0->reg) ++#define sys0_w32(val, reg) ltq_w32(val, &sys0->reg) ++#define sys0_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys0->reg) ++ ++/** SYS0 register structure */ ++struct svip_reg_sys0 { ++ unsigned long sr; /* 0x0000 */ ++ unsigned long bcr; /* 0x0004 */ ++ unsigned long pll1cr; /* 0x0008 */ ++ unsigned long pll2cr; /* 0x000c */ ++ unsigned long tscr; /* 0x0010 */ ++ unsigned long phyclkr; /* 0x0014 */ ++}; ++ ++/******************************************************************************* ++ * SYS0 Status Register ++ ******************************************************************************/ ++ ++/* Endian select pin (31) */ ++#define SYS0_SR_ESEL (0x1 << 31) ++#define SYS0_SR_ESEL_GET(val) ((((val) & SYS0_SR_ESEL) >> 31) & 0x1) ++/* Boot mode pins (27:24) */ ++#define SYS0_SR_BMODE (0xf << 24) ++#define SYS0_SR_BMODE_GET(val) ((((val) & SYS0_SR_BMODE) >> 24) & 0xf) ++/* PLL2 Lock (18) */ ++#define SYS0_SR_PLL2LOCK (0x1 << 18) ++#define SYS0_SR_PLL2LOCK_GET(val) ((((val) & SYS0_SR_PLL2LOCK) >> 18) & 0x1) ++/* PLL1 Lock (17) */ ++#define SYS0_SR_PLL1LOCK (0x1 << 17) ++#define SYS0_SR_PLL1LOCK_GET(val) ((((val) & SYS0_SR_PLL1LOCK) >> 17) & 0x1) ++/* Discrete Timing Oscillator Lock (16) */ ++#define SYS0_SR_DTOLOCK (0x1 << 16) ++#define SYS0_SR_DTOLOCK_GET(val) ((((val) & SYS0_SR_DTOLOCK) >> 16) & 0x1) ++/* Hardware Reset Indication (1) */ ++#define SYS0_SR_HRSTIN (0x1 << 1) ++#define SYS0_SR_HRSTIN_VAL(val) (((val) & 0x1) << 1) ++#define SYS0_SR_HRSTIN_GET(val) ((((val) & SYS0_SR_HRSTIN) >> 1) & 0x1) ++#define SYS0_SR_HRSTIN_SET(reg,val) (reg) = ((reg & ~SYS0_SR_HRSTIN) | (((val) & 0x1) << 1)) ++/* Power-on Reset Indication (0) */ ++#define SYS0_SR_POR (0x1 << 0) ++#define SYS0_SR_POR_VAL(val) (((val) & 0x1) << 0) ++#define SYS0_SR_POR_GET(val) ((((val) & SYS0_SR_POR) >> 0) & 0x1) ++#define SYS0_SR_POR_SET(reg,val) (reg) = ((reg & ~SYS0_SR_POR) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * SYS0 Boot Control Register ++ ******************************************************************************/ ++ ++/* Configuration of Boot Source for CPU5 (25) */ ++#define SYS0_BCR_BMODECPU5 (0x1 << 25) ++#define SYS0_BCR_BMODECPU5_VAL(val) (((val) & 0x1) << 25) ++#define SYS0_BCR_BMODECPU5_GET(val) ((((val) & SYS0_BCR_BMODECPU5) >> 25) & 0x1) ++#define SYS0_BCR_BMODECPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU5) | (((val) & 0x1) << 25)) ++/* Configuration of Boot Source for CPU4 (24) */ ++#define SYS0_BCR_BMODECPU4 (0x1 << 24) ++#define SYS0_BCR_BMODECPU4_VAL(val) (((val) & 0x1) << 24) ++#define SYS0_BCR_BMODECPU4_GET(val) ((((val) & SYS0_BCR_BMODECPU4) >> 24) & 0x1) ++#define SYS0_BCR_BMODECPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU4) | (((val) & 0x1) << 24)) ++/* Configuration of Boot Source for CPU3 (23) */ ++#define SYS0_BCR_BMODECPU3 (0x1 << 23) ++#define SYS0_BCR_BMODECPU3_VAL(val) (((val) & 0x1) << 23) ++#define SYS0_BCR_BMODECPU3_GET(val) ((((val) & SYS0_BCR_BMODECPU3) >> 23) & 0x1) ++#define SYS0_BCR_BMODECPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU3) | (((val) & 0x1) << 23)) ++/* Configuration of Boot Source for CPU2 (22) */ ++#define SYS0_BCR_BMODECPU2 (0x1 << 22) ++#define SYS0_BCR_BMODECPU2_VAL(val) (((val) & 0x1) << 22) ++#define SYS0_BCR_BMODECPU2_GET(val) ((((val) & SYS0_BCR_BMODECPU2) >> 22) & 0x1) ++#define SYS0_BCR_BMODECPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU2) | (((val) & 0x1) << 22)) ++/* Configuration of Boot Source for CPU1 (21) */ ++#define SYS0_BCR_BMODECPU1 (0x1 << 21) ++#define SYS0_BCR_BMODECPU1_VAL(val) (((val) & 0x1) << 21) ++#define SYS0_BCR_BMODECPU1_GET(val) ((((val) & SYS0_BCR_BMODECPU1) >> 21) & 0x1) ++#define SYS0_BCR_BMODECPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU1) | (((val) & 0x1) << 21)) ++/* Configuration of Boot Source for CPU0 (20:16) */ ++#define SYS0_BCR_BMODECPU0 (0x1f << 16) ++#define SYS0_BCR_BMODECPU0_VAL(val) (((val) & 0x1f) << 16) ++#define SYS0_BCR_BMODECPU0_GET(val) ((((val) & SYS0_BCR_BMODECPU0) >> 16) & 0x1f) ++#define SYS0_BCR_BMODECPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_BMODECPU0) | (((val) & 0x1f) << 16)) ++/* Configuration of Endianess for CPU5 (5) */ ++#define SYS0_BCR_ESELCPU5 (0x1 << 5) ++#define SYS0_BCR_ESELCPU5_VAL(val) (((val) & 0x1) << 5) ++#define SYS0_BCR_ESELCPU5_GET(val) ((((val) & SYS0_BCR_ESELCPU5) >> 5) & 0x1) ++#define SYS0_BCR_ESELCPU5_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU5) | (((val) & 0x1) << 5)) ++/* Configuration of Endianess for CPU4 (4) */ ++#define SYS0_BCR_ESELCPU4 (0x1 << 4) ++#define SYS0_BCR_ESELCPU4_VAL(val) (((val) & 0x1) << 4) ++#define SYS0_BCR_ESELCPU4_GET(val) ((((val) & SYS0_BCR_ESELCPU4) >> 4) & 0x1) ++#define SYS0_BCR_ESELCPU4_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU4) | (((val) & 0x1) << 4)) ++/* Configuration of Endianess for CPU3 (3) */ ++#define SYS0_BCR_ESELCPU3 (0x1 << 3) ++#define SYS0_BCR_ESELCPU3_VAL(val) (((val) & 0x1) << 3) ++#define SYS0_BCR_ESELCPU3_GET(val) ((((val) & SYS0_BCR_ESELCPU3) >> 3) & 0x1) ++#define SYS0_BCR_ESELCPU3_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU3) | (((val) & 0x1) << 3)) ++/* Configuration of Endianess for CPU2 (2) */ ++#define SYS0_BCR_ESELCPU2 (0x1 << 2) ++#define SYS0_BCR_ESELCPU2_VAL(val) (((val) & 0x1) << 2) ++#define SYS0_BCR_ESELCPU2_GET(val) ((((val) & SYS0_BCR_ESELCPU2) >> 2) & 0x1) ++#define SYS0_BCR_ESELCPU2_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU2) | (((val) & 0x1) << 2)) ++/* Configuration of Endianess for CPU1 (1) */ ++#define SYS0_BCR_ESELCPU1 (0x1 << 1) ++#define SYS0_BCR_ESELCPU1_VAL(val) (((val) & 0x1) << 1) ++#define SYS0_BCR_ESELCPU1_GET(val) ((((val) & SYS0_BCR_ESELCPU1) >> 1) & 0x1) ++#define SYS0_BCR_ESELCPU1_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU1) | (((val) & 0x1) << 1)) ++/* Configuration of Endianess for CPU0 (0) */ ++#define SYS0_BCR_ESELCPU0 (0x1) ++#define SYS0_BCR_ESELCPU0_VAL(val) (((val) & 0x1) << 0) ++#define SYS0_BCR_ESELCPU0_GET(val) ((((val) & SYS0_BCR_ESELCPU0) >> 0) & 0x1) ++#define SYS0_BCR_ESELCPU0_SET(reg,val) (reg) = ((reg & ~SYS0_BCR_ESELCPU0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * PLL1 Control Register ++ ******************************************************************************/ ++ ++/* PLL1 Bypass Enable (31) */ ++#define SYS0_PLL1CR_OSCBYP (0x1 << 31) ++#define SYS0_PLL1CR_OSCBYP_VAL(val) (((val) & 0x1) << 31) ++#define SYS0_PLL1CR_OSCBYP_GET(val) ((((val) & SYS0_PLL1CR_OSCBYP) >> 31) & 0x1) ++#define SYS0_PLL1CR_OSCBYP_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_OSCBYP) | (((val) & 0x1) << 31)) ++/* PLL1 Divider Value (1:0) */ ++#define SYS0_PLL1CR_PLLDIV (0x3) ++#define SYS0_PLL1CR_PLLDIV_VAL(val) (((val) & 0x3) << 0) ++#define SYS0_PLL1CR_PLLDIV_GET(val) ((((val) & SYS0_PLL1CR_PLLDIV) >> 0) & 0x3) ++#define SYS0_PLL1CR_PLLDIV_SET(reg,val) (reg) = ((reg & ~SYS0_PLL1CR_PLLDIV) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * PLL2 Control Register ++ ******************************************************************************/ ++ ++/* PLL2 clear deepsleep (31) */ ++#define SYS0_PLL2CR_CLRDS (0x1 << 31) ++#define SYS0_PLL2CR_CLRDS_VAL(val) (((val) & 0x1) << 31) ++#define SYS0_PLL2CR_CLRDS_GET(val) ((((val) & SYS0_PLL2CR_CLRDS) >> 31) & 0x1) ++#define SYS0_PLL2CR_CLRDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_CLRDS) | (((val) & 0x1) << 31)) ++/* PLL2 set deepsleep (30) */ ++#define SYS0_PLL2CR_SETDS (0x1 << 30) ++#define SYS0_PLL2CR_SETDS_VAL(val) (((val) & 0x1) << 30) ++#define SYS0_PLL2CR_SETDS_GET(val) ((((val) & SYS0_PLL2CR_SETDS) >> 30) & 0x1) ++#define SYS0_PLL2CR_SETDS_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_SETDS) | (((val) & 0x1) << 30)) ++/* PLL2 Fractional division enable (16) */ ++#define SYS0_PLL2CR_FRACTEN (0x1 << 16) ++#define SYS0_PLL2CR_FRACTEN_VAL(val) (((val) & 0x1) << 16) ++#define SYS0_PLL2CR_FRACTEN_GET(val) ((((val) & SYS0_PLL2CR_FRACTEN) >> 16) & 0x1) ++#define SYS0_PLL2CR_FRACTEN_SET(reg,val) (reg) = ((reg & ~SYS0_PLL2CR_FRACTEN) | (((val) & 0x1) << 16)) ++/* PLL2 Fractional division value (9:0) */ ++#define SYS0_FRACTVAL (0x3f) ++#define SYS0_FRACTVAL_VAL(val) (((val) & 0x3f) << 0) ++#define SYS0_FRACTVAL_GET(val) ((((val) & SYS0_FRACTVAL) >> 0) & 0x3f) ++#define SYS0_FRACTVAL_SET(reg,val) (reg) = ((reg & ~SYS0_FRACTVAL) | (((val) & 0x3f) << 0)) ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/dma_reg.h 2012-07-31 15:46:02.480476158 +0200 +@@ -0,0 +1,308 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __DMA_REG_H ++#define __DMA_REG_H ++ ++#define dma_r32(reg) ltq_r32(&dma->reg) ++#define dma_w32(val, reg) ltq_w32(val, &dma->reg) ++#define dma_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &dma->reg) ++ ++/** DMA register structure */ ++struct svip_reg_dma { ++ volatile unsigned long clc; /* 0x00 */ ++ volatile unsigned long reserved0; /* 0x04 */ ++ volatile unsigned long id; /* 0x08 */ ++ volatile unsigned long reserved1; /* 0x0c */ ++ volatile unsigned long ctrl; /* 0x10 */ ++ volatile unsigned long cpoll; /* 0x14 */ ++ volatile unsigned long cs; /* 0x18 */ ++ volatile unsigned long cctrl; /* 0x1C */ ++ volatile unsigned long cdba; /* 0x20 */ ++ volatile unsigned long cdlen; /* 0x24 */ ++ volatile unsigned long cis; /* 0x28 */ ++ volatile unsigned long cie; /* 0x2C */ ++ volatile unsigned long cgbl; /* 0x30 */ ++ volatile unsigned long reserved2[3]; /* 0x34 */ ++ volatile unsigned long ps; /* 0x40 */ ++ volatile unsigned long pctrl; /* 0x44 */ ++ volatile unsigned long reserved3[43]; /* 0x48 */ ++ volatile unsigned long irnen; /* 0xF4 */ ++ volatile unsigned long irncr; /* 0xF8 */ ++ volatile unsigned long irnicr; /* 0xFC */ ++}; ++ ++/******************************************************************************* ++ * CLC Register ++ ******************************************************************************/ ++ ++/* Fast Shut-Off Enable Bit (5) */ ++#define DMA_CLC_FSOE (0x1 << 5) ++#define DMA_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) ++#define DMA_CLC_FSOE_GET(val) ((((val) & DMA_CLC_FSOE) >> 5) & 0x1) ++#define DMA_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~DMA_CLC_FSOE) | (((val) & 0x1) << 5)) ++/* Suspend Bit Write Enable for OCDS (4) */ ++#define DMA_CLC_SBWE (0x1 << 4) ++#define DMA_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) ++#define DMA_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~DMA_CLC_SBWE) | (val) & 1) << 4) ++/* External Request Disable (3) */ ++#define DMA_CLC_EDIS (0x1 << 3) ++#define DMA_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) ++#define DMA_CLC_EDIS_GET(val) ((((val) & DMA_CLC_EDIS) >> 3) & 0x1) ++#define DMA_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~DMA_CLC_EDIS) | (((val) & 0x1) << 3)) ++/* Suspend Enable Bit for OCDS (2) */ ++#define DMA_CLC_SPEN (0x1 << 2) ++#define DMA_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) ++#define DMA_CLC_SPEN_GET(val) ((((val) & DMA_CLC_SPEN) >> 2) & 0x1) ++#define DMA_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~DMA_CLC_SPEN) | (((val) & 0x1) << 2)) ++/* Disable Status Bit (1) */ ++#define DMA_CLC_DISS (0x1 << 1) ++#define DMA_CLC_DISS_GET(val) ((((val) & DMA_CLC_DISS) >> 1) & 0x1) ++/* Disable Request Bit (0) */ ++#define DMA_CLC_DISR (0x1) ++#define DMA_CLC_DISR_VAL(val) (((val) & 0x1) << 0) ++#define DMA_CLC_DISR_GET(val) ((((val) & DMA_CLC_DISR) >> 0) & 0x1) ++#define DMA_CLC_DISR_SET(reg,val) (reg) = ((reg & ~DMA_CLC_DISR) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * ID Register ++ ******************************************************************************/ ++ ++/* Number of Channels (25:20) */ ++#define DMA_ID_CHNR (0x3f << 20) ++#define DMA_ID_CHNR_GET(val) ((((val) & DMA_ID_CHNR) >> 20) & 0x3f) ++/* Number of Ports (19:16) */ ++#define DMA_ID_PRTNR (0xf << 16) ++#define DMA_ID_PRTNR_GET(val) ((((val) & DMA_ID_PRTNR) >> 16) & 0xf) ++/* Module ID (15:8) */ ++#define DMA_ID_ID (0xff << 8) ++#define DMA_ID_ID_GET(val) ((((val) & DMA_ID_ID) >> 8) & 0xff) ++/* Revision (4:0) */ ++#define DMA_ID_REV (0x1f) ++#define DMA_ID_REV_GET(val) ((((val) & DMA_ID_REV) >> 0) & 0x1f) ++ ++/******************************************************************************* ++ * Control Register ++ ******************************************************************************/ ++ ++/* Global Software Reset (0) */ ++#define DMA_CTRL_RST (0x1) ++#define DMA_CTRL_RST_GET(val) ((((val) & DMA_CTRL_RST) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Channel Polling Register ++ ******************************************************************************/ ++ ++/* Enable (31) */ ++#define DMA_CPOLL_EN (0x1 << 31) ++#define DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) ++#define DMA_CPOLL_EN_GET(val) ((((val) & DMA_CPOLL_EN) >> 31) & 0x1) ++#define DMA_CPOLL_EN_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_EN) | (((val) & 0x1) << 31)) ++/* Counter (15:4) */ ++#define DMA_CPOLL_CNT (0xfff << 4) ++#define DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) ++#define DMA_CPOLL_CNT_GET(val) ((((val) & DMA_CPOLL_CNT) >> 4) & 0xfff) ++#define DMA_CPOLL_CNT_SET(reg,val) (reg) = ((reg & ~DMA_CPOLL_CNT) | (((val) & 0xfff) << 4)) ++ ++/******************************************************************************* ++ * Global Buffer Length Register ++ ******************************************************************************/ ++ ++/* Global Buffer Length (15:0) */ ++#define DMA_CGBL_GBL (0xffff) ++#define DMA_CGBL_GBL_VAL(val) (((val) & 0xffff) << 0) ++#define DMA_CGBL_GBL_GET(val) ((((val) & DMA_CGBL_GBL) >> 0) & 0xffff) ++#define DMA_CGBL_GBL_SET(reg,val) (reg) = ((reg & ~DMA_CGBL_GBL) | (((val) & 0xffff) << 0)) ++ ++/******************************************************************************* ++ * Channel Select Register ++ ******************************************************************************/ ++ ++/* Channel Selection (4:0) */ ++#define DMA_CS_CS (0x1f) ++#define DMA_CS_CS_VAL(val) (((val) & 0x1f) << 0) ++#define DMA_CS_CS_GET(val) ((((val) & DMA_CS_CS) >> 0) & 0x1f) ++#define DMA_CS_CS_SET(reg,val) (reg) = ((reg & ~DMA_CS_CS) | (((val) & 0x1f) << 0)) ++ ++/******************************************************************************* ++ * Channel Control Register ++ ******************************************************************************/ ++ ++/* Peripheral to Peripheral Copy (24) */ ++#define DMA_CCTRL_P2PCPY (0x1 << 24) ++#define DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) ++#define DMA_CCTRL_P2PCPY_GET(val) ((((val) & DMA_CCTRL_P2PCPY) >> 24) & 0x1) ++#define DMA_CCTRL_P2PCPY_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_P2PCPY) | (((val) & 0x1) << 24)) ++/* Channel Weight for Transmit Direction (17:16) */ ++#define DMA_CCTRL_TXWGT (0x3 << 16) ++#define DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) ++#define DMA_CCTRL_TXWGT_GET(val) ((((val) & DMA_CCTRL_TXWGT) >> 16) & 0x3) ++#define DMA_CCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_TXWGT) | (((val) & 0x3) << 16)) ++/* Port Assignment (13:11) */ ++#define DMA_CCTRL_PRTNR (0x7 << 11) ++#define DMA_CCTRL_PRTNR_GET(val) ((((val) & DMA_CCTRL_PRTNR) >> 11) & 0x7) ++/* Class (10:9) */ ++#define DMA_CCTRL_CLASS (0x3 << 9) ++#define DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) ++#define DMA_CCTRL_CLASS_GET(val) ((((val) & DMA_CCTRL_CLASS) >> 9) & 0x3) ++#define DMA_CCTRL_CLASS_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_CLASS) | (((val) & 0x3) << 9)) ++/* Direction (8) */ ++#define DMA_CCTRL_DIR (0x1 << 8) ++#define DMA_CCTRL_DIR_GET(val) ((((val) & DMA_CCTRL_DIR) >> 8) & 0x1) ++/* Reset (1) */ ++#define DMA_CCTRL_RST (0x1 << 1) ++#define DMA_CCTRL_RST_VAL(val) (((val) & 0x1) << 1) ++#define DMA_CCTRL_RST_GET(val) ((((val) & DMA_CCTRL_RST) >> 1) & 0x1) ++#define DMA_CCTRL_RST_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_RST) | (((val) & 0x1) << 1)) ++/* Channel On or Off (0) */ ++#define DMA_CCTRL_ON_OFF (0x1) ++#define DMA_CCTRL_ON_OFF_VAL(val) (((val) & 0x1) << 0) ++#define DMA_CCTRL_ON_OFF_GET(val) ((((val) & DMA_CCTRL_ON_OFF) >> 0) & 0x1) ++#define DMA_CCTRL_ON_OFF_SET(reg,val) (reg) = ((reg & ~DMA_CCTRL_ON_OFF) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Channel Descriptor Base Address Register ++ ******************************************************************************/ ++ ++/* Channel Descriptor Base Address (29:3) */ ++#define DMA_CDBA_CDBA (0x7ffffff << 3) ++#define DMA_CDBA_CDBA_VAL(val) (((val) & 0x7ffffff) << 3) ++#define DMA_CDBA_CDBA_GET(val) ((((val) & DMA_CDBA_CDBA) >> 3) & 0x7ffffff) ++#define DMA_CDBA_CDBA_SET(reg,val) (reg) = ((reg & ~DMA_CDBA_CDBA) | (((val) & 0x7ffffff) << 3)) ++ ++/******************************************************************************* ++ * Channel Descriptor Length Register ++ ******************************************************************************/ ++ ++/* Channel Descriptor Length (7:0) */ ++#define DMA_CDLEN_CDLEN (0xff) ++#define DMA_CDLEN_CDLEN_VAL(val) (((val) & 0xff) << 0) ++#define DMA_CDLEN_CDLEN_GET(val) ((((val) & DMA_CDLEN_CDLEN) >> 0) & 0xff) ++#define DMA_CDLEN_CDLEN_SET(reg,val) (reg) = ((reg & ~DMA_CDLEN_CDLEN) | (((val) & 0xff) << 0)) ++ ++/******************************************************************************* ++ * Channel Interrupt Status Register ++ ******************************************************************************/ ++ ++/* SAI Read Error Interrupt (5) */ ++#define DMA_CIS_RDERR (0x1 << 5) ++#define DMA_CIS_RDERR_GET(val) ((((val) & DMA_CIS_RDERR) >> 5) & 0x1) ++/* Channel Off Interrupt (4) */ ++#define DMA_CIS_CHOFF (0x1 << 4) ++#define DMA_CIS_CHOFF_GET(val) ((((val) & DMA_CIS_CHOFF) >> 4) & 0x1) ++/* Descriptor Complete Interrupt (3) */ ++#define DMA_CIS_DESCPT (0x1 << 3) ++#define DMA_CIS_DESCPT_GET(val) ((((val) & DMA_CIS_DESCPT) >> 3) & 0x1) ++/* Descriptor Under-Run Interrupt (2) */ ++#define DMA_CIS_DUR (0x1 << 2) ++#define DMA_CIS_DUR_GET(val) ((((val) & DMA_CIS_DUR) >> 2) & 0x1) ++/* End of Packet Interrupt (1) */ ++#define DMA_CIS_EOP (0x1 << 1) ++#define DMA_CIS_EOP_GET(val) ((((val) & DMA_CIS_EOP) >> 1) & 0x1) ++ ++/******************************************************************************* ++ * Channel Interrupt Enable Register ++ ******************************************************************************/ ++ ++/* SAI Read Error Interrupt (5) */ ++#define DMA_CIE_RDERR (0x1 << 5) ++#define DMA_CIE_RDERR_GET(val) ((((val) & DMA_CIE_RDERR) >> 5) & 0x1) ++/* Channel Off Interrupt (4) */ ++#define DMA_CIE_CHOFF (0x1 << 4) ++#define DMA_CIE_CHOFF_GET(val) ((((val) & DMA_CIE_CHOFF) >> 4) & 0x1) ++/* Descriptor Complete Interrupt Enable (3) */ ++#define DMA_CIE_DESCPT (0x1 << 3) ++#define DMA_CIE_DESCPT_GET(val) ((((val) & DMA_CIE_DESCPT) >> 3) & 0x1) ++/* Descriptor Under Run Interrupt Enable (2) */ ++#define DMA_CIE_DUR (0x1 << 2) ++#define DMA_CIE_DUR_GET(val) ((((val) & DMA_CIE_DUR) >> 2) & 0x1) ++/* End of Packet Interrupt Enable (1) */ ++#define DMA_CIE_EOP (0x1 << 1) ++#define DMA_CIE_EOP_GET(val) ((((val) & DMA_CIE_EOP) >> 1) & 0x1) ++ ++/******************************************************************************* ++ * Port Select Register ++ ******************************************************************************/ ++ ++/* Port Selection (2:0) */ ++#define DMA_PS_PS (0x7) ++#define DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) ++#define DMA_PS_PS_GET(val) ((((val) & DMA_PS_PS) >> 0) & 0x7) ++#define DMA_PS_PS_SET(reg,val) (reg) = ((reg & ~DMA_PS_PS) | (((val) & 0x7) << 0)) ++ ++/******************************************************************************* ++ * Port Control Register ++ ******************************************************************************/ ++ ++/* General Purpose Control (16) */ ++#define DMA_PCTRL_GPC (0x1 << 16) ++#define DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) ++#define DMA_PCTRL_GPC_GET(val) ((((val) & DMA_PCTRL_GPC) >> 16) & 0x1) ++#define DMA_PCTRL_GPC_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_GPC) | (((val) & 0x1) << 16)) ++/* Port Weight for Transmit Direction (14:12) */ ++#define DMA_PCTRL_TXWGT (0x7 << 12) ++#define DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) ++#define DMA_PCTRL_TXWGT_GET(val) ((((val) & DMA_PCTRL_TXWGT) >> 12) & 0x7) ++#define DMA_PCTRL_TXWGT_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXWGT) | (((val) & 0x7) << 12)) ++/* Endianness for Transmit Direction (11:10) */ ++#define DMA_PCTRL_TXENDI (0x3 << 10) ++#define DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) ++#define DMA_PCTRL_TXENDI_GET(val) ((((val) & DMA_PCTRL_TXENDI) >> 10) & 0x3) ++#define DMA_PCTRL_TXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXENDI) | (((val) & 0x3) << 10)) ++/* Endianness for Receive Direction (9:8) */ ++#define DMA_PCTRL_RXENDI (0x3 << 8) ++#define DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) ++#define DMA_PCTRL_RXENDI_GET(val) ((((val) & DMA_PCTRL_RXENDI) >> 8) & 0x3) ++#define DMA_PCTRL_RXENDI_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXENDI) | (((val) & 0x3) << 8)) ++/* Packet Drop Enable (6) */ ++#define DMA_PCTRL_PDEN (0x1 << 6) ++#define DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) ++#define DMA_PCTRL_PDEN_GET(val) ((((val) & DMA_PCTRL_PDEN) >> 6) & 0x1) ++#define DMA_PCTRL_PDEN_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_PDEN) | (((val) & 0x1) << 6)) ++/* Burst Length for Transmit Direction (5:4) */ ++#define DMA_PCTRL_TXBL (0x3 << 4) ++#define DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) ++#define DMA_PCTRL_TXBL_GET(val) ((((val) & DMA_PCTRL_TXBL) >> 4) & 0x3) ++#define DMA_PCTRL_TXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_TXBL) | (((val) & 0x3) << 4)) ++/* Burst Length for Receive Direction (3:2) */ ++#define DMA_PCTRL_RXBL (0x3 << 2) ++#define DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) ++#define DMA_PCTRL_RXBL_GET(val) ((((val) & DMA_PCTRL_RXBL) >> 2) & 0x3) ++#define DMA_PCTRL_RXBL_SET(reg,val) (reg) = ((reg & ~DMA_PCTRL_RXBL) | (((val) & 0x3) << 2)) ++ ++/******************************************************************************* ++ * DMA_IRNEN Register ++ ******************************************************************************/ ++ ++/* Channel x Interrupt Request Enable (23) */ ++#define DMA_IRNEN_CH23 (0x1 << 23) ++#define DMA_IRNEN_CH23_VAL(val) (((val) & 0x1) << 23) ++#define DMA_IRNEN_CH23_GET(val) ((((val) & DMA_IRNEN_CH23) >> 23) & 0x1) ++#define DMA_IRNEN_CH23_SET(reg,val) (reg) = ((reg & ~DMA_IRNEN_CH23) | (((val) & 0x1) << 23)) ++ ++/******************************************************************************* ++ * DMA_IRNCR Register ++ ******************************************************************************/ ++ ++/* Channel x Interrupt (23) */ ++#define DMA_IRNCR_CH23 (0x1 << 23) ++#define DMA_IRNCR_CH23_GET(val) ((((val) & DMA_IRNCR_CH23) >> 23) & 0x1) ++ ++/******************************************************************************* ++ * DMA_IRNICR Register ++ ******************************************************************************/ ++ ++/* Channel x Interrupt Request (23) */ ++#define DMA_IRNICR_CH23 (0x1 << 23) ++#define DMA_IRNICR_CH23_GET(val) ((((val) & DMA_IRNICR_CH23) >> 23) & 0x1) ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_dma.h 2012-07-31 15:46:02.480476158 +0200 +@@ -0,0 +1,245 @@ ++/************************************************************************ ++ * ++ * Copyright (c) 2007 ++ * Infineon Technologies AG ++ * St. Martin Strasse 53; 81669 Muenchen; Germany ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ ************************************************************************/ ++ ++#ifndef __SVIP_DMA_H ++#define __SVIP_DMA_H ++ ++#define LTQ_DMA_CH_ON 1 ++#define LTQ_DMA_CH_OFF 0 ++#define LTQ_DMA_CH_DEFAULT_WEIGHT 100; ++ ++#define DMA_OWN 1 ++#define CPU_OWN 0 ++#define DMA_MAJOR 250 ++ ++/* Descriptors */ ++#define DMA_DESC_OWN_CPU 0x0 ++#define DMA_DESC_OWN_DMA 0x80000000 ++#define DMA_DESC_CPT_SET 0x40000000 ++#define DMA_DESC_SOP_SET 0x20000000 ++#define DMA_DESC_EOP_SET 0x10000000 ++ ++struct rx_desc { ++ union { ++ struct { ++#ifdef CONFIG_CPU_LITTLE_ENDIAN ++ volatile u32 data_length:16; ++ volatile u32 reserve2:7; ++ volatile u32 byte_offset:2; ++ volatile u32 reserve1:3; ++ volatile u32 eop:1; ++ volatile u32 sop:1; ++ volatile u32 c:1; ++ volatile u32 own:1; ++#else ++ volatile u32 own:1; ++ volatile u32 c:1; ++ volatile u32 sop:1; ++ volatile u32 eop:1; ++ volatile u32 reserve1:3; ++ volatile u32 byte_offset:2; ++ volatile u32 reserve2:7; ++ volatile u32 data_length:16; ++#endif ++ } field; ++ ++ volatile u32 word; ++ } status; ++ ++ volatile u32 data_pointer; ++}; ++ ++struct tx_desc { ++ union { ++ struct { ++#ifdef CONFIG_CPU_LITTLE_ENDIAN ++ volatile u32 data_length:16; ++ volatile u32 reserved:7; ++ volatile u32 byte_offset:5; ++ volatile u32 eop:1; ++ volatile u32 sop:1; ++ volatile u32 c:1; ++ volatile u32 own:1; ++#else ++ volatile u32 own:1; ++ volatile u32 c:1; ++ volatile u32 sop:1; ++ volatile u32 eop:1; ++ volatile u32 byte_offset:5; ++ volatile u32 reserved:7; ++ volatile u32 data_length:16; ++#endif ++ } field; ++ ++ volatile u32 word; ++ } status; ++ ++ volatile u32 data_pointer; ++}; ++ ++/* DMA pseudo interrupts notified to switch driver */ ++#define RCV_INT 0x01 ++#define TX_BUF_FULL_INT 0x02 ++#define TRANSMIT_CPT_INT 0x04 ++#define CHANNEL_CLOSED 0x10 ++ ++/* Parameters for switch DMA device */ ++#define DEFAULT_SW_CHANNEL_WEIGHT 3 ++#define DEFAULT_SW_PORT_WEIGHT 7 ++ ++#define DEFAULT_SW_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ ++#define DEFAULT_SW_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ ++ ++#define DEFAULT_SW_TX_CHANNEL_NUM 4 ++#define DEFAULT_SW_RX_CHANNEL_NUM 4 ++ ++#define DEFAULT_SW_TX_CHANNEL_DESCR_NUM 20 ++#define DEFAULT_SW_RX_CHANNEL_DESCR_NUM 20 ++ ++/* Parameters for SSC DMA device */ ++#define DEFAULT_SSC_CHANNEL_WEIGHT 3 ++#define DEFAULT_SSC_PORT_WEIGHT 7 ++ ++#define DEFAULT_SSC_TX_CHANNEL_CLASS 3 ++#define DEFAULT_SSC_RX_CHANNEL_CLASS 0 ++ ++#define DEFAULT_SSC_TX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ ++#define DEFAULT_SSC_RX_BURST_LEN 2 /* 2 words, 4 words, 8 words */ ++ ++#define DEFAULT_SSC0_TX_CHANNEL_NUM 1 ++#define DEFAULT_SSC0_RX_CHANNEL_NUM 1 ++#define DEFAULT_SSC1_TX_CHANNEL_NUM 1 ++#define DEFAULT_SSC1_RX_CHANNEL_NUM 1 ++ ++#define DEFAULT_SSC_TX_CHANNEL_DESCR_NUM 10 ++#define DEFAULT_SSC_RX_CHANNEL_DESCR_NUM 10 ++ ++/* Parameters for memory DMA device */ ++#define DEFAULT_MEM_CHANNEL_WEIGHT 3 ++#define DEFAULT_MEM_PORT_WEIGHT 7 ++ ++#define DEFAULT_MEM_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ ++#define DEFAULT_MEM_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ ++ ++#define DEFAULT_MEM_TX_CHANNEL_NUM 1 ++#define DEFAULT_MEM_RX_CHANNEL_NUM 1 ++ ++#define DEFAULT_MEM_TX_CHANNEL_DESCR_NUM 2 ++#define DEFAULT_MEM_RX_CHANNEL_DESCR_NUM 2 ++ ++/* Parameters for DEU DMA device */ ++#define DEFAULT_DEU_CHANNEL_WEIGHT 1 ++#define DEFAULT_DEU_PORT_WEIGHT 1 ++ ++#define DEFAULT_DEU_TX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ ++#define DEFAULT_DEU_RX_BURST_LEN 4 /* 2 words, 4 words, 8 words */ ++ ++#define DEFAULT_DEU_TX_CHANNEL_DESCR_NUM 20 ++#define DEFAULT_DEU_RX_CHANNEL_DESCR_NUM 20 ++ ++#define DMA_DESCR_NUM 30 /* number of descriptors per channel */ ++ ++enum dma_dir_t { ++ DIR_RX = 0, ++ DIR_TX = 1, ++}; ++ ++struct dma_device_info; ++ ++struct dma_channel_info { ++ /*Pointer to the peripheral device who is using this channel*/ ++ /*const*/ struct dma_device_info *dma_dev; ++ /*direction*/ ++ const enum dma_dir_t dir; /*RX or TX*/ ++ /*class for this channel for QoS*/ ++ int pri; ++ /*irq number*/ ++ const int irq; ++ /*relative channel number*/ ++ const int rel_chan_no; ++ /*absolute channel number*/ ++ int abs_chan_no; ++ ++ /*specify byte_offset*/ ++ int byte_offset; ++ int tx_weight; ++ ++ /*descriptor parameter*/ ++ int desc_base; ++ int desc_len; ++ int curr_desc; ++ int prev_desc;/*only used if it is a tx channel*/ ++ ++ /*weight setting for WFQ algorithm*/ ++ int weight; ++ int default_weight; ++ ++ int packet_size; ++ ++ /*status of this channel*/ ++ int control; /*on or off*/ ++ int xfer_cnt; ++ int dur; /*descriptor underrun*/ ++ ++ /**optional information for the upper layer devices*/ ++ void *opt[DMA_DESCR_NUM]; ++ ++ /*channel operations*/ ++ int (*open)(struct dma_channel_info *ch); ++ int (*close)(struct dma_channel_info *ch); ++ int (*reset)(struct dma_channel_info *ch); ++ void (*enable_irq)(struct dma_channel_info *ch); ++ void (*disable_irq)(struct dma_channel_info *ch); ++}; ++ ++ ++struct dma_device_info { ++ /*device name of this peripheral*/ ++ const char device_name[16]; ++ const int max_rx_chan_num; ++ const int max_tx_chan_num; ++ int drop_enable; ++ ++ int reserved; ++ ++ int tx_burst_len; ++ int rx_burst_len; ++ int tx_weight; ++ ++ int current_tx_chan; ++ int current_rx_chan; ++ int num_tx_chan; ++ int num_rx_chan; ++ int tx_endianness_mode; ++ int rx_endianness_mode; ++ struct dma_channel_info *tx_chan[4]; ++ struct dma_channel_info *rx_chan[4]; ++ ++ /*functions, optional*/ ++ u8 *(*buffer_alloc)(int len,int *offset, void **opt); ++ void (*buffer_free)(u8 *dataptr, void *opt); ++ int (*intr_handler)(struct dma_device_info *dma_dev, int status); ++ ++ /* used by peripheral driver only */ ++ void *priv; ++}; ++ ++struct dma_device_info *dma_device_reserve(char *dev_name); ++int dma_device_release(struct dma_device_info *dma_dev); ++int dma_device_register(struct dma_device_info *dma_dev); ++int dma_device_unregister(struct dma_device_info *dma_dev); ++int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt); ++int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, ++ int len, void *opt); ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/ebu_reg.h 2012-07-31 15:46:02.484476159 +0200 +@@ -0,0 +1,615 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __EBU_REG_H ++#define __EBU_REG_H ++ ++#define ebu_r32(reg) ltq_r32(&ebu->reg) ++#define ebu_w32(val, reg) ltq_w32(val, &ebu->reg) ++#define ebu_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &ebu->reg) ++ ++/** EBU register structure */ ++struct svip_reg_ebu { ++ volatile unsigned long clc; /* 0x0000 */ ++ volatile unsigned long reserved0; /* 0x04 */ ++ volatile unsigned long id; /* 0x0008 */ ++ volatile unsigned long reserved1; /* 0x0c */ ++ volatile unsigned long con; /* 0x0010 */ ++ volatile unsigned long reserved2[3]; /* 0x14 */ ++ volatile unsigned long addr_sel_0; /* 0x0020 */ ++ volatile unsigned long addr_sel_1; /* 0x0024 */ ++ volatile unsigned long addr_sel_2; /* 0x0028 */ ++ volatile unsigned long addr_sel_3; /* 0x002c */ ++ volatile unsigned long reserved3[12]; /* 0x30 */ ++ volatile unsigned long con_0; /* 0x0060 */ ++ volatile unsigned long con_1; /* 0x0064 */ ++ volatile unsigned long con_2; /* 0x0068 */ ++ volatile unsigned long con_3; /* 0x006c */ ++ volatile unsigned long reserved4[4]; /* 0x70 */ ++ volatile unsigned long emu_addr; /* 0x0080 */ ++ volatile unsigned long emu_bc; /* 0x0084 */ ++ volatile unsigned long emu_con; /* 0x0088 */ ++ volatile unsigned long reserved5; /* 0x8c */ ++ volatile unsigned long pcc_con; /* 0x0090 */ ++ volatile unsigned long pcc_stat; /* 0x0094 */ ++ volatile unsigned long reserved6[2]; /* 0x98 */ ++ volatile unsigned long pcc_istat; /* 0x00A0 */ ++ volatile unsigned long pcc_ien; /* 0x00A4 */ ++ volatile unsigned long pcc_int_out; /* 0x00A8 */ ++ volatile unsigned long pcc_irs; /* 0x00AC */ ++ volatile unsigned long nand_con; /* 0x00B0 */ ++ volatile unsigned long nand_wait; /* 0x00B4 */ ++ volatile unsigned long nand_ecc0; /* 0x00B8 */ ++ volatile unsigned long nand_ecc_ac; /* 0x00BC */ ++}; ++ ++/******************************************************************************* ++ * EBU ++ ******************************************************************************/ ++#define LTQ_EBU_CLC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0000)) ++#define LTQ_EBU_ID ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0008)) ++#define LTQ_EBU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0010)) ++#define LTQ_EBU_ADDR_SEL_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0020)) ++#define LTQ_EBU_ADDR_SEL_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0024)) ++#define LTQ_EBU_ADDR_SEL_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0028)) ++#define LTQ_EBU_ADDR_SEL_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x002c)) ++#define LTQ_EBU_CON_0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0060)) ++#define LTQ_EBU_CON_1 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0064)) ++#define LTQ_EBU_CON_2 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0068)) ++#define LTQ_EBU_CON_3 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x006c)) ++#define LTQ_EBU_EMU_BC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0084)) ++#define LTQ_EBU_PCC_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0090)) ++#define LTQ_EBU_PCC_STAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0094)) ++#define LTQ_EBU_PCC_ISTAT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A0)) ++#define LTQ_EBU_PCC_IEN ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A4)) ++#define LTQ_EBU_PCC_INT_OUT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00A8)) ++#define LTQ_EBU_PCC_IRS ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00AC)) ++#define LTQ_EBU_NAND_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B0)) ++#define LTQ_EBU_NAND_WAIT ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B4)) ++#define LTQ_EBU_NAND_ECC0 ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00B8)) ++#define LTQ_EBU_NAND_ECC_AC ((volatile unsigned int*)(LTQ_EBU_BASE + 0x00BC)) ++#define LTQ_EBU_EMU_ADDR ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0080)) ++#define LTQ_EBU_EMU_CON ((volatile unsigned int*)(LTQ_EBU_BASE + 0x0088)) ++ ++/******************************************************************************* ++ * EBU Clock Control Register ++ ******************************************************************************/ ++ ++/* EBU Disable Status Bit (1) */ ++#define LTQ_EBU_CLC_DISS (0x1 << 1) ++#define LTQ_EBU_CLC_DISS_GET(val) ((((val) & LTQ_EBU_CLC_DISS) >> 1) & 0x1) ++/* Used for Enable/disable Control of the EBU (0) */ ++#define LTQ_EBU_CLC_DISR (0x1) ++#define LTQ_EBU_CLC_DISR_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_CLC_DISR_GET(val) ((((val) & LTQ_EBU_CLC_DISR) >> 0) & 0x1) ++#define LTQ_EBU_CLC_DISR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CLC_DISR) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * EBU Identification Register (Internal) ++ ******************************************************************************/ ++ ++/* Module Number (31:8) */ ++#define LTQ_EBU_ID_MODNUM (0xffffff << 8) ++#define LTQ_EBU_ID_MODNUM_GET(val) ((((val) & LTQ_EBU_ID_MODNUM) >> 8) & 0xffffff) ++/* Revision Number (7:0) */ ++#define LTQ_EBU_ID_REVNUM (0xff) ++#define LTQ_EBU_ID_REVNUM_GET(val) ((((val) & LTQ_EBU_ID_REVNUM) >> 0) & 0xff) ++ ++/******************************************************************************* ++ * External Bus Unit Control Register ++ ******************************************************************************/ ++ ++/* Driver Turn-Around Control, Chip Select Triggered (22:20) */ ++#define LTQ_EBU_CON_DTACS (0x7 << 20) ++#define LTQ_EBU_CON_DTACS_VAL(val) (((val) & 0x7) << 20) ++#define LTQ_EBU_CON_DTACS_GET(val) ((((val) & LTQ_EBU_CON_DTACS) >> 20) & 0x7) ++#define LTQ_EBU_CON_DTACS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTACS) | (((val) & 0x7) << 20)) ++/* Driver Turn-Around Control, Read-write Triggered (18:16) */ ++#define LTQ_EBU_CON_DTARW (0x7 << 16) ++#define LTQ_EBU_CON_DTARW_VAL(val) (((val) & 0x7) << 16) ++#define LTQ_EBU_CON_DTARW_GET(val) ((((val) & LTQ_EBU_CON_DTARW) >> 16) & 0x7) ++#define LTQ_EBU_CON_DTARW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_DTARW) | (((val) & 0x7) << 16)) ++/* Time-Out Control (15:8) */ ++#define LTQ_EBU_CON_TOUTC (0xff << 8) ++#define LTQ_EBU_CON_TOUTC_VAL(val) (((val) & 0xff) << 8) ++#define LTQ_EBU_CON_TOUTC_GET(val) ((((val) & LTQ_EBU_CON_TOUTC) >> 8) & 0xff) ++#define LTQ_EBU_CON_TOUTC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_TOUTC) | (((val) & 0xff) << 8)) ++/* Arbitration Mode (7:6) */ ++#define LTQ_EBU_CON_ARBMODE (0x3 << 6) ++#define LTQ_EBU_CON_ARBMODE_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_EBU_CON_ARBMODE_GET(val) ((((val) & LTQ_EBU_CON_ARBMODE) >> 6) & 0x3) ++#define LTQ_EBU_CON_ARBMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBMODE) | (((val) & 0x3) << 6)) ++/* Arbitration Synchronization (5) */ ++#define LTQ_EBU_CON_ARBSYNC (0x1 << 5) ++#define LTQ_EBU_CON_ARBSYNC_VAL(val) (((val) & 0x1) << 5) ++#define LTQ_EBU_CON_ARBSYNC_GET(val) ((((val) & LTQ_EBU_CON_ARBSYNC) >> 5) & 0x1) ++#define LTQ_EBU_CON_ARBSYNC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_ARBSYNC) | (((val) & 0x1) << 5)) ++ ++/******************************************************************************* ++ * Address Select Registers ++ ******************************************************************************/ ++ ++/* Memory Region Base Address (31:12) */ ++#define LTQ_EBU_ADDR_SEL_0_BASE (0xfffff << 12) ++#define LTQ_EBU_ADDR_SEL_0_BASE_VAL(val) (((val) & 0xfffff) << 12) ++#define LTQ_EBU_ADDR_SEL_0_BASE_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_BASE) >> 12) & 0xfffff) ++#define LTQ_EBU_ADDR_SEL_0_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_BASE) | (((val) & 0xfffff) << 12)) ++/* Memory Region Address Mask (7:4) */ ++#define LTQ_EBU_ADDR_SEL_0_MASK (0xf << 4) ++#define LTQ_EBU_ADDR_SEL_0_MASK_VAL(val) (((val) & 0xf) << 4) ++#define LTQ_EBU_ADDR_SEL_0_MASK_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MASK) >> 4) & 0xf) ++#define LTQ_EBU_ADDR_SEL_0_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MASK) | (((val) & 0xf) << 4)) ++/* Memory Region Mirror Enable Control (1) */ ++#define LTQ_EBU_ADDR_SEL_0_MRME (0x1 << 1) ++#define LTQ_EBU_ADDR_SEL_0_MRME_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_EBU_ADDR_SEL_0_MRME_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_MRME) >> 1) & 0x1) ++#define LTQ_EBU_ADDR_SEL_0_MRME_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_MRME) | (((val) & 0x1) << 1)) ++/* Memory Region Enable Control (0) */ ++#define LTQ_EBU_ADDR_SEL_0_REGEN (0x1) ++#define LTQ_EBU_ADDR_SEL_0_REGEN_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_ADDR_SEL_0_REGEN_GET(val) ((((val) & LTQ_EBU_ADDR_SEL_0_REGEN) >> 0) & 0x1) ++#define LTQ_EBU_ADDR_SEL_0_REGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_ADDR_SEL_0_REGEN) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Bus Configuration Registers ++ ******************************************************************************/ ++ ++/* Memory Region Write Protection (31) */ ++#define LTQ_EBU_CON_0_WRDIS (0x1 << 31) ++#define LTQ_EBU_CON_0_WRDIS_VAL(val) (((val) & 0x1) << 31) ++#define LTQ_EBU_CON_0_WRDIS_GET(val) ((((val) & LTQ_EBU_CON_0_WRDIS) >> 31) & 0x1) ++#define LTQ_EBU_CON_0_WRDIS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WRDIS) | (((val) & 0x1) << 31)) ++/* Address Swapping (30) */ ++#define LTQ_EBU_CON_0_ADSWP (0x1 << 30) ++#define LTQ_EBU_CON_0_ADSWP_VAL(val) (((val) & 0x1) << 30) ++#define LTQ_EBU_CON_0_ADSWP_GET(val) ((((val) & LTQ_EBU_CON_0_ADSWP) >> 30) & 0x1) ++#define LTQ_EBU_CON_0_ADSWP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ADSWP) | (((val) & 0x1) << 30)) ++/* Address Generation Control (26:24) */ ++#define LTQ_EBU_CON_0_AGEN (0x7 << 24) ++#define LTQ_EBU_CON_0_AGEN_VAL(val) (((val) & 0x7) << 24) ++#define LTQ_EBU_CON_0_AGEN_GET(val) ((((val) & LTQ_EBU_CON_0_AGEN) >> 24) & 0x7) ++#define LTQ_EBU_CON_0_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_AGEN) | (((val) & 0x7) << 24)) ++/* Extended Address Setup Control (22) */ ++#define LTQ_EBU_CON_0_SETUP (0x1 << 22) ++#define LTQ_EBU_CON_0_SETUP_VAL(val) (((val) & 0x1) << 22) ++#define LTQ_EBU_CON_0_SETUP_GET(val) ((((val) & LTQ_EBU_CON_0_SETUP) >> 22) & 0x1) ++#define LTQ_EBU_CON_0_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_SETUP) | (((val) & 0x1) << 22)) ++/* Variable Wait-State Insertion Control (21:20) */ ++#define LTQ_EBU_CON_0_WAIT (0x3 << 20) ++#define LTQ_EBU_CON_0_WAIT_VAL(val) (((val) & 0x3) << 20) ++#define LTQ_EBU_CON_0_WAIT_GET(val) ((((val) & LTQ_EBU_CON_0_WAIT) >> 20) & 0x3) ++#define LTQ_EBU_CON_0_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAIT) | (((val) & 0x3) << 20)) ++/* Active WAIT Level Control (19) */ ++#define LTQ_EBU_CON_0_WINV (0x1 << 19) ++#define LTQ_EBU_CON_0_WINV_VAL(val) (((val) & 0x1) << 19) ++#define LTQ_EBU_CON_0_WINV_GET(val) ((((val) & LTQ_EBU_CON_0_WINV) >> 19) & 0x1) ++#define LTQ_EBU_CON_0_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WINV) | (((val) & 0x1) << 19)) ++/* External Device Data Width Control (17:16) */ ++#define LTQ_EBU_CON_0_PW (0x3 << 16) ++#define LTQ_EBU_CON_0_PW_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_EBU_CON_0_PW_GET(val) ((((val) & LTQ_EBU_CON_0_PW) >> 16) & 0x3) ++#define LTQ_EBU_CON_0_PW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_PW) | (((val) & 0x3) << 16)) ++/* Address Latch Enable ALE Duration Control (15:14) */ ++#define LTQ_EBU_CON_0_ALEC (0x3 << 14) ++#define LTQ_EBU_CON_0_ALEC_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_EBU_CON_0_ALEC_GET(val) ((((val) & LTQ_EBU_CON_0_ALEC) >> 14) & 0x3) ++#define LTQ_EBU_CON_0_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_ALEC) | (((val) & 0x3) << 14)) ++/* Byte Control Signal Timing Mode Control (13:12) */ ++#define LTQ_EBU_CON_0_BCGEN (0x3 << 12) ++#define LTQ_EBU_CON_0_BCGEN_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_EBU_CON_0_BCGEN_GET(val) ((((val) & LTQ_EBU_CON_0_BCGEN) >> 12) & 0x3) ++#define LTQ_EBU_CON_0_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_BCGEN) | (((val) & 0x3) << 12)) ++/* Write Access Wait-State Control (10:8) */ ++#define LTQ_EBU_CON_0_WAITWRC (0x7 << 8) ++#define LTQ_EBU_CON_0_WAITWRC_VAL(val) (((val) & 0x7) << 8) ++#define LTQ_EBU_CON_0_WAITWRC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITWRC) >> 8) & 0x7) ++#define LTQ_EBU_CON_0_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITWRC) | (((val) & 0x7) << 8)) ++/* Read Access Wait-State Control (7:6) */ ++#define LTQ_EBU_CON_0_WAITRDC (0x3 << 6) ++#define LTQ_EBU_CON_0_WAITRDC_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_EBU_CON_0_WAITRDC_GET(val) ((((val) & LTQ_EBU_CON_0_WAITRDC) >> 6) & 0x3) ++#define LTQ_EBU_CON_0_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_WAITRDC) | (((val) & 0x3) << 6)) ++/* Hold/Pause Cycle Control (5:4) */ ++#define LTQ_EBU_CON_0_HOLDC (0x3 << 4) ++#define LTQ_EBU_CON_0_HOLDC_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_EBU_CON_0_HOLDC_GET(val) ((((val) & LTQ_EBU_CON_0_HOLDC) >> 4) & 0x3) ++#define LTQ_EBU_CON_0_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_HOLDC) | (((val) & 0x3) << 4)) ++/* Recovery Cycle Control (3:2) */ ++#define LTQ_EBU_CON_0_RECOVC (0x3 << 2) ++#define LTQ_EBU_CON_0_RECOVC_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_EBU_CON_0_RECOVC_GET(val) ((((val) & LTQ_EBU_CON_0_RECOVC) >> 2) & 0x3) ++#define LTQ_EBU_CON_0_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_RECOVC) | (((val) & 0x3) << 2)) ++/* Wait Cycle Multiplier Control (1:0) */ ++#define LTQ_EBU_CON_0_CMULT (0x3) ++#define LTQ_EBU_CON_0_CMULT_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_EBU_CON_0_CMULT_GET(val) ((((val) & LTQ_EBU_CON_0_CMULT) >> 0) & 0x3) ++#define LTQ_EBU_CON_0_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_CON_0_CMULT) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * External Bus Unit Emulator Bus Configuration Register ++ ******************************************************************************/ ++ ++/* Write Protection (31) */ ++#define LTQ_EBU_EMU_BC_WRITE (0x1 << 31) ++#define LTQ_EBU_EMU_BC_WRITE_VAL(val) (((val) & 0x1) << 31) ++#define LTQ_EBU_EMU_BC_WRITE_GET(val) ((((val) & LTQ_EBU_EMU_BC_WRITE) >> 31) & 0x1) ++#define LTQ_EBU_EMU_BC_WRITE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WRITE) | (((val) & 0x1) << 31)) ++/* Address Generation Control (26:24) */ ++#define LTQ_EBU_EMU_BC_AGEN (0x7 << 24) ++#define LTQ_EBU_EMU_BC_AGEN_VAL(val) (((val) & 0x7) << 24) ++#define LTQ_EBU_EMU_BC_AGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_AGEN) >> 24) & 0x7) ++#define LTQ_EBU_EMU_BC_AGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_AGEN) | (((val) & 0x7) << 24)) ++/* Extended Address Setup Control (22) */ ++#define LTQ_EBU_EMU_BC_SETUP (0x1 << 22) ++#define LTQ_EBU_EMU_BC_SETUP_VAL(val) (((val) & 0x1) << 22) ++#define LTQ_EBU_EMU_BC_SETUP_GET(val) ((((val) & LTQ_EBU_EMU_BC_SETUP) >> 22) & 0x1) ++#define LTQ_EBU_EMU_BC_SETUP_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_SETUP) | (((val) & 0x1) << 22)) ++/* Variable Waitstate Insertion Control (21:20) */ ++#define LTQ_EBU_EMU_BC_WAIT (0x3 << 20) ++#define LTQ_EBU_EMU_BC_WAIT_VAL(val) (((val) & 0x3) << 20) ++#define LTQ_EBU_EMU_BC_WAIT_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAIT) >> 20) & 0x3) ++#define LTQ_EBU_EMU_BC_WAIT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAIT) | (((val) & 0x3) << 20)) ++/* Active WAIT Level Control (19) */ ++#define LTQ_EBU_EMU_BC_WINV (0x1 << 19) ++#define LTQ_EBU_EMU_BC_WINV_VAL(val) (((val) & 0x1) << 19) ++#define LTQ_EBU_EMU_BC_WINV_GET(val) ((((val) & LTQ_EBU_EMU_BC_WINV) >> 19) & 0x1) ++#define LTQ_EBU_EMU_BC_WINV_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WINV) | (((val) & 0x1) << 19)) ++/* External Device Data Width Control (17:16) */ ++#define LTQ_EBU_EMU_BC_PORTW (0x3 << 16) ++#define LTQ_EBU_EMU_BC_PORTW_VAL(val) (((val) & 0x3) << 16) ++#define LTQ_EBU_EMU_BC_PORTW_GET(val) ((((val) & LTQ_EBU_EMU_BC_PORTW) >> 16) & 0x3) ++#define LTQ_EBU_EMU_BC_PORTW_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_PORTW) | (((val) & 0x3) << 16)) ++/* Address Latch Enable Function (15:14) */ ++#define LTQ_EBU_EMU_BC_ALEC (0x3 << 14) ++#define LTQ_EBU_EMU_BC_ALEC_VAL(val) (((val) & 0x3) << 14) ++#define LTQ_EBU_EMU_BC_ALEC_GET(val) ((((val) & LTQ_EBU_EMU_BC_ALEC) >> 14) & 0x3) ++#define LTQ_EBU_EMU_BC_ALEC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_ALEC) | (((val) & 0x3) << 14)) ++/* Byte Control Signal Timing Mode (13:12) */ ++#define LTQ_EBU_EMU_BC_BCGEN (0x3 << 12) ++#define LTQ_EBU_EMU_BC_BCGEN_VAL(val) (((val) & 0x3) << 12) ++#define LTQ_EBU_EMU_BC_BCGEN_GET(val) ((((val) & LTQ_EBU_EMU_BC_BCGEN) >> 12) & 0x3) ++#define LTQ_EBU_EMU_BC_BCGEN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_BCGEN) | (((val) & 0x3) << 12)) ++/* Write Access Waitstate Control (10:8) */ ++#define LTQ_EBU_EMU_BC_WAITWRC (0x7 << 8) ++#define LTQ_EBU_EMU_BC_WAITWRC_VAL(val) (((val) & 0x7) << 8) ++#define LTQ_EBU_EMU_BC_WAITWRC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITWRC) >> 8) & 0x7) ++#define LTQ_EBU_EMU_BC_WAITWRC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITWRC) | (((val) & 0x7) << 8)) ++/* Read Access Waitstate Control (7:6) */ ++#define LTQ_EBU_EMU_BC_WAITRDC (0x3 << 6) ++#define LTQ_EBU_EMU_BC_WAITRDC_VAL(val) (((val) & 0x3) << 6) ++#define LTQ_EBU_EMU_BC_WAITRDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_WAITRDC) >> 6) & 0x3) ++#define LTQ_EBU_EMU_BC_WAITRDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_WAITRDC) | (((val) & 0x3) << 6)) ++/* Hold/Pause Cycle Control (5:4) */ ++#define LTQ_EBU_EMU_BC_HOLDC (0x3 << 4) ++#define LTQ_EBU_EMU_BC_HOLDC_VAL(val) (((val) & 0x3) << 4) ++#define LTQ_EBU_EMU_BC_HOLDC_GET(val) ((((val) & LTQ_EBU_EMU_BC_HOLDC) >> 4) & 0x3) ++#define LTQ_EBU_EMU_BC_HOLDC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_HOLDC) | (((val) & 0x3) << 4)) ++/* Recovery Cycles Control (3:2) */ ++#define LTQ_EBU_EMU_BC_RECOVC (0x3 << 2) ++#define LTQ_EBU_EMU_BC_RECOVC_VAL(val) (((val) & 0x3) << 2) ++#define LTQ_EBU_EMU_BC_RECOVC_GET(val) ((((val) & LTQ_EBU_EMU_BC_RECOVC) >> 2) & 0x3) ++#define LTQ_EBU_EMU_BC_RECOVC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_RECOVC) | (((val) & 0x3) << 2)) ++/* Cycle Multiplier Control (1:0) */ ++#define LTQ_EBU_EMU_BC_CMULT (0x3) ++#define LTQ_EBU_EMU_BC_CMULT_VAL(val) (((val) & 0x3) << 0) ++#define LTQ_EBU_EMU_BC_CMULT_GET(val) ((((val) & LTQ_EBU_EMU_BC_CMULT) >> 0) & 0x3) ++#define LTQ_EBU_EMU_BC_CMULT_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_BC_CMULT) | (((val) & 0x3) << 0)) ++ ++/******************************************************************************* ++ * PC-Card Control Register ++ ******************************************************************************/ ++ ++/* External Interrupt Input IREQ (3:1) */ ++#define LTQ_EBU_PCC_CON_IREQ (0x7 << 1) ++#define LTQ_EBU_PCC_CON_IREQ_VAL(val) (((val) & 0x7) << 1) ++#define LTQ_EBU_PCC_CON_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_CON_IREQ) >> 1) & 0x7) ++#define LTQ_EBU_PCC_CON_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_IREQ) | (((val) & 0x7) << 1)) ++/* PC Card ON (0) */ ++#define LTQ_EBU_PCC_CON_ON (0x1) ++#define LTQ_EBU_PCC_CON_ON_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_PCC_CON_ON_GET(val) ((((val) & LTQ_EBU_PCC_CON_ON) >> 0) & 0x1) ++#define LTQ_EBU_PCC_CON_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_CON_ON) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * PCC Status Register ++ ******************************************************************************/ ++ ++/* Interrupt Request (6) */ ++#define LTQ_EBU_PCC_STAT_IRQ (0x1 << 6) ++#define LTQ_EBU_PCC_STAT_IRQ_GET(val) ((((val) & LTQ_EBU_PCC_STAT_IRQ) >> 6) & 0x1) ++/* PC-Card Overcurrent (5) */ ++#define LTQ_EBU_PCC_STAT_OC (0x1 << 5) ++#define LTQ_EBU_PCC_STAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_STAT_OC) >> 5) & 0x1) ++/* PC-Card Socket Power On (4) */ ++#define LTQ_EBU_PCC_STAT_SPON (0x1 << 4) ++#define LTQ_EBU_PCC_STAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_STAT_SPON) >> 4) & 0x1) ++/* Card Detect Status (1:0) */ ++#define LTQ_EBU_PCC_STAT_CD (0x3) ++#define LTQ_EBU_PCC_STAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_STAT_CD) >> 0) & 0x3) ++ ++/******************************************************************************* ++ * PCC Interrupt Status Register ++ ******************************************************************************/ ++ ++/* Interrupt Request Active Interrupt (4) */ ++#define LTQ_EBU_PCC_ISTAT_IREQ (0x1 << 4) ++#define LTQ_EBU_PCC_ISTAT_IREQ_VAL(val) (((val) & 0x1) << 4) ++#define LTQ_EBU_PCC_ISTAT_IREQ_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_IREQ) >> 4) & 0x1) ++#define LTQ_EBU_PCC_ISTAT_IREQ_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_IREQ) | (((val) & 0x1) << 4)) ++/* Over Current Status Change Interrupt (3) */ ++#define LTQ_EBU_PCC_ISTAT_OC (0x1 << 3) ++#define LTQ_EBU_PCC_ISTAT_OC_VAL(val) (((val) & 0x1) << 3) ++#define LTQ_EBU_PCC_ISTAT_OC_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_OC) >> 3) & 0x1) ++#define LTQ_EBU_PCC_ISTAT_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_OC) | (((val) & 0x1) << 3)) ++/* Socket Power on Status Change Interrupt (2) */ ++#define LTQ_EBU_PCC_ISTAT_SPON (0x1 << 2) ++#define LTQ_EBU_PCC_ISTAT_SPON_VAL(val) (((val) & 0x1) << 2) ++#define LTQ_EBU_PCC_ISTAT_SPON_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_SPON) >> 2) & 0x1) ++#define LTQ_EBU_PCC_ISTAT_SPON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_SPON) | (((val) & 0x1) << 2)) ++/* Voltage Sense Status Change Interrupt (1) */ ++#define LTQ_EBU_PCC_ISTAT_VS (0x1 << 1) ++#define LTQ_EBU_PCC_ISTAT_VS_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_EBU_PCC_ISTAT_VS_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_VS) >> 1) & 0x1) ++#define LTQ_EBU_PCC_ISTAT_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_VS) | (((val) & 0x1) << 1)) ++/* Card Detect Status Change Interrupt (0) */ ++#define LTQ_EBU_PCC_ISTAT_CD (0x1) ++#define LTQ_EBU_PCC_ISTAT_CD_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_PCC_ISTAT_CD_GET(val) ((((val) & LTQ_EBU_PCC_ISTAT_CD) >> 0) & 0x1) ++#define LTQ_EBU_PCC_ISTAT_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_ISTAT_CD) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * PCC Interrupt Enable Register ++ ******************************************************************************/ ++ ++/* Enable of Interrupt Request IR (4) */ ++#define LTQ_EBU_PCC_IEN_IR (0x1 << 4) ++#define LTQ_EBU_PCC_IEN_IR_VAL(val) (((val) & 0x1) << 4) ++#define LTQ_EBU_PCC_IEN_IR_GET(val) ((((val) & LTQ_EBU_PCC_IEN_IR) >> 4) & 0x1) ++#define LTQ_EBU_PCC_IEN_IR_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_IR) | (((val) & 0x1) << 4)) ++/* Enable of Interrupt Request OC event (3) */ ++#define LTQ_EBU_PCC_IEN_OC (0x1 << 3) ++#define LTQ_EBU_PCC_IEN_OC_VAL(val) (((val) & 0x1) << 3) ++#define LTQ_EBU_PCC_IEN_OC_GET(val) ((((val) & LTQ_EBU_PCC_IEN_OC) >> 3) & 0x1) ++#define LTQ_EBU_PCC_IEN_OC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_OC) | (((val) & 0x1) << 3)) ++/* Enable of Interrupt Request Socket Power On (2) */ ++#define LTQ_EBU_PCC_IEN_PWRON (0x1 << 2) ++#define LTQ_EBU_PCC_IEN_PWRON_VAL(val) (((val) & 0x1) << 2) ++#define LTQ_EBU_PCC_IEN_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_IEN_PWRON) >> 2) & 0x1) ++#define LTQ_EBU_PCC_IEN_PWRON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_PWRON) | (((val) & 0x1) << 2)) ++/* Enable of Interrupt Request Voltage Sense (1) */ ++#define LTQ_EBU_PCC_IEN_VS (0x1 << 1) ++#define LTQ_EBU_PCC_IEN_VS_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_EBU_PCC_IEN_VS_GET(val) ((((val) & LTQ_EBU_PCC_IEN_VS) >> 1) & 0x1) ++#define LTQ_EBU_PCC_IEN_VS_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_VS) | (((val) & 0x1) << 1)) ++/* Enable of Interrupt Request Card Detect (0) */ ++#define LTQ_EBU_PCC_IEN_CD (0x1) ++#define LTQ_EBU_PCC_IEN_CD_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_PCC_IEN_CD_GET(val) ((((val) & LTQ_EBU_PCC_IEN_CD) >> 0) & 0x1) ++#define LTQ_EBU_PCC_IEN_CD_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_PCC_IEN_CD) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * PCC Interrupt Output Status Register ++ ******************************************************************************/ ++ ++/* Status of Interrupt Request IR (4) */ ++#define LTQ_EBU_PCC_INT_OUT_IR (0x1 << 4) ++#define LTQ_EBU_PCC_INT_OUT_IR_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_IR) >> 4) & 0x1) ++/* Status of Interrupt Request OC (3) */ ++#define LTQ_EBU_PCC_INT_OUT_OC (0x1 << 3) ++#define LTQ_EBU_PCC_INT_OUT_OC_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_OC) >> 3) & 0x1) ++/* Status of Interrupt Request Socket Power On (2) */ ++#define LTQ_EBU_PCC_INT_OUT_PWRON (0x1 << 2) ++#define LTQ_EBU_PCC_INT_OUT_PWRON_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_PWRON) >> 2) & 0x1) ++/* Status of Interrupt Request Voltage Sense (1) */ ++#define LTQ_EBU_PCC_INT_OUT_VS (0x1 << 1) ++#define LTQ_EBU_PCC_INT_OUT_VS_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_VS) >> 1) & 0x1) ++/* Status of Interrupt Request Card Detect (0) */ ++#define LTQ_EBU_PCC_INT_OUT_CD (0x1) ++#define LTQ_EBU_PCC_INT_OUT_CD_GET(val) ((((val) & LTQ_EBU_PCC_INT_OUT_CD) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * PCC Interrupt Request Set Register ++ ******************************************************************************/ ++ ++/* Set Interrupt Request IR (4) */ ++#define LTQ_EBU_PCC_IRS_IR (0x1 << 4) ++#define LTQ_EBU_PCC_IRS_IR_VAL(val) (((val) & 0x1) << 4) ++#define LTQ_EBU_PCC_IRS_IR_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_IR) | (val) & 1) << 4) ++/* Set Interrupt Request OC (3) */ ++#define LTQ_EBU_PCC_IRS_OC (0x1 << 3) ++#define LTQ_EBU_PCC_IRS_OC_VAL(val) (((val) & 0x1) << 3) ++#define LTQ_EBU_PCC_IRS_OC_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_OC) | (val) & 1) << 3) ++/* Set Interrupt Request Socket Power On (2) */ ++#define LTQ_EBU_PCC_IRS_PWRON (0x1 << 2) ++#define LTQ_EBU_PCC_IRS_PWRON_VAL(val) (((val) & 0x1) << 2) ++#define LTQ_EBU_PCC_IRS_PWRON_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_PWRON) | (val) & 1) << 2) ++/* Set Interrupt Request Voltage Sense (1) */ ++#define LTQ_EBU_PCC_IRS_VS (0x1 << 1) ++#define LTQ_EBU_PCC_IRS_VS_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_EBU_PCC_IRS_VS_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_VS) | (val) & 1) << 1) ++/* Set Interrupt Request Card Detect (0) */ ++#define LTQ_EBU_PCC_IRS_CD (0x1) ++#define LTQ_EBU_PCC_IRS_CD_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_PCC_IRS_CD_SET(reg,val) (reg) = (((reg & ~LTQ_EBU_PCC_IRS_CD) | (val) & 1) << 0) ++ ++/******************************************************************************* ++ * NAND Flash Control Register ++ ******************************************************************************/ ++ ++/* ECC Enabling (31) */ ++#define LTQ_EBU_NAND_CON_ECC_ON (0x1 << 31) ++#define LTQ_EBU_NAND_CON_ECC_ON_VAL(val) (((val) & 0x1) << 31) ++#define LTQ_EBU_NAND_CON_ECC_ON_GET(val) ((((val) & LTQ_EBU_NAND_CON_ECC_ON) >> 31) & 0x1) ++#define LTQ_EBU_NAND_CON_ECC_ON_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ECC_ON) | (((val) & 0x1) << 31)) ++/* Latch enable (23:18) */ ++#define LTQ_EBU_NAND_CON_LAT_EN (0x3f << 18) ++#define LTQ_EBU_NAND_CON_LAT_EN_VAL(val) (((val) & 0x3f) << 18) ++#define LTQ_EBU_NAND_CON_LAT_EN_GET(val) ((((val) & LTQ_EBU_NAND_CON_LAT_EN) >> 18) & 0x3f) ++#define LTQ_EBU_NAND_CON_LAT_EN_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_LAT_EN) | (((val) & 0x3f) << 18)) ++/* Output ChipSelect# Selection (11:10) */ ++#define LTQ_EBU_NAND_CON_OUT_CS_S (0x3 << 10) ++#define LTQ_EBU_NAND_CON_OUT_CS_S_VAL(val) (((val) & 0x3) << 10) ++#define LTQ_EBU_NAND_CON_OUT_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_OUT_CS_S) >> 10) & 0x3) ++#define LTQ_EBU_NAND_CON_OUT_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_OUT_CS_S) | (((val) & 0x3) << 10)) ++/* Input ChipSelect# Selection (9:8) */ ++#define LTQ_EBU_NAND_CON_IN_CS_S (0x3 << 8) ++#define LTQ_EBU_NAND_CON_IN_CS_S_VAL(val) (((val) & 0x3) << 8) ++#define LTQ_EBU_NAND_CON_IN_CS_S_GET(val) ((((val) & LTQ_EBU_NAND_CON_IN_CS_S) >> 8) & 0x3) ++#define LTQ_EBU_NAND_CON_IN_CS_S_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_IN_CS_S) | (((val) & 0x3) << 8)) ++/* Set PRE (7) */ ++#define LTQ_EBU_NAND_CON_PRE_P (0x1 << 7) ++#define LTQ_EBU_NAND_CON_PRE_P_VAL(val) (((val) & 0x1) << 7) ++#define LTQ_EBU_NAND_CON_PRE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_PRE_P) >> 7) & 0x1) ++#define LTQ_EBU_NAND_CON_PRE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_PRE_P) | (((val) & 0x1) << 7)) ++/* Set WP Active Polarity (6) */ ++#define LTQ_EBU_NAND_CON_WP_P (0x1 << 6) ++#define LTQ_EBU_NAND_CON_WP_P_VAL(val) (((val) & 0x1) << 6) ++#define LTQ_EBU_NAND_CON_WP_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_WP_P) >> 6) & 0x1) ++#define LTQ_EBU_NAND_CON_WP_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_WP_P) | (((val) & 0x1) << 6)) ++/* Set SE Active Polarity (5) */ ++#define LTQ_EBU_NAND_CON_SE_P (0x1 << 5) ++#define LTQ_EBU_NAND_CON_SE_P_VAL(val) (((val) & 0x1) << 5) ++#define LTQ_EBU_NAND_CON_SE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_SE_P) >> 5) & 0x1) ++#define LTQ_EBU_NAND_CON_SE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_SE_P) | (((val) & 0x1) << 5)) ++/* Set CS Active Polarity (4) */ ++#define LTQ_EBU_NAND_CON_CS_P (0x1 << 4) ++#define LTQ_EBU_NAND_CON_CS_P_VAL(val) (((val) & 0x1) << 4) ++#define LTQ_EBU_NAND_CON_CS_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CS_P) >> 4) & 0x1) ++#define LTQ_EBU_NAND_CON_CS_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CS_P) | (((val) & 0x1) << 4)) ++/* Set CLE Active Polarity (3) */ ++#define LTQ_EBU_NAND_CON_CLE_P (0x1 << 3) ++#define LTQ_EBU_NAND_CON_CLE_P_VAL(val) (((val) & 0x1) << 3) ++#define LTQ_EBU_NAND_CON_CLE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_CLE_P) >> 3) & 0x1) ++#define LTQ_EBU_NAND_CON_CLE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CLE_P) | (((val) & 0x1) << 3)) ++/* Set ALE Active Polarity (2) */ ++#define LTQ_EBU_NAND_CON_ALE_P (0x1 << 2) ++#define LTQ_EBU_NAND_CON_ALE_P_VAL(val) (((val) & 0x1) << 2) ++#define LTQ_EBU_NAND_CON_ALE_P_GET(val) ((((val) & LTQ_EBU_NAND_CON_ALE_P) >> 2) & 0x1) ++#define LTQ_EBU_NAND_CON_ALE_P_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_ALE_P) | (((val) & 0x1) << 2)) ++/* NAND CS Mux with EBU CS Enable (1) */ ++#define LTQ_EBU_NAND_CON_CSMUX_E (0x1 << 1) ++#define LTQ_EBU_NAND_CON_CSMUX_E_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_EBU_NAND_CON_CSMUX_E_GET(val) ((((val) & LTQ_EBU_NAND_CON_CSMUX_E) >> 1) & 0x1) ++#define LTQ_EBU_NAND_CON_CSMUX_E_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_CSMUX_E) | (((val) & 0x1) << 1)) ++/* NAND FLASH Mode Support (0) */ ++#define LTQ_EBU_NAND_CON_NANDMODE (0x1) ++#define LTQ_EBU_NAND_CON_NANDMODE_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_NAND_CON_NANDMODE_GET(val) ((((val) & LTQ_EBU_NAND_CON_NANDMODE) >> 0) & 0x1) ++#define LTQ_EBU_NAND_CON_NANDMODE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_CON_NANDMODE) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * NAND Flash State Register ++ ******************************************************************************/ ++ ++/* Reserved (31:3) */ ++#define LTQ_EBU_NAND_WAIT_RES (0x1fffffff << 3) ++#define LTQ_EBU_NAND_WAIT_RES_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RES) >> 3) & 0x1fffffff) ++/* NAND Write Complete (3) */ ++#define LTQ_EBU_NAND_WAIT_WR_C (0x1 << 3) ++#define LTQ_EBU_NAND_WAIT_WR_C_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_WR_C) >> 3) & 0x1) ++/* Record the RD Edge (rising ) (2) */ ++#define LTQ_EBU_NAND_WAIT_RD_EDGE (0x1 << 2) ++#define LTQ_EBU_NAND_WAIT_RD_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RD_EDGE) >> 2) & 0x1) ++/* Record the BY# Edge (falling) (1) */ ++#define LTQ_EBU_NAND_WAIT_BY_EDGE (0x1 << 1) ++#define LTQ_EBU_NAND_WAIT_BY_EDGE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_BY_EDGE) >> 1) & 0x1) ++/* Rd/BY# value (0) */ ++#define LTQ_EBU_NAND_WAIT_RDBY_VALUE (0x1) ++#define LTQ_EBU_NAND_WAIT_RDBY_VALUE_GET(val) ((((val) & LTQ_EBU_NAND_WAIT_RDBY_VALUE) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * NAND ECC Result Register 0 ++ ******************************************************************************/ ++ ++/* Reserved (31:24) */ ++#define LTQ_EBU_NAND_ECC0_RES (0xff << 24) ++#define LTQ_EBU_NAND_ECC0_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_RES) >> 24) & 0xff) ++/* ECC value (23:16) */ ++#define LTQ_EBU_NAND_ECC0_ECC_B2 (0xff << 16) ++#define LTQ_EBU_NAND_ECC0_ECC_B2_VAL(val) (((val) & 0xff) << 16) ++#define LTQ_EBU_NAND_ECC0_ECC_B2_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B2) >> 16) & 0xff) ++#define LTQ_EBU_NAND_ECC0_ECC_B2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B2) | (((val) & 0xff) << 16)) ++/* ECC value (15:8) */ ++#define LTQ_EBU_NAND_ECC0_ECC_B1 (0xff << 8) ++#define LTQ_EBU_NAND_ECC0_ECC_B1_VAL(val) (((val) & 0xff) << 8) ++#define LTQ_EBU_NAND_ECC0_ECC_B1_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B1) >> 8) & 0xff) ++#define LTQ_EBU_NAND_ECC0_ECC_B1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B1) | (((val) & 0xff) << 8)) ++/* ECC value (7:0) */ ++#define LTQ_EBU_NAND_ECC0_ECC_B0 (0xff) ++#define LTQ_EBU_NAND_ECC0_ECC_B0_VAL(val) (((val) & 0xff) << 0) ++#define LTQ_EBU_NAND_ECC0_ECC_B0_GET(val) ((((val) & LTQ_EBU_NAND_ECC0_ECC_B0) >> 0) & 0xff) ++#define LTQ_EBU_NAND_ECC0_ECC_B0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC0_ECC_B0) | (((val) & 0xff) << 0)) ++ ++/******************************************************************************* ++ * NAND ECC Address Counter Register ++ ******************************************************************************/ ++ ++/* Reserved (31:9) */ ++#define LTQ_EBU_NAND_ECC_AC_RES (0x7fffff << 9) ++#define LTQ_EBU_NAND_ECC_AC_RES_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_RES) >> 9) & 0x7fffff) ++/* ECC address counter (8:0) */ ++#define LTQ_EBU_NAND_ECC_AC_ECC_AC (0x1ff) ++#define LTQ_EBU_NAND_ECC_AC_ECC_AC_VAL(val) (((val) & 0x1ff) << 0) ++#define LTQ_EBU_NAND_ECC_AC_ECC_AC_GET(val) ((((val) & LTQ_EBU_NAND_ECC_AC_ECC_AC) >> 0) & 0x1ff) ++#define LTQ_EBU_NAND_ECC_AC_ECC_AC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_NAND_ECC_AC_ECC_AC) | (((val) & 0x1ff) << 0)) ++ ++/******************************************************************************* ++ * Internal Address Emulation Register ++ ******************************************************************************/ ++ ++/* Memory Region Base Address (31:12) */ ++#define LTQ_EBU_EMU_ADDR_BASE (0xfffff << 12) ++#define LTQ_EBU_EMU_ADDR_BASE_VAL(val) (((val) & 0xfffff) << 12) ++#define LTQ_EBU_EMU_ADDR_BASE_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_BASE) >> 12) & 0xfffff) ++#define LTQ_EBU_EMU_ADDR_BASE_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_BASE) | (((val) & 0xfffff) << 12)) ++/* Memory Region Address Mask (7:4) */ ++#define LTQ_EBU_EMU_ADDR_MASK (0xf << 4) ++#define LTQ_EBU_EMU_ADDR_MASK_VAL(val) (((val) & 0xf) << 4) ++#define LTQ_EBU_EMU_ADDR_MASK_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MASK) >> 4) & 0xf) ++#define LTQ_EBU_EMU_ADDR_MASK_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MASK) | (((val) & 0xf) << 4)) ++/* Memory Region Mirror Segment B Control (1) */ ++#define LTQ_EBU_EMU_ADDR_MRMB (0x1 << 1) ++#define LTQ_EBU_EMU_ADDR_MRMB_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_EBU_EMU_ADDR_MRMB_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MRMB) >> 1) & 0x1) ++#define LTQ_EBU_EMU_ADDR_MRMB_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MRMB) | (((val) & 0x1) << 1)) ++/* Memory Region Enable Control (0) */ ++#define LTQ_EBU_EMU_ADDR_MREC (0x1) ++#define LTQ_EBU_EMU_ADDR_MREC_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_EMU_ADDR_MREC_GET(val) ((((val) & LTQ_EBU_EMU_ADDR_MREC) >> 0) & 0x1) ++#define LTQ_EBU_EMU_ADDR_MREC_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_ADDR_MREC) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * nternal Emulator Configuration Register ++ ******************************************************************************/ ++ ++/* Overlay Memory Control Region 3 (3) */ ++#define LTQ_EBU_EMU_CON_OVL3 (0x1 << 3) ++#define LTQ_EBU_EMU_CON_OVL3_VAL(val) (((val) & 0x1) << 3) ++#define LTQ_EBU_EMU_CON_OVL3_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL3) >> 3) & 0x1) ++#define LTQ_EBU_EMU_CON_OVL3_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL3) | (((val) & 0x1) << 3)) ++/* Overlay Memory Control Region 2 (2) */ ++#define LTQ_EBU_EMU_CON_OVL2 (0x1 << 2) ++#define LTQ_EBU_EMU_CON_OVL2_VAL(val) (((val) & 0x1) << 2) ++#define LTQ_EBU_EMU_CON_OVL2_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL2) >> 2) & 0x1) ++#define LTQ_EBU_EMU_CON_OVL2_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL2) | (((val) & 0x1) << 2)) ++/* Overlay Memory Control Region 1 (1) */ ++#define LTQ_EBU_EMU_CON_OVL1 (0x1 << 1) ++#define LTQ_EBU_EMU_CON_OVL1_VAL(val) (((val) & 0x1) << 1) ++#define LTQ_EBU_EMU_CON_OVL1_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL1) >> 1) & 0x1) ++#define LTQ_EBU_EMU_CON_OVL1_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL1) | (((val) & 0x1) << 1)) ++/* Overlay Memory Control Region 0 (0) */ ++#define LTQ_EBU_EMU_CON_OVL0 (0x1) ++#define LTQ_EBU_EMU_CON_OVL0_VAL(val) (((val) & 0x1) << 0) ++#define LTQ_EBU_EMU_CON_OVL0_GET(val) ((((val) & LTQ_EBU_EMU_CON_OVL0) >> 0) & 0x1) ++#define LTQ_EBU_EMU_CON_OVL0_SET(reg,val) (reg) = ((reg & ~LTQ_EBU_EMU_CON_OVL0) | (((val) & 0x1) << 0)) ++ ++#endif /* __LTQ_EBU_H */ +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/port_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/port_reg.h 2012-07-31 15:46:02.484476159 +0200 +@@ -0,0 +1,3262 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __PORT_REG_H ++#define __PORT_REG_H ++ ++#define port_r32(reg) __raw_readl(®) ++#define port_w32(val, reg) __raw_writel(val, ®) ++ ++/** PORT register structure */ ++struct svip_reg_port { ++ volatile u32 out; /* 0x0000 */ ++ volatile u32 in; /* 0x0004 */ ++ volatile u32 dir; /* 0x0008 */ ++ volatile u32 altsel0; /* 0x000C */ ++ volatile u32 altsel1; /* 0x0010 */ ++ volatile u32 puen; /* 0x0014 */ ++ volatile u32 exintcr0; /* 0x0018 */ ++ volatile u32 exintcr1; /* 0x001C */ ++ volatile u32 irncr; /* 0x0020 */ ++ volatile u32 irnicr; /* 0x0024 */ ++ volatile u32 irnen; /* 0x0028 */ ++ volatile u32 irncfg; /* 0x002C */ ++ volatile u32 irnenset; /* 0x0030 */ ++ volatile u32 irnenclr; /* 0x0034 */ ++}; ++ ++/******************************************************************************* ++ * Port 0 Data Output Register ++ ******************************************************************************/ ++ ++/* Port 0 Pin # Output Value (19) */ ++#define PORT_P0_OUT_P19 (0x1 << 19) ++#define PORT_P0_OUT_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_OUT_P19_GET(val) ((((val) & PORT_P0_OUT_P19) >> 19) & 0x1) ++#define PORT_P0_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P19) | (((val) & 0x1) << 19)) ++/* Port 0 Pin # Output Value (18) */ ++#define PORT_P0_OUT_P18 (0x1 << 18) ++#define PORT_P0_OUT_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P0_OUT_P18_GET(val) ((((val) & PORT_P0_OUT_P18) >> 18) & 0x1) ++#define PORT_P0_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P18) | (((val) & 0x1) << 18)) ++/* Port 0 Pin # Output Value (17) */ ++#define PORT_P0_OUT_P17 (0x1 << 17) ++#define PORT_P0_OUT_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_OUT_P17_GET(val) ((((val) & PORT_P0_OUT_P17) >> 17) & 0x1) ++#define PORT_P0_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P17) | (((val) & 0x1) << 17)) ++/* Port 0 Pin # Output Value (16) */ ++#define PORT_P0_OUT_P16 (0x1 << 16) ++#define PORT_P0_OUT_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_OUT_P16_GET(val) ((((val) & PORT_P0_OUT_P16) >> 16) & 0x1) ++#define PORT_P0_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P16) | (((val) & 0x1) << 16)) ++/* Port 0 Pin # Output Value (15) */ ++#define PORT_P0_OUT_P15 (0x1 << 15) ++#define PORT_P0_OUT_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_OUT_P15_GET(val) ((((val) & PORT_P0_OUT_P15) >> 15) & 0x1) ++#define PORT_P0_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P15) | (((val) & 0x1) << 15)) ++/* Port 0 Pin # Output Value (14) */ ++#define PORT_P0_OUT_P14 (0x1 << 14) ++#define PORT_P0_OUT_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_OUT_P14_GET(val) ((((val) & PORT_P0_OUT_P14) >> 14) & 0x1) ++#define PORT_P0_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P14) | (((val) & 0x1) << 14)) ++/* Port 0 Pin # Output Value (13) */ ++#define PORT_P0_OUT_P13 (0x1 << 13) ++#define PORT_P0_OUT_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_OUT_P13_GET(val) ((((val) & PORT_P0_OUT_P13) >> 13) & 0x1) ++#define PORT_P0_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P13) | (((val) & 0x1) << 13)) ++/* Port 0 Pin # Output Value (12) */ ++#define PORT_P0_OUT_P12 (0x1 << 12) ++#define PORT_P0_OUT_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_OUT_P12_GET(val) ((((val) & PORT_P0_OUT_P12) >> 12) & 0x1) ++#define PORT_P0_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P12) | (((val) & 0x1) << 12)) ++/* Port 0 Pin # Output Value (11) */ ++#define PORT_P0_OUT_P11 (0x1 << 11) ++#define PORT_P0_OUT_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_OUT_P11_GET(val) ((((val) & PORT_P0_OUT_P11) >> 11) & 0x1) ++#define PORT_P0_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P11) | (((val) & 0x1) << 11)) ++/* Port 0 Pin # Output Value (10) */ ++#define PORT_P0_OUT_P10 (0x1 << 10) ++#define PORT_P0_OUT_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_OUT_P10_GET(val) ((((val) & PORT_P0_OUT_P10) >> 10) & 0x1) ++#define PORT_P0_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P10) | (((val) & 0x1) << 10)) ++/* Port 0 Pin # Output Value (9) */ ++#define PORT_P0_OUT_P9 (0x1 << 9) ++#define PORT_P0_OUT_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_OUT_P9_GET(val) ((((val) & PORT_P0_OUT_P9) >> 9) & 0x1) ++#define PORT_P0_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P9) | (((val) & 0x1) << 9)) ++/* Port 0 Pin # Output Value (8) */ ++#define PORT_P0_OUT_P8 (0x1 << 8) ++#define PORT_P0_OUT_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_OUT_P8_GET(val) ((((val) & PORT_P0_OUT_P8) >> 8) & 0x1) ++#define PORT_P0_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P8) | (((val) & 0x1) << 8)) ++/* Port 0 Pin # Output Value (7) */ ++#define PORT_P0_OUT_P7 (0x1 << 7) ++#define PORT_P0_OUT_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_OUT_P7_GET(val) ((((val) & PORT_P0_OUT_P7) >> 7) & 0x1) ++#define PORT_P0_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P7) | (((val) & 0x1) << 7)) ++/* Port 0 Pin # Output Value (6) */ ++#define PORT_P0_OUT_P6 (0x1 << 6) ++#define PORT_P0_OUT_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P0_OUT_P6_GET(val) ((((val) & PORT_P0_OUT_P6) >> 6) & 0x1) ++#define PORT_P0_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P6) | (((val) & 0x1) << 6)) ++/* Port 0 Pin # Output Value (5) */ ++#define PORT_P0_OUT_P5 (0x1 << 5) ++#define PORT_P0_OUT_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P0_OUT_P5_GET(val) ((((val) & PORT_P0_OUT_P5) >> 5) & 0x1) ++#define PORT_P0_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P5) | (((val) & 0x1) << 5)) ++/* Port 0 Pin # Output Value (4) */ ++#define PORT_P0_OUT_P4 (0x1 << 4) ++#define PORT_P0_OUT_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P0_OUT_P4_GET(val) ((((val) & PORT_P0_OUT_P4) >> 4) & 0x1) ++#define PORT_P0_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P4) | (((val) & 0x1) << 4)) ++/* Port 0 Pin # Output Value (3) */ ++#define PORT_P0_OUT_P3 (0x1 << 3) ++#define PORT_P0_OUT_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P0_OUT_P3_GET(val) ((((val) & PORT_P0_OUT_P3) >> 3) & 0x1) ++#define PORT_P0_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P3) | (((val) & 0x1) << 3)) ++/* Port 0 Pin # Output Value (2) */ ++#define PORT_P0_OUT_P2 (0x1 << 2) ++#define PORT_P0_OUT_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P0_OUT_P2_GET(val) ((((val) & PORT_P0_OUT_P2) >> 2) & 0x1) ++#define PORT_P0_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P2) | (((val) & 0x1) << 2)) ++/* Port 0 Pin # Output Value (1) */ ++#define PORT_P0_OUT_P1 (0x1 << 1) ++#define PORT_P0_OUT_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P0_OUT_P1_GET(val) ((((val) & PORT_P0_OUT_P1) >> 1) & 0x1) ++#define PORT_P0_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P1) | (((val) & 0x1) << 1)) ++/* Port 0 Pin # Output Value (0) */ ++#define PORT_P0_OUT_P0 (0x1) ++#define PORT_P0_OUT_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P0_OUT_P0_GET(val) ((((val) & PORT_P0_OUT_P0) >> 0) & 0x1) ++#define PORT_P0_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_OUT_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 0 Data Input Register ++ ******************************************************************************/ ++ ++/* Port 0 Pin # Latched Input Value (19) */ ++#define PORT_P0_IN_P19 (0x1 << 19) ++#define PORT_P0_IN_P19_GET(val) ((((val) & PORT_P0_IN_P19) >> 19) & 0x1) ++/* Port 0 Pin # Latched Input Value (18) */ ++#define PORT_P0_IN_P18 (0x1 << 18) ++#define PORT_P0_IN_P18_GET(val) ((((val) & PORT_P0_IN_P18) >> 18) & 0x1) ++/* Port 0 Pin # Latched Input Value (17) */ ++#define PORT_P0_IN_P17 (0x1 << 17) ++#define PORT_P0_IN_P17_GET(val) ((((val) & PORT_P0_IN_P17) >> 17) & 0x1) ++/* Port 0 Pin # Latched Input Value (16) */ ++#define PORT_P0_IN_P16 (0x1 << 16) ++#define PORT_P0_IN_P16_GET(val) ((((val) & PORT_P0_IN_P16) >> 16) & 0x1) ++/* Port 0 Pin # Latched Input Value (15) */ ++#define PORT_P0_IN_P15 (0x1 << 15) ++#define PORT_P0_IN_P15_GET(val) ((((val) & PORT_P0_IN_P15) >> 15) & 0x1) ++/* Port 0 Pin # Latched Input Value (14) */ ++#define PORT_P0_IN_P14 (0x1 << 14) ++#define PORT_P0_IN_P14_GET(val) ((((val) & PORT_P0_IN_P14) >> 14) & 0x1) ++/* Port 0 Pin # Latched Input Value (13) */ ++#define PORT_P0_IN_P13 (0x1 << 13) ++#define PORT_P0_IN_P13_GET(val) ((((val) & PORT_P0_IN_P13) >> 13) & 0x1) ++/* Port 0 Pin # Latched Input Value (12) */ ++#define PORT_P0_IN_P12 (0x1 << 12) ++#define PORT_P0_IN_P12_GET(val) ((((val) & PORT_P0_IN_P12) >> 12) & 0x1) ++/* Port 0 Pin # Latched Input Value (11) */ ++#define PORT_P0_IN_P11 (0x1 << 11) ++#define PORT_P0_IN_P11_GET(val) ((((val) & PORT_P0_IN_P11) >> 11) & 0x1) ++/* Port 0 Pin # Latched Input Value (10) */ ++#define PORT_P0_IN_P10 (0x1 << 10) ++#define PORT_P0_IN_P10_GET(val) ((((val) & PORT_P0_IN_P10) >> 10) & 0x1) ++/* Port 0 Pin # Latched Input Value (9) */ ++#define PORT_P0_IN_P9 (0x1 << 9) ++#define PORT_P0_IN_P9_GET(val) ((((val) & PORT_P0_IN_P9) >> 9) & 0x1) ++/* Port 0 Pin # Latched Input Value (8) */ ++#define PORT_P0_IN_P8 (0x1 << 8) ++#define PORT_P0_IN_P8_GET(val) ((((val) & PORT_P0_IN_P8) >> 8) & 0x1) ++/* Port 0 Pin # Latched Input Value (7) */ ++#define PORT_P0_IN_P7 (0x1 << 7) ++#define PORT_P0_IN_P7_GET(val) ((((val) & PORT_P0_IN_P7) >> 7) & 0x1) ++/* Port 0 Pin # Latched Input Value (6) */ ++#define PORT_P0_IN_P6 (0x1 << 6) ++#define PORT_P0_IN_P6_GET(val) ((((val) & PORT_P0_IN_P6) >> 6) & 0x1) ++/* Port 0 Pin # Latched Input Value (5) */ ++#define PORT_P0_IN_P5 (0x1 << 5) ++#define PORT_P0_IN_P5_GET(val) ((((val) & PORT_P0_IN_P5) >> 5) & 0x1) ++/* Port 0 Pin # Latched Input Value (4) */ ++#define PORT_P0_IN_P4 (0x1 << 4) ++#define PORT_P0_IN_P4_GET(val) ((((val) & PORT_P0_IN_P4) >> 4) & 0x1) ++/* Port 0 Pin # Latched Input Value (3) */ ++#define PORT_P0_IN_P3 (0x1 << 3) ++#define PORT_P0_IN_P3_GET(val) ((((val) & PORT_P0_IN_P3) >> 3) & 0x1) ++/* Port 0 Pin # Latched Input Value (2) */ ++#define PORT_P0_IN_P2 (0x1 << 2) ++#define PORT_P0_IN_P2_GET(val) ((((val) & PORT_P0_IN_P2) >> 2) & 0x1) ++/* Port 0 Pin # Latched Input Value (1) */ ++#define PORT_P0_IN_P1 (0x1 << 1) ++#define PORT_P0_IN_P1_GET(val) ((((val) & PORT_P0_IN_P1) >> 1) & 0x1) ++/* Port 0 Pin # Latched Input Value (0) */ ++#define PORT_P0_IN_P0 (0x1) ++#define PORT_P0_IN_P0_GET(val) ((((val) & PORT_P0_IN_P0) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Port 0 Direction Register ++ ******************************************************************************/ ++ ++/* Port 0 Pin #Direction Control (19) */ ++#define PORT_P0_DIR_P19 (0x1 << 19) ++#define PORT_P0_DIR_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_DIR_P19_GET(val) ((((val) & PORT_P0_DIR_P19) >> 19) & 0x1) ++#define PORT_P0_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P19) | (((val) & 0x1) << 19)) ++/* Port 0 Pin #Direction Control (18) */ ++#define PORT_P0_DIR_P18 (0x1 << 18) ++#define PORT_P0_DIR_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P0_DIR_P18_GET(val) ((((val) & PORT_P0_DIR_P18) >> 18) & 0x1) ++#define PORT_P0_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P18) | (((val) & 0x1) << 18)) ++/* Port 0 Pin #Direction Control (17) */ ++#define PORT_P0_DIR_P17 (0x1 << 17) ++#define PORT_P0_DIR_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_DIR_P17_GET(val) ((((val) & PORT_P0_DIR_P17) >> 17) & 0x1) ++#define PORT_P0_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P17) | (((val) & 0x1) << 17)) ++/* Port 0 Pin #Direction Control (16) */ ++#define PORT_P0_DIR_P16 (0x1 << 16) ++#define PORT_P0_DIR_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_DIR_P16_GET(val) ((((val) & PORT_P0_DIR_P16) >> 16) & 0x1) ++#define PORT_P0_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P16) | (((val) & 0x1) << 16)) ++/* Port 0 Pin #Direction Control (15) */ ++#define PORT_P0_DIR_P15 (0x1 << 15) ++#define PORT_P0_DIR_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_DIR_P15_GET(val) ((((val) & PORT_P0_DIR_P15) >> 15) & 0x1) ++#define PORT_P0_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P15) | (((val) & 0x1) << 15)) ++/* Port 0 Pin #Direction Control (14) */ ++#define PORT_P0_DIR_P14 (0x1 << 14) ++#define PORT_P0_DIR_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_DIR_P14_GET(val) ((((val) & PORT_P0_DIR_P14) >> 14) & 0x1) ++#define PORT_P0_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P14) | (((val) & 0x1) << 14)) ++/* Port 0 Pin #Direction Control (13) */ ++#define PORT_P0_DIR_P13 (0x1 << 13) ++#define PORT_P0_DIR_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_DIR_P13_GET(val) ((((val) & PORT_P0_DIR_P13) >> 13) & 0x1) ++#define PORT_P0_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P13) | (((val) & 0x1) << 13)) ++/* Port 0 Pin #Direction Control (12) */ ++#define PORT_P0_DIR_P12 (0x1 << 12) ++#define PORT_P0_DIR_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_DIR_P12_GET(val) ((((val) & PORT_P0_DIR_P12) >> 12) & 0x1) ++#define PORT_P0_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P12) | (((val) & 0x1) << 12)) ++/* Port 0 Pin #Direction Control (11) */ ++#define PORT_P0_DIR_P11 (0x1 << 11) ++#define PORT_P0_DIR_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_DIR_P11_GET(val) ((((val) & PORT_P0_DIR_P11) >> 11) & 0x1) ++#define PORT_P0_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P11) | (((val) & 0x1) << 11)) ++/* Port 0 Pin #Direction Control (10) */ ++#define PORT_P0_DIR_P10 (0x1 << 10) ++#define PORT_P0_DIR_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_DIR_P10_GET(val) ((((val) & PORT_P0_DIR_P10) >> 10) & 0x1) ++#define PORT_P0_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P10) | (((val) & 0x1) << 10)) ++/* Port 0 Pin #Direction Control (9) */ ++#define PORT_P0_DIR_P9 (0x1 << 9) ++#define PORT_P0_DIR_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_DIR_P9_GET(val) ((((val) & PORT_P0_DIR_P9) >> 9) & 0x1) ++#define PORT_P0_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P9) | (((val) & 0x1) << 9)) ++/* Port 0 Pin #Direction Control (8) */ ++#define PORT_P0_DIR_P8 (0x1 << 8) ++#define PORT_P0_DIR_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_DIR_P8_GET(val) ((((val) & PORT_P0_DIR_P8) >> 8) & 0x1) ++#define PORT_P0_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P8) | (((val) & 0x1) << 8)) ++/* Port 0 Pin #Direction Control (7) */ ++#define PORT_P0_DIR_P7 (0x1 << 7) ++#define PORT_P0_DIR_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_DIR_P7_GET(val) ((((val) & PORT_P0_DIR_P7) >> 7) & 0x1) ++#define PORT_P0_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P7) | (((val) & 0x1) << 7)) ++/* Port 0 Pin #Direction Control (6) */ ++#define PORT_P0_DIR_P6 (0x1 << 6) ++#define PORT_P0_DIR_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P0_DIR_P6_GET(val) ((((val) & PORT_P0_DIR_P6) >> 6) & 0x1) ++#define PORT_P0_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P6) | (((val) & 0x1) << 6)) ++/* Port 0 Pin #Direction Control (5) */ ++#define PORT_P0_DIR_P5 (0x1 << 5) ++#define PORT_P0_DIR_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P0_DIR_P5_GET(val) ((((val) & PORT_P0_DIR_P5) >> 5) & 0x1) ++#define PORT_P0_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P5) | (((val) & 0x1) << 5)) ++/* Port 0 Pin #Direction Control (4) */ ++#define PORT_P0_DIR_P4 (0x1 << 4) ++#define PORT_P0_DIR_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P0_DIR_P4_GET(val) ((((val) & PORT_P0_DIR_P4) >> 4) & 0x1) ++#define PORT_P0_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P4) | (((val) & 0x1) << 4)) ++/* Port 0 Pin #Direction Control (3) */ ++#define PORT_P0_DIR_P3 (0x1 << 3) ++#define PORT_P0_DIR_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P0_DIR_P3_GET(val) ((((val) & PORT_P0_DIR_P3) >> 3) & 0x1) ++#define PORT_P0_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P3) | (((val) & 0x1) << 3)) ++/* Port 0 Pin #Direction Control (2) */ ++#define PORT_P0_DIR_P2 (0x1 << 2) ++#define PORT_P0_DIR_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P0_DIR_P2_GET(val) ((((val) & PORT_P0_DIR_P2) >> 2) & 0x1) ++#define PORT_P0_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P2) | (((val) & 0x1) << 2)) ++/* Port 0 Pin #Direction Control (1) */ ++#define PORT_P0_DIR_P1 (0x1 << 1) ++#define PORT_P0_DIR_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P0_DIR_P1_GET(val) ((((val) & PORT_P0_DIR_P1) >> 1) & 0x1) ++#define PORT_P0_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P1) | (((val) & 0x1) << 1)) ++/* Port 0 Pin #Direction Control (0) */ ++#define PORT_P0_DIR_P0 (0x1) ++#define PORT_P0_DIR_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P0_DIR_P0_GET(val) ((((val) & PORT_P0_DIR_P0) >> 0) & 0x1) ++#define PORT_P0_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_DIR_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 0 Alternate Function Select Register 0 ++ ******************************************************************************/ ++ ++/* Alternate Function at Port 0 Bit # (19) */ ++#define PORT_P0_ALTSEL0_P19 (0x1 << 19) ++#define PORT_P0_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_ALTSEL0_P19_GET(val) ((((val) & PORT_P0_ALTSEL0_P19) >> 19) & 0x1) ++#define PORT_P0_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P19) | (((val) & 0x1) << 19)) ++/* Alternate Function at Port 0 Bit # (18) */ ++#define PORT_P0_ALTSEL0_P18 (0x1 << 18) ++#define PORT_P0_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P0_ALTSEL0_P18_GET(val) ((((val) & PORT_P0_ALTSEL0_P18) >> 18) & 0x1) ++#define PORT_P0_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P18) | (((val) & 0x1) << 18)) ++/* Alternate Function at Port 0 Bit # (17) */ ++#define PORT_P0_ALTSEL0_P17 (0x1 << 17) ++#define PORT_P0_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_ALTSEL0_P17_GET(val) ((((val) & PORT_P0_ALTSEL0_P17) >> 17) & 0x1) ++#define PORT_P0_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P17) | (((val) & 0x1) << 17)) ++/* Alternate Function at Port 0 Bit # (16) */ ++#define PORT_P0_ALTSEL0_P16 (0x1 << 16) ++#define PORT_P0_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_ALTSEL0_P16_GET(val) ((((val) & PORT_P0_ALTSEL0_P16) >> 16) & 0x1) ++#define PORT_P0_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P16) | (((val) & 0x1) << 16)) ++/* Alternate Function at Port 0 Bit # (15) */ ++#define PORT_P0_ALTSEL0_P15 (0x1 << 15) ++#define PORT_P0_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_ALTSEL0_P15_GET(val) ((((val) & PORT_P0_ALTSEL0_P15) >> 15) & 0x1) ++#define PORT_P0_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P15) | (((val) & 0x1) << 15)) ++/* Alternate Function at Port 0 Bit # (14) */ ++#define PORT_P0_ALTSEL0_P14 (0x1 << 14) ++#define PORT_P0_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_ALTSEL0_P14_GET(val) ((((val) & PORT_P0_ALTSEL0_P14) >> 14) & 0x1) ++#define PORT_P0_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P14) | (((val) & 0x1) << 14)) ++/* Alternate Function at Port 0 Bit # (13) */ ++#define PORT_P0_ALTSEL0_P13 (0x1 << 13) ++#define PORT_P0_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_ALTSEL0_P13_GET(val) ((((val) & PORT_P0_ALTSEL0_P13) >> 13) & 0x1) ++#define PORT_P0_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P13) | (((val) & 0x1) << 13)) ++/* Alternate Function at Port 0 Bit # (12) */ ++#define PORT_P0_ALTSEL0_P12 (0x1 << 12) ++#define PORT_P0_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_ALTSEL0_P12_GET(val) ((((val) & PORT_P0_ALTSEL0_P12) >> 12) & 0x1) ++#define PORT_P0_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P12) | (((val) & 0x1) << 12)) ++/* Alternate Function at Port 0 Bit # (11) */ ++#define PORT_P0_ALTSEL0_P11 (0x1 << 11) ++#define PORT_P0_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_ALTSEL0_P11_GET(val) ((((val) & PORT_P0_ALTSEL0_P11) >> 11) & 0x1) ++#define PORT_P0_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P11) | (((val) & 0x1) << 11)) ++/* Alternate Function at Port 0 Bit # (10) */ ++#define PORT_P0_ALTSEL0_P10 (0x1 << 10) ++#define PORT_P0_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_ALTSEL0_P10_GET(val) ((((val) & PORT_P0_ALTSEL0_P10) >> 10) & 0x1) ++#define PORT_P0_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P10) | (((val) & 0x1) << 10)) ++/* Alternate Function at Port 0 Bit # (9) */ ++#define PORT_P0_ALTSEL0_P9 (0x1 << 9) ++#define PORT_P0_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_ALTSEL0_P9_GET(val) ((((val) & PORT_P0_ALTSEL0_P9) >> 9) & 0x1) ++#define PORT_P0_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P9) | (((val) & 0x1) << 9)) ++/* Alternate Function at Port 0 Bit # (8) */ ++#define PORT_P0_ALTSEL0_P8 (0x1 << 8) ++#define PORT_P0_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_ALTSEL0_P8_GET(val) ((((val) & PORT_P0_ALTSEL0_P8) >> 8) & 0x1) ++#define PORT_P0_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P8) | (((val) & 0x1) << 8)) ++/* Alternate Function at Port 0 Bit # (7) */ ++#define PORT_P0_ALTSEL0_P7 (0x1 << 7) ++#define PORT_P0_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_ALTSEL0_P7_GET(val) ((((val) & PORT_P0_ALTSEL0_P7) >> 7) & 0x1) ++#define PORT_P0_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P7) | (((val) & 0x1) << 7)) ++/* Alternate Function at Port 0 Bit # (6) */ ++#define PORT_P0_ALTSEL0_P6 (0x1 << 6) ++#define PORT_P0_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P0_ALTSEL0_P6_GET(val) ((((val) & PORT_P0_ALTSEL0_P6) >> 6) & 0x1) ++#define PORT_P0_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P6) | (((val) & 0x1) << 6)) ++/* Alternate Function at Port 0 Bit # (5) */ ++#define PORT_P0_ALTSEL0_P5 (0x1 << 5) ++#define PORT_P0_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P0_ALTSEL0_P5_GET(val) ((((val) & PORT_P0_ALTSEL0_P5) >> 5) & 0x1) ++#define PORT_P0_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P5) | (((val) & 0x1) << 5)) ++/* Alternate Function at Port 0 Bit # (4) */ ++#define PORT_P0_ALTSEL0_P4 (0x1 << 4) ++#define PORT_P0_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P0_ALTSEL0_P4_GET(val) ((((val) & PORT_P0_ALTSEL0_P4) >> 4) & 0x1) ++#define PORT_P0_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P4) | (((val) & 0x1) << 4)) ++/* Alternate Function at Port 0 Bit # (3) */ ++#define PORT_P0_ALTSEL0_P3 (0x1 << 3) ++#define PORT_P0_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P0_ALTSEL0_P3_GET(val) ((((val) & PORT_P0_ALTSEL0_P3) >> 3) & 0x1) ++#define PORT_P0_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P3) | (((val) & 0x1) << 3)) ++/* Alternate Function at Port 0 Bit # (2) */ ++#define PORT_P0_ALTSEL0_P2 (0x1 << 2) ++#define PORT_P0_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P0_ALTSEL0_P2_GET(val) ((((val) & PORT_P0_ALTSEL0_P2) >> 2) & 0x1) ++#define PORT_P0_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P2) | (((val) & 0x1) << 2)) ++/* Alternate Function at Port 0 Bit # (1) */ ++#define PORT_P0_ALTSEL0_P1 (0x1 << 1) ++#define PORT_P0_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P0_ALTSEL0_P1_GET(val) ((((val) & PORT_P0_ALTSEL0_P1) >> 1) & 0x1) ++#define PORT_P0_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P1) | (((val) & 0x1) << 1)) ++/* Alternate Function at Port 0 Bit # (0) */ ++#define PORT_P0_ALTSEL0_P0 (0x1) ++#define PORT_P0_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P0_ALTSEL0_P0_GET(val) ((((val) & PORT_P0_ALTSEL0_P0) >> 0) & 0x1) ++#define PORT_P0_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL0_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 0 Alternate Function Select Register 1 ++ ******************************************************************************/ ++ ++/* Alternate Function at Port 0 Bit # (13) */ ++#define PORT_P0_ALTSEL1_P13 (0x1 << 13) ++#define PORT_P0_ALTSEL1_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_ALTSEL1_P13_GET(val) ((((val) & PORT_P0_ALTSEL1_P13) >> 13) & 0x1) ++#define PORT_P0_ALTSEL1_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P13) | (((val) & 0x1) << 13)) ++/* Alternate Function at Port 0 Bit # (12) */ ++#define PORT_P0_ALTSEL1_P12 (0x1 << 12) ++#define PORT_P0_ALTSEL1_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_ALTSEL1_P12_GET(val) ((((val) & PORT_P0_ALTSEL1_P12) >> 12) & 0x1) ++#define PORT_P0_ALTSEL1_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P12) | (((val) & 0x1) << 12)) ++/* Alternate Function at Port 0 Bit # (11) */ ++#define PORT_P0_ALTSEL1_P11 (0x1 << 11) ++#define PORT_P0_ALTSEL1_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_ALTSEL1_P11_GET(val) ((((val) & PORT_P0_ALTSEL1_P11) >> 11) & 0x1) ++#define PORT_P0_ALTSEL1_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P11) | (((val) & 0x1) << 11)) ++/* Alternate Function at Port 0 Bit # (10) */ ++#define PORT_P0_ALTSEL1_P10 (0x1 << 10) ++#define PORT_P0_ALTSEL1_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_ALTSEL1_P10_GET(val) ((((val) & PORT_P0_ALTSEL1_P10) >> 10) & 0x1) ++#define PORT_P0_ALTSEL1_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P10) | (((val) & 0x1) << 10)) ++/* Alternate Function at Port 0 Bit # (9) */ ++#define PORT_P0_ALTSEL1_P9 (0x1 << 9) ++#define PORT_P0_ALTSEL1_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_ALTSEL1_P9_GET(val) ((((val) & PORT_P0_ALTSEL1_P9) >> 9) & 0x1) ++#define PORT_P0_ALTSEL1_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P9) | (((val) & 0x1) << 9)) ++/* Alternate Function at Port 0 Bit # (8) */ ++#define PORT_P0_ALTSEL1_P8 (0x1 << 8) ++#define PORT_P0_ALTSEL1_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_ALTSEL1_P8_GET(val) ((((val) & PORT_P0_ALTSEL1_P8) >> 8) & 0x1) ++#define PORT_P0_ALTSEL1_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P8) | (((val) & 0x1) << 8)) ++/* Alternate Function at Port 0 Bit # (7) */ ++#define PORT_P0_ALTSEL1_P7 (0x1 << 7) ++#define PORT_P0_ALTSEL1_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_ALTSEL1_P7_GET(val) ((((val) & PORT_P0_ALTSEL1_P7) >> 7) & 0x1) ++#define PORT_P0_ALTSEL1_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P7) | (((val) & 0x1) << 7)) ++/* Alternate Function at Port 0 Bit # (6) */ ++#define PORT_P0_ALTSEL1_P6 (0x1 << 6) ++#define PORT_P0_ALTSEL1_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P0_ALTSEL1_P6_GET(val) ((((val) & PORT_P0_ALTSEL1_P6) >> 6) & 0x1) ++#define PORT_P0_ALTSEL1_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P6) | (((val) & 0x1) << 6)) ++/* Alternate Function at Port 0 Bit # (3) */ ++#define PORT_P0_ALTSEL1_P3 (0x1 << 3) ++#define PORT_P0_ALTSEL1_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P0_ALTSEL1_P3_GET(val) ((((val) & PORT_P0_ALTSEL1_P3) >> 3) & 0x1) ++#define PORT_P0_ALTSEL1_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_ALTSEL1_P3) | (((val) & 0x1) << 3)) ++ ++/******************************************************************************* ++ * Port 0 Pull Up Enable Register ++ ******************************************************************************/ ++ ++/* Pull Up Device Enable at Port 0 Bit # (19) */ ++#define PORT_P0_PUEN_P19 (0x1 << 19) ++#define PORT_P0_PUEN_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_PUEN_P19_GET(val) ((((val) & PORT_P0_PUEN_P19) >> 19) & 0x1) ++#define PORT_P0_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P19) | (((val) & 0x1) << 19)) ++/* Pull Up Device Enable at Port 0 Bit # (18) */ ++#define PORT_P0_PUEN_P18 (0x1 << 18) ++#define PORT_P0_PUEN_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P0_PUEN_P18_GET(val) ((((val) & PORT_P0_PUEN_P18) >> 18) & 0x1) ++#define PORT_P0_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P18) | (((val) & 0x1) << 18)) ++/* Pull Up Device Enable at Port 0 Bit # (17) */ ++#define PORT_P0_PUEN_P17 (0x1 << 17) ++#define PORT_P0_PUEN_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_PUEN_P17_GET(val) ((((val) & PORT_P0_PUEN_P17) >> 17) & 0x1) ++#define PORT_P0_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P17) | (((val) & 0x1) << 17)) ++/* Pull Up Device Enable at Port 0 Bit # (16) */ ++#define PORT_P0_PUEN_P16 (0x1 << 16) ++#define PORT_P0_PUEN_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_PUEN_P16_GET(val) ((((val) & PORT_P0_PUEN_P16) >> 16) & 0x1) ++#define PORT_P0_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P16) | (((val) & 0x1) << 16)) ++/* Pull Up Device Enable at Port 0 Bit # (15) */ ++#define PORT_P0_PUEN_P15 (0x1 << 15) ++#define PORT_P0_PUEN_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_PUEN_P15_GET(val) ((((val) & PORT_P0_PUEN_P15) >> 15) & 0x1) ++#define PORT_P0_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P15) | (((val) & 0x1) << 15)) ++/* Pull Up Device Enable at Port 0 Bit # (14) */ ++#define PORT_P0_PUEN_P14 (0x1 << 14) ++#define PORT_P0_PUEN_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_PUEN_P14_GET(val) ((((val) & PORT_P0_PUEN_P14) >> 14) & 0x1) ++#define PORT_P0_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P14) | (((val) & 0x1) << 14)) ++/* Pull Up Device Enable at Port 0 Bit # (13) */ ++#define PORT_P0_PUEN_P13 (0x1 << 13) ++#define PORT_P0_PUEN_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_PUEN_P13_GET(val) ((((val) & PORT_P0_PUEN_P13) >> 13) & 0x1) ++#define PORT_P0_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P13) | (((val) & 0x1) << 13)) ++/* Pull Up Device Enable at Port 0 Bit # (12) */ ++#define PORT_P0_PUEN_P12 (0x1 << 12) ++#define PORT_P0_PUEN_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_PUEN_P12_GET(val) ((((val) & PORT_P0_PUEN_P12) >> 12) & 0x1) ++#define PORT_P0_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P12) | (((val) & 0x1) << 12)) ++/* Pull Up Device Enable at Port 0 Bit # (11) */ ++#define PORT_P0_PUEN_P11 (0x1 << 11) ++#define PORT_P0_PUEN_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_PUEN_P11_GET(val) ((((val) & PORT_P0_PUEN_P11) >> 11) & 0x1) ++#define PORT_P0_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P11) | (((val) & 0x1) << 11)) ++/* Pull Up Device Enable at Port 0 Bit # (10) */ ++#define PORT_P0_PUEN_P10 (0x1 << 10) ++#define PORT_P0_PUEN_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_PUEN_P10_GET(val) ((((val) & PORT_P0_PUEN_P10) >> 10) & 0x1) ++#define PORT_P0_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P10) | (((val) & 0x1) << 10)) ++/* Pull Up Device Enable at Port 0 Bit # (9) */ ++#define PORT_P0_PUEN_P9 (0x1 << 9) ++#define PORT_P0_PUEN_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_PUEN_P9_GET(val) ((((val) & PORT_P0_PUEN_P9) >> 9) & 0x1) ++#define PORT_P0_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P9) | (((val) & 0x1) << 9)) ++/* Pull Up Device Enable at Port 0 Bit # (8) */ ++#define PORT_P0_PUEN_P8 (0x1 << 8) ++#define PORT_P0_PUEN_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_PUEN_P8_GET(val) ((((val) & PORT_P0_PUEN_P8) >> 8) & 0x1) ++#define PORT_P0_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P8) | (((val) & 0x1) << 8)) ++/* Pull Up Device Enable at Port 0 Bit # (7) */ ++#define PORT_P0_PUEN_P7 (0x1 << 7) ++#define PORT_P0_PUEN_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_PUEN_P7_GET(val) ((((val) & PORT_P0_PUEN_P7) >> 7) & 0x1) ++#define PORT_P0_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P7) | (((val) & 0x1) << 7)) ++/* Pull Up Device Enable at Port 0 Bit # (6) */ ++#define PORT_P0_PUEN_P6 (0x1 << 6) ++#define PORT_P0_PUEN_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P0_PUEN_P6_GET(val) ((((val) & PORT_P0_PUEN_P6) >> 6) & 0x1) ++#define PORT_P0_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P6) | (((val) & 0x1) << 6)) ++/* Pull Up Device Enable at Port 0 Bit # (5) */ ++#define PORT_P0_PUEN_P5 (0x1 << 5) ++#define PORT_P0_PUEN_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P0_PUEN_P5_GET(val) ((((val) & PORT_P0_PUEN_P5) >> 5) & 0x1) ++#define PORT_P0_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P5) | (((val) & 0x1) << 5)) ++/* Pull Up Device Enable at Port 0 Bit # (4) */ ++#define PORT_P0_PUEN_P4 (0x1 << 4) ++#define PORT_P0_PUEN_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P0_PUEN_P4_GET(val) ((((val) & PORT_P0_PUEN_P4) >> 4) & 0x1) ++#define PORT_P0_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P4) | (((val) & 0x1) << 4)) ++/* Pull Up Device Enable at Port 0 Bit # (3) */ ++#define PORT_P0_PUEN_P3 (0x1 << 3) ++#define PORT_P0_PUEN_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P0_PUEN_P3_GET(val) ((((val) & PORT_P0_PUEN_P3) >> 3) & 0x1) ++#define PORT_P0_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P3) | (((val) & 0x1) << 3)) ++/* Pull Up Device Enable at Port 0 Bit # (2) */ ++#define PORT_P0_PUEN_P2 (0x1 << 2) ++#define PORT_P0_PUEN_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P0_PUEN_P2_GET(val) ((((val) & PORT_P0_PUEN_P2) >> 2) & 0x1) ++#define PORT_P0_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P2) | (((val) & 0x1) << 2)) ++/* Pull Up Device Enable at Port 0 Bit # (1) */ ++#define PORT_P0_PUEN_P1 (0x1 << 1) ++#define PORT_P0_PUEN_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P0_PUEN_P1_GET(val) ((((val) & PORT_P0_PUEN_P1) >> 1) & 0x1) ++#define PORT_P0_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P1) | (((val) & 0x1) << 1)) ++/* Pull Up Device Enable at Port 0 Bit # (0) */ ++#define PORT_P0_PUEN_P0 (0x1) ++#define PORT_P0_PUEN_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P0_PUEN_P0_GET(val) ((((val) & PORT_P0_PUEN_P0) >> 0) & 0x1) ++#define PORT_P0_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P0_PUEN_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * External Interrupt Control Register 0 ++ ******************************************************************************/ ++ ++/* Type of Level or Edge Detection of EXINT16 (19) */ ++#define PORT_P0_EXINTCR0_EXINT16 (0x1 << 19) ++#define PORT_P0_EXINTCR0_EXINT16_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_EXINTCR0_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT16) >> 19) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT16) | (((val) & 0x1) << 19)) ++/* Type of Level or Edge Detection of EXINT10 (17) */ ++#define PORT_P0_EXINTCR0_EXINT10 (0x1 << 17) ++#define PORT_P0_EXINTCR0_EXINT10_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_EXINTCR0_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT10) >> 17) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT10) | (((val) & 0x1) << 17)) ++/* Type of Level or Edge Detection of EXINT9 (16) */ ++#define PORT_P0_EXINTCR0_EXINT9 (0x1 << 16) ++#define PORT_P0_EXINTCR0_EXINT9_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_EXINTCR0_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT9) >> 16) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT9) | (((val) & 0x1) << 16)) ++/* Type of Level or Edge Detection of EXINT8 (15) */ ++#define PORT_P0_EXINTCR0_EXINT8 (0x1 << 15) ++#define PORT_P0_EXINTCR0_EXINT8_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_EXINTCR0_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT8) >> 15) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT8) | (((val) & 0x1) << 15)) ++/* Type of Level or Edge Detection of EXINT7 (14) */ ++#define PORT_P0_EXINTCR0_EXINT7 (0x1 << 14) ++#define PORT_P0_EXINTCR0_EXINT7_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_EXINTCR0_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT7) >> 14) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT7) | (((val) & 0x1) << 14)) ++/* Type of Level or Edge Detection of EXINT6 (13) */ ++#define PORT_P0_EXINTCR0_EXINT6 (0x1 << 13) ++#define PORT_P0_EXINTCR0_EXINT6_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_EXINTCR0_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT6) >> 13) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT6) | (((val) & 0x1) << 13)) ++/* Type of Level or Edge Detection of EXINT5 (12) */ ++#define PORT_P0_EXINTCR0_EXINT5 (0x1 << 12) ++#define PORT_P0_EXINTCR0_EXINT5_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_EXINTCR0_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT5) >> 12) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT5) | (((val) & 0x1) << 12)) ++/* Type of Level or Edge Detection of EXINT4 (11) */ ++#define PORT_P0_EXINTCR0_EXINT4 (0x1 << 11) ++#define PORT_P0_EXINTCR0_EXINT4_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_EXINTCR0_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT4) >> 11) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT4) | (((val) & 0x1) << 11)) ++/* Type of Level or Edge Detection of EXINT3 (10) */ ++#define PORT_P0_EXINTCR0_EXINT3 (0x1 << 10) ++#define PORT_P0_EXINTCR0_EXINT3_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_EXINTCR0_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT3) >> 10) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT3) | (((val) & 0x1) << 10)) ++/* Type of Level or Edge Detection of EXINT2 (9) */ ++#define PORT_P0_EXINTCR0_EXINT2 (0x1 << 9) ++#define PORT_P0_EXINTCR0_EXINT2_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_EXINTCR0_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT2) >> 9) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT2) | (((val) & 0x1) << 9)) ++/* Type of Level or Edge Detection of EXINT1 (8) */ ++#define PORT_P0_EXINTCR0_EXINT1 (0x1 << 8) ++#define PORT_P0_EXINTCR0_EXINT1_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_EXINTCR0_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT1) >> 8) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT1) | (((val) & 0x1) << 8)) ++/* Type of Level or Edge Detection of EXINT0 (7) */ ++#define PORT_P0_EXINTCR0_EXINT0 (0x1 << 7) ++#define PORT_P0_EXINTCR0_EXINT0_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_EXINTCR0_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR0_EXINT0) >> 7) & 0x1) ++#define PORT_P0_EXINTCR0_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR0_EXINT0) | (((val) & 0x1) << 7)) ++ ++/******************************************************************************* ++ * External Interrupt Control Register 1 ++ ******************************************************************************/ ++ ++/* Type of Level or Edge Detection of EXINT16 (19) */ ++#define PORT_P0_EXINTCR1_EXINT16 (0x1 << 19) ++#define PORT_P0_EXINTCR1_EXINT16_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_EXINTCR1_EXINT16_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT16) >> 19) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT16) | (((val) & 0x1) << 19)) ++/* Type of Level or Edge Detection of EXINT10 (17) */ ++#define PORT_P0_EXINTCR1_EXINT10 (0x1 << 17) ++#define PORT_P0_EXINTCR1_EXINT10_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_EXINTCR1_EXINT10_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT10) >> 17) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT10) | (((val) & 0x1) << 17)) ++/* Type of Level or Edge Detection of EXINT9 (16) */ ++#define PORT_P0_EXINTCR1_EXINT9 (0x1 << 16) ++#define PORT_P0_EXINTCR1_EXINT9_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_EXINTCR1_EXINT9_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT9) >> 16) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT9) | (((val) & 0x1) << 16)) ++/* Type of Level or Edge Detection of EXINT8 (15) */ ++#define PORT_P0_EXINTCR1_EXINT8 (0x1 << 15) ++#define PORT_P0_EXINTCR1_EXINT8_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_EXINTCR1_EXINT8_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT8) >> 15) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT8) | (((val) & 0x1) << 15)) ++/* Type of Level or Edge Detection of EXINT7 (14) */ ++#define PORT_P0_EXINTCR1_EXINT7 (0x1 << 14) ++#define PORT_P0_EXINTCR1_EXINT7_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_EXINTCR1_EXINT7_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT7) >> 14) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT7) | (((val) & 0x1) << 14)) ++/* Type of Level or Edge Detection of EXINT6 (13) */ ++#define PORT_P0_EXINTCR1_EXINT6 (0x1 << 13) ++#define PORT_P0_EXINTCR1_EXINT6_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_EXINTCR1_EXINT6_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT6) >> 13) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT6) | (((val) & 0x1) << 13)) ++/* Type of Level or Edge Detection of EXINT5 (12) */ ++#define PORT_P0_EXINTCR1_EXINT5 (0x1 << 12) ++#define PORT_P0_EXINTCR1_EXINT5_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_EXINTCR1_EXINT5_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT5) >> 12) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT5) | (((val) & 0x1) << 12)) ++/* Type of Level or Edge Detection of EXINT4 (11) */ ++#define PORT_P0_EXINTCR1_EXINT4 (0x1 << 11) ++#define PORT_P0_EXINTCR1_EXINT4_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_EXINTCR1_EXINT4_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT4) >> 11) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT4) | (((val) & 0x1) << 11)) ++/* Type of Level or Edge Detection of EXINT3 (10) */ ++#define PORT_P0_EXINTCR1_EXINT3 (0x1 << 10) ++#define PORT_P0_EXINTCR1_EXINT3_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_EXINTCR1_EXINT3_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT3) >> 10) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT3) | (((val) & 0x1) << 10)) ++/* Type of Level or Edge Detection of EXINT2 (9) */ ++#define PORT_P0_EXINTCR1_EXINT2 (0x1 << 9) ++#define PORT_P0_EXINTCR1_EXINT2_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_EXINTCR1_EXINT2_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT2) >> 9) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT2) | (((val) & 0x1) << 9)) ++/* Type of Level or Edge Detection of EXINT1 (8) */ ++#define PORT_P0_EXINTCR1_EXINT1 (0x1 << 8) ++#define PORT_P0_EXINTCR1_EXINT1_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_EXINTCR1_EXINT1_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT1) >> 8) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT1) | (((val) & 0x1) << 8)) ++/* Type of Level or Edge Detection of EXINT0 (7) */ ++#define PORT_P0_EXINTCR1_EXINT0 (0x1 << 7) ++#define PORT_P0_EXINTCR1_EXINT0_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_EXINTCR1_EXINT0_GET(val) ((((val) & PORT_P0_EXINTCR1_EXINT0) >> 7) & 0x1) ++#define PORT_P0_EXINTCR1_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_EXINTCR1_EXINT0) | (((val) & 0x1) << 7)) ++ ++/******************************************************************************* ++ * P0_IRNEN Register ++ ******************************************************************************/ ++ ++/* EXINT16 Interrupt Request Enable (19) */ ++#define PORT_P0_IRNEN_EXINT16 (0x1 << 19) ++#define PORT_P0_IRNEN_EXINT16_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_IRNEN_EXINT16_GET(val) ((((val) & PORT_P0_IRNEN_EXINT16) >> 19) & 0x1) ++#define PORT_P0_IRNEN_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT16) | (((val) & 0x1) << 19)) ++/* EXINT10 Interrupt Request Enable (17) */ ++#define PORT_P0_IRNEN_EXINT10 (0x1 << 17) ++#define PORT_P0_IRNEN_EXINT10_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_IRNEN_EXINT10_GET(val) ((((val) & PORT_P0_IRNEN_EXINT10) >> 17) & 0x1) ++#define PORT_P0_IRNEN_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT10) | (((val) & 0x1) << 17)) ++/* EXINT9 Interrupt Request Enable (16) */ ++#define PORT_P0_IRNEN_EXINT9 (0x1 << 16) ++#define PORT_P0_IRNEN_EXINT9_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_IRNEN_EXINT9_GET(val) ((((val) & PORT_P0_IRNEN_EXINT9) >> 16) & 0x1) ++#define PORT_P0_IRNEN_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT9) | (((val) & 0x1) << 16)) ++/* EXINT8 Interrupt Request Enable (15) */ ++#define PORT_P0_IRNEN_EXINT8 (0x1 << 15) ++#define PORT_P0_IRNEN_EXINT8_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_IRNEN_EXINT8_GET(val) ((((val) & PORT_P0_IRNEN_EXINT8) >> 15) & 0x1) ++#define PORT_P0_IRNEN_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT8) | (((val) & 0x1) << 15)) ++/* EXINT7 Interrupt Request Enable (14) */ ++#define PORT_P0_IRNEN_EXINT7 (0x1 << 14) ++#define PORT_P0_IRNEN_EXINT7_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_IRNEN_EXINT7_GET(val) ((((val) & PORT_P0_IRNEN_EXINT7) >> 14) & 0x1) ++#define PORT_P0_IRNEN_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT7) | (((val) & 0x1) << 14)) ++/* EXINT6 Interrupt Request Enable (13) */ ++#define PORT_P0_IRNEN_EXINT6 (0x1 << 13) ++#define PORT_P0_IRNEN_EXINT6_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_IRNEN_EXINT6_GET(val) ((((val) & PORT_P0_IRNEN_EXINT6) >> 13) & 0x1) ++#define PORT_P0_IRNEN_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT6) | (((val) & 0x1) << 13)) ++/* EXINT5 Interrupt Request Enable (12) */ ++#define PORT_P0_IRNEN_EXINT5 (0x1 << 12) ++#define PORT_P0_IRNEN_EXINT5_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_IRNEN_EXINT5_GET(val) ((((val) & PORT_P0_IRNEN_EXINT5) >> 12) & 0x1) ++#define PORT_P0_IRNEN_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT5) | (((val) & 0x1) << 12)) ++/* EXINT4 Interrupt Request Enable (11) */ ++#define PORT_P0_IRNEN_EXINT4 (0x1 << 11) ++#define PORT_P0_IRNEN_EXINT4_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_IRNEN_EXINT4_GET(val) ((((val) & PORT_P0_IRNEN_EXINT4) >> 11) & 0x1) ++#define PORT_P0_IRNEN_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT4) | (((val) & 0x1) << 11)) ++/* EXINT3 Interrupt Request Enable (10) */ ++#define PORT_P0_IRNEN_EXINT3 (0x1 << 10) ++#define PORT_P0_IRNEN_EXINT3_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_IRNEN_EXINT3_GET(val) ((((val) & PORT_P0_IRNEN_EXINT3) >> 10) & 0x1) ++#define PORT_P0_IRNEN_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT3) | (((val) & 0x1) << 10)) ++/* EXINT2 Interrupt Request Enable (9) */ ++#define PORT_P0_IRNEN_EXINT2 (0x1 << 9) ++#define PORT_P0_IRNEN_EXINT2_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_IRNEN_EXINT2_GET(val) ((((val) & PORT_P0_IRNEN_EXINT2) >> 9) & 0x1) ++#define PORT_P0_IRNEN_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT2) | (((val) & 0x1) << 9)) ++/* EXINT1 Interrupt Request Enable (8) */ ++#define PORT_P0_IRNEN_EXINT1 (0x1 << 8) ++#define PORT_P0_IRNEN_EXINT1_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_IRNEN_EXINT1_GET(val) ((((val) & PORT_P0_IRNEN_EXINT1) >> 8) & 0x1) ++#define PORT_P0_IRNEN_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT1) | (((val) & 0x1) << 8)) ++/* EXINT0 Interrupt Request Enable (7) */ ++#define PORT_P0_IRNEN_EXINT0 (0x1 << 7) ++#define PORT_P0_IRNEN_EXINT0_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_IRNEN_EXINT0_GET(val) ((((val) & PORT_P0_IRNEN_EXINT0) >> 7) & 0x1) ++#define PORT_P0_IRNEN_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNEN_EXINT0) | (((val) & 0x1) << 7)) ++ ++/******************************************************************************* ++ * P0_IRNICR Register ++ ******************************************************************************/ ++ ++/* EXINT16 Interrupt Request (19) */ ++#define PORT_P0_IRNICR_EXINT16 (0x1 << 19) ++#define PORT_P0_IRNICR_EXINT16_GET(val) ((((val) & PORT_P0_IRNICR_EXINT16) >> 19) & 0x1) ++/* EXINT10 Interrupt Request (17) */ ++#define PORT_P0_IRNICR_EXINT10 (0x1 << 17) ++#define PORT_P0_IRNICR_EXINT10_GET(val) ((((val) & PORT_P0_IRNICR_EXINT10) >> 17) & 0x1) ++/* EXINT9 Interrupt Request (16) */ ++#define PORT_P0_IRNICR_EXINT9 (0x1 << 16) ++#define PORT_P0_IRNICR_EXINT9_GET(val) ((((val) & PORT_P0_IRNICR_EXINT9) >> 16) & 0x1) ++/* EXINT8 Interrupt Request (15) */ ++#define PORT_P0_IRNICR_EXINT8 (0x1 << 15) ++#define PORT_P0_IRNICR_EXINT8_GET(val) ((((val) & PORT_P0_IRNICR_EXINT8) >> 15) & 0x1) ++/* EXINT7 Interrupt Request (14) */ ++#define PORT_P0_IRNICR_EXINT7 (0x1 << 14) ++#define PORT_P0_IRNICR_EXINT7_GET(val) ((((val) & PORT_P0_IRNICR_EXINT7) >> 14) & 0x1) ++/* EXINT6 Interrupt Request (13) */ ++#define PORT_P0_IRNICR_EXINT6 (0x1 << 13) ++#define PORT_P0_IRNICR_EXINT6_GET(val) ((((val) & PORT_P0_IRNICR_EXINT6) >> 13) & 0x1) ++/* EXINT5 Interrupt Request (12) */ ++#define PORT_P0_IRNICR_EXINT5 (0x1 << 12) ++#define PORT_P0_IRNICR_EXINT5_GET(val) ((((val) & PORT_P0_IRNICR_EXINT5) >> 12) & 0x1) ++/* EXINT4 Interrupt Request (11) */ ++#define PORT_P0_IRNICR_EXINT4 (0x1 << 11) ++#define PORT_P0_IRNICR_EXINT4_GET(val) ((((val) & PORT_P0_IRNICR_EXINT4) >> 11) & 0x1) ++/* EXINT3 Interrupt Request (10) */ ++#define PORT_P0_IRNICR_EXINT3 (0x1 << 10) ++#define PORT_P0_IRNICR_EXINT3_GET(val) ((((val) & PORT_P0_IRNICR_EXINT3) >> 10) & 0x1) ++/* EXINT2 Interrupt Request (9) */ ++#define PORT_P0_IRNICR_EXINT2 (0x1 << 9) ++#define PORT_P0_IRNICR_EXINT2_GET(val) ((((val) & PORT_P0_IRNICR_EXINT2) >> 9) & 0x1) ++/* EXINT1 Interrupt Request (8) */ ++#define PORT_P0_IRNICR_EXINT1 (0x1 << 8) ++#define PORT_P0_IRNICR_EXINT1_GET(val) ((((val) & PORT_P0_IRNICR_EXINT1) >> 8) & 0x1) ++/* EXINT0 Interrupt Request (7) */ ++#define PORT_P0_IRNICR_EXINT0 (0x1 << 7) ++#define PORT_P0_IRNICR_EXINT0_GET(val) ((((val) & PORT_P0_IRNICR_EXINT0) >> 7) & 0x1) ++ ++/******************************************************************************* ++ * P0_IRNCR Register ++ ******************************************************************************/ ++ ++/* EXINT16 Interrupt Request (19) */ ++#define PORT_P0_IRNCR_EXINT16 (0x1 << 19) ++#define PORT_P0_IRNCR_EXINT16_GET(val) ((((val) & PORT_P0_IRNCR_EXINT16) >> 19) & 0x1) ++/* EXINT10 Interrupt Request (17) */ ++#define PORT_P0_IRNCR_EXINT10 (0x1 << 17) ++#define PORT_P0_IRNCR_EXINT10_GET(val) ((((val) & PORT_P0_IRNCR_EXINT10) >> 17) & 0x1) ++/* EXINT9 Interrupt Request (16) */ ++#define PORT_P0_IRNCR_EXINT9 (0x1 << 16) ++#define PORT_P0_IRNCR_EXINT9_GET(val) ((((val) & PORT_P0_IRNCR_EXINT9) >> 16) & 0x1) ++/* EXINT8 Interrupt Request (15) */ ++#define PORT_P0_IRNCR_EXINT8 (0x1 << 15) ++#define PORT_P0_IRNCR_EXINT8_GET(val) ((((val) & PORT_P0_IRNCR_EXINT8) >> 15) & 0x1) ++/* EXINT7 Interrupt Request (14) */ ++#define PORT_P0_IRNCR_EXINT7 (0x1 << 14) ++#define PORT_P0_IRNCR_EXINT7_GET(val) ((((val) & PORT_P0_IRNCR_EXINT7) >> 14) & 0x1) ++/* EXINT6 Interrupt Request (13) */ ++#define PORT_P0_IRNCR_EXINT6 (0x1 << 13) ++#define PORT_P0_IRNCR_EXINT6_GET(val) ((((val) & PORT_P0_IRNCR_EXINT6) >> 13) & 0x1) ++/* EXINT5 Interrupt Request (12) */ ++#define PORT_P0_IRNCR_EXINT5 (0x1 << 12) ++#define PORT_P0_IRNCR_EXINT5_GET(val) ((((val) & PORT_P0_IRNCR_EXINT5) >> 12) & 0x1) ++/* EXINT4 Interrupt Request (11) */ ++#define PORT_P0_IRNCR_EXINT4 (0x1 << 11) ++#define PORT_P0_IRNCR_EXINT4_GET(val) ((((val) & PORT_P0_IRNCR_EXINT4) >> 11) & 0x1) ++/* EXINT3 Interrupt Request (10) */ ++#define PORT_P0_IRNCR_EXINT3 (0x1 << 10) ++#define PORT_P0_IRNCR_EXINT3_GET(val) ((((val) & PORT_P0_IRNCR_EXINT3) >> 10) & 0x1) ++/* EXINT2 Interrupt Request (9) */ ++#define PORT_P0_IRNCR_EXINT2 (0x1 << 9) ++#define PORT_P0_IRNCR_EXINT2_GET(val) ((((val) & PORT_P0_IRNCR_EXINT2) >> 9) & 0x1) ++/* EXINT1 Interrupt Request (8) */ ++#define PORT_P0_IRNCR_EXINT1 (0x1 << 8) ++#define PORT_P0_IRNCR_EXINT1_GET(val) ((((val) & PORT_P0_IRNCR_EXINT1) >> 8) & 0x1) ++/* EXINT0 Interrupt Request (7) */ ++#define PORT_P0_IRNCR_EXINT0 (0x1 << 7) ++#define PORT_P0_IRNCR_EXINT0_GET(val) ((((val) & PORT_P0_IRNCR_EXINT0) >> 7) & 0x1) ++ ++/******************************************************************************* ++ * P0 External Event Detection Configuration Register ++ ******************************************************************************/ ++ ++/* EXINT16 configured for Edge or Level Detection (19) */ ++#define PORT_P0_IRNCFG_EXINT16 (0x1 << 19) ++#define PORT_P0_IRNCFG_EXINT16_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_IRNCFG_EXINT16_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT16) >> 19) & 0x1) ++#define PORT_P0_IRNCFG_EXINT16_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT16) | (((val) & 0x1) << 19)) ++/* EXINT10 configured for Edge or Level Detection (17) */ ++#define PORT_P0_IRNCFG_EXINT10 (0x1 << 17) ++#define PORT_P0_IRNCFG_EXINT10_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_IRNCFG_EXINT10_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT10) >> 17) & 0x1) ++#define PORT_P0_IRNCFG_EXINT10_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT10) | (((val) & 0x1) << 17)) ++/* EXINT9 configured for Edge or Level Detection (16) */ ++#define PORT_P0_IRNCFG_EXINT9 (0x1 << 16) ++#define PORT_P0_IRNCFG_EXINT9_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_IRNCFG_EXINT9_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT9) >> 16) & 0x1) ++#define PORT_P0_IRNCFG_EXINT9_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT9) | (((val) & 0x1) << 16)) ++/* EXINT8 configured for Edge or Level Detection (15) */ ++#define PORT_P0_IRNCFG_EXINT8 (0x1 << 15) ++#define PORT_P0_IRNCFG_EXINT8_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_IRNCFG_EXINT8_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT8) >> 15) & 0x1) ++#define PORT_P0_IRNCFG_EXINT8_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT8) | (((val) & 0x1) << 15)) ++/* EXINT7 configured for Edge or Level Detection (14) */ ++#define PORT_P0_IRNCFG_EXINT7 (0x1 << 14) ++#define PORT_P0_IRNCFG_EXINT7_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_IRNCFG_EXINT7_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT7) >> 14) & 0x1) ++#define PORT_P0_IRNCFG_EXINT7_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT7) | (((val) & 0x1) << 14)) ++/* EXINT6 configured for Edge or Level Detection (13) */ ++#define PORT_P0_IRNCFG_EXINT6 (0x1 << 13) ++#define PORT_P0_IRNCFG_EXINT6_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_IRNCFG_EXINT6_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT6) >> 13) & 0x1) ++#define PORT_P0_IRNCFG_EXINT6_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT6) | (((val) & 0x1) << 13)) ++/* EXINT5 configured for Edge or Level Detection (12) */ ++#define PORT_P0_IRNCFG_EXINT5 (0x1 << 12) ++#define PORT_P0_IRNCFG_EXINT5_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_IRNCFG_EXINT5_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT5) >> 12) & 0x1) ++#define PORT_P0_IRNCFG_EXINT5_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT5) | (((val) & 0x1) << 12)) ++/* EXINT4 configured for Edge or Level Detection (11) */ ++#define PORT_P0_IRNCFG_EXINT4 (0x1 << 11) ++#define PORT_P0_IRNCFG_EXINT4_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_IRNCFG_EXINT4_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT4) >> 11) & 0x1) ++#define PORT_P0_IRNCFG_EXINT4_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT4) | (((val) & 0x1) << 11)) ++/* EXINT3 configured for Edge or Level Detection (10) */ ++#define PORT_P0_IRNCFG_EXINT3 (0x1 << 10) ++#define PORT_P0_IRNCFG_EXINT3_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_IRNCFG_EXINT3_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT3) >> 10) & 0x1) ++#define PORT_P0_IRNCFG_EXINT3_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT3) | (((val) & 0x1) << 10)) ++/* EXINT2 configured for Edge or Level Detection (9) */ ++#define PORT_P0_IRNCFG_EXINT2 (0x1 << 9) ++#define PORT_P0_IRNCFG_EXINT2_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_IRNCFG_EXINT2_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT2) >> 9) & 0x1) ++#define PORT_P0_IRNCFG_EXINT2_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT2) | (((val) & 0x1) << 9)) ++/* EXINT1 configured for Edge or Level Detection (8) */ ++#define PORT_P0_IRNCFG_EXINT1 (0x1 << 8) ++#define PORT_P0_IRNCFG_EXINT1_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_IRNCFG_EXINT1_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT1) >> 8) & 0x1) ++#define PORT_P0_IRNCFG_EXINT1_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT1) | (((val) & 0x1) << 8)) ++/* EXINT0 configured for Edge or Level Detection (7) */ ++#define PORT_P0_IRNCFG_EXINT0 (0x1 << 7) ++#define PORT_P0_IRNCFG_EXINT0_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_IRNCFG_EXINT0_GET(val) ((((val) & PORT_P0_IRNCFG_EXINT0) >> 7) & 0x1) ++#define PORT_P0_IRNCFG_EXINT0_SET(reg,val) (reg) = ((reg & ~PORT_P0_IRNCFG_EXINT0) | (((val) & 0x1) << 7)) ++ ++/******************************************************************************* ++ * P0_IRNENSET Register ++ ******************************************************************************/ ++ ++/* Set Interrupt Node Enable Flag EXINT16 (19) */ ++#define PORT_P0_IRNENSET_EXINT16 (0x1 << 19) ++#define PORT_P0_IRNENSET_EXINT16_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_IRNENSET_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT16) | (val) & 1) << 19) ++/* Set Interrupt Node Enable Flag EXINT10 (17) */ ++#define PORT_P0_IRNENSET_EXINT10 (0x1 << 17) ++#define PORT_P0_IRNENSET_EXINT10_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_IRNENSET_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT10) | (val) & 1) << 17) ++/* Set Interrupt Node Enable Flag EXINT9 (16) */ ++#define PORT_P0_IRNENSET_EXINT9 (0x1 << 16) ++#define PORT_P0_IRNENSET_EXINT9_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_IRNENSET_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT9) | (val) & 1) << 16) ++/* Set Interrupt Node Enable Flag EXINT8 (15) */ ++#define PORT_P0_IRNENSET_EXINT8 (0x1 << 15) ++#define PORT_P0_IRNENSET_EXINT8_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_IRNENSET_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT8) | (val) & 1) << 15) ++/* Set Interrupt Node Enable Flag EXINT7 (14) */ ++#define PORT_P0_IRNENSET_EXINT7 (0x1 << 14) ++#define PORT_P0_IRNENSET_EXINT7_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_IRNENSET_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT7) | (val) & 1) << 14) ++/* Set Interrupt Node Enable Flag EXINT6 (13) */ ++#define PORT_P0_IRNENSET_EXINT6 (0x1 << 13) ++#define PORT_P0_IRNENSET_EXINT6_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_IRNENSET_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT6) | (val) & 1) << 13) ++/* Set Interrupt Node Enable Flag EXINT5 (12) */ ++#define PORT_P0_IRNENSET_EXINT5 (0x1 << 12) ++#define PORT_P0_IRNENSET_EXINT5_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_IRNENSET_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT5) | (val) & 1) << 12) ++/* Set Interrupt Node Enable Flag EXINT4 (11) */ ++#define PORT_P0_IRNENSET_EXINT4 (0x1 << 11) ++#define PORT_P0_IRNENSET_EXINT4_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_IRNENSET_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT4) | (val) & 1) << 11) ++/* Set Interrupt Node Enable Flag EXINT3 (10) */ ++#define PORT_P0_IRNENSET_EXINT3 (0x1 << 10) ++#define PORT_P0_IRNENSET_EXINT3_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_IRNENSET_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT3) | (val) & 1) << 10) ++/* Set Interrupt Node Enable Flag EXINT2 (9) */ ++#define PORT_P0_IRNENSET_EXINT2 (0x1 << 9) ++#define PORT_P0_IRNENSET_EXINT2_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_IRNENSET_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT2) | (val) & 1) << 9) ++/* Set Interrupt Node Enable Flag EXINT1 (8) */ ++#define PORT_P0_IRNENSET_EXINT1 (0x1 << 8) ++#define PORT_P0_IRNENSET_EXINT1_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_IRNENSET_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT1) | (val) & 1) << 8) ++/* Set Interrupt Node Enable Flag EXINT0 (7) */ ++#define PORT_P0_IRNENSET_EXINT0 (0x1 << 7) ++#define PORT_P0_IRNENSET_EXINT0_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_IRNENSET_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENSET_EXINT0) | (val) & 1) << 7) ++ ++/******************************************************************************* ++ * P0_IRNENCLR Register ++ ******************************************************************************/ ++ ++/* Clear Interrupt Node Enable Flag EXINT16 (19) */ ++#define PORT_P0_IRNENCLR_EXINT16 (0x1 << 19) ++#define PORT_P0_IRNENCLR_EXINT16_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P0_IRNENCLR_EXINT16_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT16) | (val) & 1) << 19) ++/* Clear Interrupt Node Enable Flag EXINT10 (17) */ ++#define PORT_P0_IRNENCLR_EXINT10 (0x1 << 17) ++#define PORT_P0_IRNENCLR_EXINT10_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P0_IRNENCLR_EXINT10_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT10) | (val) & 1) << 17) ++/* Clear Interrupt Node Enable Flag EXINT9 (16) */ ++#define PORT_P0_IRNENCLR_EXINT9 (0x1 << 16) ++#define PORT_P0_IRNENCLR_EXINT9_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P0_IRNENCLR_EXINT9_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT9) | (val) & 1) << 16) ++/* Clear Interrupt Node Enable Flag EXINT8 (15) */ ++#define PORT_P0_IRNENCLR_EXINT8 (0x1 << 15) ++#define PORT_P0_IRNENCLR_EXINT8_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P0_IRNENCLR_EXINT8_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT8) | (val) & 1) << 15) ++/* Clear Interrupt Node Enable Flag EXINT7 (14) */ ++#define PORT_P0_IRNENCLR_EXINT7 (0x1 << 14) ++#define PORT_P0_IRNENCLR_EXINT7_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P0_IRNENCLR_EXINT7_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT7) | (val) & 1) << 14) ++/* Clear Interrupt Node Enable Flag EXINT6 (13) */ ++#define PORT_P0_IRNENCLR_EXINT6 (0x1 << 13) ++#define PORT_P0_IRNENCLR_EXINT6_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P0_IRNENCLR_EXINT6_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT6) | (val) & 1) << 13) ++/* Clear Interrupt Node Enable Flag EXINT5 (12) */ ++#define PORT_P0_IRNENCLR_EXINT5 (0x1 << 12) ++#define PORT_P0_IRNENCLR_EXINT5_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P0_IRNENCLR_EXINT5_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT5) | (val) & 1) << 12) ++/* Clear Interrupt Node Enable Flag EXINT4 (11) */ ++#define PORT_P0_IRNENCLR_EXINT4 (0x1 << 11) ++#define PORT_P0_IRNENCLR_EXINT4_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P0_IRNENCLR_EXINT4_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT4) | (val) & 1) << 11) ++/* Clear Interrupt Node Enable Flag EXINT3 (10) */ ++#define PORT_P0_IRNENCLR_EXINT3 (0x1 << 10) ++#define PORT_P0_IRNENCLR_EXINT3_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P0_IRNENCLR_EXINT3_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT3) | (val) & 1) << 10) ++/* Clear Interrupt Node Enable Flag EXINT2 (9) */ ++#define PORT_P0_IRNENCLR_EXINT2 (0x1 << 9) ++#define PORT_P0_IRNENCLR_EXINT2_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P0_IRNENCLR_EXINT2_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT2) | (val) & 1) << 9) ++/* Clear Interrupt Node Enable Flag EXINT1 (8) */ ++#define PORT_P0_IRNENCLR_EXINT1 (0x1 << 8) ++#define PORT_P0_IRNENCLR_EXINT1_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P0_IRNENCLR_EXINT1_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT1) | (val) & 1) << 8) ++/* Clear Interrupt Node Enable Flag EXINT0 (7) */ ++#define PORT_P0_IRNENCLR_EXINT0 (0x1 << 7) ++#define PORT_P0_IRNENCLR_EXINT0_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P0_IRNENCLR_EXINT0_SET(reg,val) (reg) = (((reg & ~PORT_P0_IRNENCLR_EXINT0) | (val) & 1) << 7) ++ ++/******************************************************************************* ++ * Port 1 Data Output Register ++ ******************************************************************************/ ++ ++/* Port 1 Pin # Output Value (19) */ ++#define PORT_P1_OUT_P19 (0x1 << 19) ++#define PORT_P1_OUT_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_OUT_P19_GET(val) ((((val) & PORT_P1_OUT_P19) >> 19) & 0x1) ++#define PORT_P1_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P19) | (((val) & 0x1) << 19)) ++/* Port 1 Pin # Output Value (18) */ ++#define PORT_P1_OUT_P18 (0x1 << 18) ++#define PORT_P1_OUT_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_OUT_P18_GET(val) ((((val) & PORT_P1_OUT_P18) >> 18) & 0x1) ++#define PORT_P1_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P18) | (((val) & 0x1) << 18)) ++/* Port 1 Pin # Output Value (17) */ ++#define PORT_P1_OUT_P17 (0x1 << 17) ++#define PORT_P1_OUT_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_OUT_P17_GET(val) ((((val) & PORT_P1_OUT_P17) >> 17) & 0x1) ++#define PORT_P1_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P17) | (((val) & 0x1) << 17)) ++/* Port 1 Pin # Output Value (16) */ ++#define PORT_P1_OUT_P16 (0x1 << 16) ++#define PORT_P1_OUT_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_OUT_P16_GET(val) ((((val) & PORT_P1_OUT_P16) >> 16) & 0x1) ++#define PORT_P1_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P16) | (((val) & 0x1) << 16)) ++/* Port 1 Pin # Output Value (15) */ ++#define PORT_P1_OUT_P15 (0x1 << 15) ++#define PORT_P1_OUT_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_OUT_P15_GET(val) ((((val) & PORT_P1_OUT_P15) >> 15) & 0x1) ++#define PORT_P1_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P15) | (((val) & 0x1) << 15)) ++/* Port 1 Pin # Output Value (14) */ ++#define PORT_P1_OUT_P14 (0x1 << 14) ++#define PORT_P1_OUT_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P1_OUT_P14_GET(val) ((((val) & PORT_P1_OUT_P14) >> 14) & 0x1) ++#define PORT_P1_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P14) | (((val) & 0x1) << 14)) ++/* Port 1 Pin # Output Value (13) */ ++#define PORT_P1_OUT_P13 (0x1 << 13) ++#define PORT_P1_OUT_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P1_OUT_P13_GET(val) ((((val) & PORT_P1_OUT_P13) >> 13) & 0x1) ++#define PORT_P1_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P13) | (((val) & 0x1) << 13)) ++/* Port 1 Pin # Output Value (12) */ ++#define PORT_P1_OUT_P12 (0x1 << 12) ++#define PORT_P1_OUT_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P1_OUT_P12_GET(val) ((((val) & PORT_P1_OUT_P12) >> 12) & 0x1) ++#define PORT_P1_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P12) | (((val) & 0x1) << 12)) ++/* Port 1 Pin # Output Value (11) */ ++#define PORT_P1_OUT_P11 (0x1 << 11) ++#define PORT_P1_OUT_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P1_OUT_P11_GET(val) ((((val) & PORT_P1_OUT_P11) >> 11) & 0x1) ++#define PORT_P1_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P11) | (((val) & 0x1) << 11)) ++/* Port 1 Pin # Output Value (10) */ ++#define PORT_P1_OUT_P10 (0x1 << 10) ++#define PORT_P1_OUT_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P1_OUT_P10_GET(val) ((((val) & PORT_P1_OUT_P10) >> 10) & 0x1) ++#define PORT_P1_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P10) | (((val) & 0x1) << 10)) ++/* Port 1 Pin # Output Value (9) */ ++#define PORT_P1_OUT_P9 (0x1 << 9) ++#define PORT_P1_OUT_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P1_OUT_P9_GET(val) ((((val) & PORT_P1_OUT_P9) >> 9) & 0x1) ++#define PORT_P1_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P9) | (((val) & 0x1) << 9)) ++/* Port 1 Pin # Output Value (8) */ ++#define PORT_P1_OUT_P8 (0x1 << 8) ++#define PORT_P1_OUT_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P1_OUT_P8_GET(val) ((((val) & PORT_P1_OUT_P8) >> 8) & 0x1) ++#define PORT_P1_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P8) | (((val) & 0x1) << 8)) ++/* Port 1 Pin # Output Value (7) */ ++#define PORT_P1_OUT_P7 (0x1 << 7) ++#define PORT_P1_OUT_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P1_OUT_P7_GET(val) ((((val) & PORT_P1_OUT_P7) >> 7) & 0x1) ++#define PORT_P1_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P7) | (((val) & 0x1) << 7)) ++/* Port 1 Pin # Output Value (6) */ ++#define PORT_P1_OUT_P6 (0x1 << 6) ++#define PORT_P1_OUT_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P1_OUT_P6_GET(val) ((((val) & PORT_P1_OUT_P6) >> 6) & 0x1) ++#define PORT_P1_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P6) | (((val) & 0x1) << 6)) ++/* Port 1 Pin # Output Value (5) */ ++#define PORT_P1_OUT_P5 (0x1 << 5) ++#define PORT_P1_OUT_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P1_OUT_P5_GET(val) ((((val) & PORT_P1_OUT_P5) >> 5) & 0x1) ++#define PORT_P1_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P5) | (((val) & 0x1) << 5)) ++/* Port 1 Pin # Output Value (4) */ ++#define PORT_P1_OUT_P4 (0x1 << 4) ++#define PORT_P1_OUT_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P1_OUT_P4_GET(val) ((((val) & PORT_P1_OUT_P4) >> 4) & 0x1) ++#define PORT_P1_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P4) | (((val) & 0x1) << 4)) ++/* Port 1 Pin # Output Value (3) */ ++#define PORT_P1_OUT_P3 (0x1 << 3) ++#define PORT_P1_OUT_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P1_OUT_P3_GET(val) ((((val) & PORT_P1_OUT_P3) >> 3) & 0x1) ++#define PORT_P1_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P3) | (((val) & 0x1) << 3)) ++/* Port 1 Pin # Output Value (2) */ ++#define PORT_P1_OUT_P2 (0x1 << 2) ++#define PORT_P1_OUT_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P1_OUT_P2_GET(val) ((((val) & PORT_P1_OUT_P2) >> 2) & 0x1) ++#define PORT_P1_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P2) | (((val) & 0x1) << 2)) ++/* Port 1 Pin # Output Value (1) */ ++#define PORT_P1_OUT_P1 (0x1 << 1) ++#define PORT_P1_OUT_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P1_OUT_P1_GET(val) ((((val) & PORT_P1_OUT_P1) >> 1) & 0x1) ++#define PORT_P1_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P1) | (((val) & 0x1) << 1)) ++/* Port 1 Pin # Output Value (0) */ ++#define PORT_P1_OUT_P0 (0x1) ++#define PORT_P1_OUT_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P1_OUT_P0_GET(val) ((((val) & PORT_P1_OUT_P0) >> 0) & 0x1) ++#define PORT_P1_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_OUT_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 1 Data Input Register ++ ******************************************************************************/ ++ ++/* Port 1 Pin # Latched Input Value (19) */ ++#define PORT_P1_IN_P19 (0x1 << 19) ++#define PORT_P1_IN_P19_GET(val) ((((val) & PORT_P1_IN_P19) >> 19) & 0x1) ++/* Port 1 Pin # Latched Input Value (18) */ ++#define PORT_P1_IN_P18 (0x1 << 18) ++#define PORT_P1_IN_P18_GET(val) ((((val) & PORT_P1_IN_P18) >> 18) & 0x1) ++/* Port 1 Pin # Latched Input Value (17) */ ++#define PORT_P1_IN_P17 (0x1 << 17) ++#define PORT_P1_IN_P17_GET(val) ((((val) & PORT_P1_IN_P17) >> 17) & 0x1) ++/* Port 1 Pin # Latched Input Value (16) */ ++#define PORT_P1_IN_P16 (0x1 << 16) ++#define PORT_P1_IN_P16_GET(val) ((((val) & PORT_P1_IN_P16) >> 16) & 0x1) ++/* Port 1 Pin # Latched Input Value (15) */ ++#define PORT_P1_IN_P15 (0x1 << 15) ++#define PORT_P1_IN_P15_GET(val) ((((val) & PORT_P1_IN_P15) >> 15) & 0x1) ++/* Port 1 Pin # Latched Input Value (14) */ ++#define PORT_P1_IN_P14 (0x1 << 14) ++#define PORT_P1_IN_P14_GET(val) ((((val) & PORT_P1_IN_P14) >> 14) & 0x1) ++/* Port 1 Pin # Latched Input Value (13) */ ++#define PORT_P1_IN_P13 (0x1 << 13) ++#define PORT_P1_IN_P13_GET(val) ((((val) & PORT_P1_IN_P13) >> 13) & 0x1) ++/* Port 1 Pin # Latched Input Value (12) */ ++#define PORT_P1_IN_P12 (0x1 << 12) ++#define PORT_P1_IN_P12_GET(val) ((((val) & PORT_P1_IN_P12) >> 12) & 0x1) ++/* Port 1 Pin # Latched Input Value (11) */ ++#define PORT_P1_IN_P11 (0x1 << 11) ++#define PORT_P1_IN_P11_GET(val) ((((val) & PORT_P1_IN_P11) >> 11) & 0x1) ++/* Port 1 Pin # Latched Input Value (10) */ ++#define PORT_P1_IN_P10 (0x1 << 10) ++#define PORT_P1_IN_P10_GET(val) ((((val) & PORT_P1_IN_P10) >> 10) & 0x1) ++/* Port 1 Pin # Latched Input Value (9) */ ++#define PORT_P1_IN_P9 (0x1 << 9) ++#define PORT_P1_IN_P9_GET(val) ((((val) & PORT_P1_IN_P9) >> 9) & 0x1) ++/* Port 1 Pin # Latched Input Value (8) */ ++#define PORT_P1_IN_P8 (0x1 << 8) ++#define PORT_P1_IN_P8_GET(val) ((((val) & PORT_P1_IN_P8) >> 8) & 0x1) ++/* Port 1 Pin # Latched Input Value (7) */ ++#define PORT_P1_IN_P7 (0x1 << 7) ++#define PORT_P1_IN_P7_GET(val) ((((val) & PORT_P1_IN_P7) >> 7) & 0x1) ++/* Port 1 Pin # Latched Input Value (6) */ ++#define PORT_P1_IN_P6 (0x1 << 6) ++#define PORT_P1_IN_P6_GET(val) ((((val) & PORT_P1_IN_P6) >> 6) & 0x1) ++/* Port 1 Pin # Latched Input Value (5) */ ++#define PORT_P1_IN_P5 (0x1 << 5) ++#define PORT_P1_IN_P5_GET(val) ((((val) & PORT_P1_IN_P5) >> 5) & 0x1) ++/* Port 1 Pin # Latched Input Value (4) */ ++#define PORT_P1_IN_P4 (0x1 << 4) ++#define PORT_P1_IN_P4_GET(val) ((((val) & PORT_P1_IN_P4) >> 4) & 0x1) ++/* Port 1 Pin # Latched Input Value (3) */ ++#define PORT_P1_IN_P3 (0x1 << 3) ++#define PORT_P1_IN_P3_GET(val) ((((val) & PORT_P1_IN_P3) >> 3) & 0x1) ++/* Port 1 Pin # Latched Input Value (2) */ ++#define PORT_P1_IN_P2 (0x1 << 2) ++#define PORT_P1_IN_P2_GET(val) ((((val) & PORT_P1_IN_P2) >> 2) & 0x1) ++/* Port 1 Pin # Latched Input Value (1) */ ++#define PORT_P1_IN_P1 (0x1 << 1) ++#define PORT_P1_IN_P1_GET(val) ((((val) & PORT_P1_IN_P1) >> 1) & 0x1) ++/* Port 1 Pin # Latched Input Value (0) */ ++#define PORT_P1_IN_P0 (0x1) ++#define PORT_P1_IN_P0_GET(val) ((((val) & PORT_P1_IN_P0) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Port 1 Direction Register ++ ******************************************************************************/ ++ ++/* Port 1 Pin #Direction Control (19) */ ++#define PORT_P1_DIR_P19 (0x1 << 19) ++#define PORT_P1_DIR_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_DIR_P19_GET(val) ((((val) & PORT_P1_DIR_P19) >> 19) & 0x1) ++#define PORT_P1_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P19) | (((val) & 0x1) << 19)) ++/* Port 1 Pin #Direction Control (18) */ ++#define PORT_P1_DIR_P18 (0x1 << 18) ++#define PORT_P1_DIR_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_DIR_P18_GET(val) ((((val) & PORT_P1_DIR_P18) >> 18) & 0x1) ++#define PORT_P1_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P18) | (((val) & 0x1) << 18)) ++/* Port 1 Pin #Direction Control (17) */ ++#define PORT_P1_DIR_P17 (0x1 << 17) ++#define PORT_P1_DIR_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_DIR_P17_GET(val) ((((val) & PORT_P1_DIR_P17) >> 17) & 0x1) ++#define PORT_P1_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P17) | (((val) & 0x1) << 17)) ++/* Port 1 Pin #Direction Control (16) */ ++#define PORT_P1_DIR_P16 (0x1 << 16) ++#define PORT_P1_DIR_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_DIR_P16_GET(val) ((((val) & PORT_P1_DIR_P16) >> 16) & 0x1) ++#define PORT_P1_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P16) | (((val) & 0x1) << 16)) ++/* Port 1 Pin #Direction Control (15) */ ++#define PORT_P1_DIR_P15 (0x1 << 15) ++#define PORT_P1_DIR_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_DIR_P15_GET(val) ((((val) & PORT_P1_DIR_P15) >> 15) & 0x1) ++#define PORT_P1_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P15) | (((val) & 0x1) << 15)) ++/* Port 1 Pin #Direction Control (14) */ ++#define PORT_P1_DIR_P14 (0x1 << 14) ++#define PORT_P1_DIR_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P1_DIR_P14_GET(val) ((((val) & PORT_P1_DIR_P14) >> 14) & 0x1) ++#define PORT_P1_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P14) | (((val) & 0x1) << 14)) ++/* Port 1 Pin #Direction Control (13) */ ++#define PORT_P1_DIR_P13 (0x1 << 13) ++#define PORT_P1_DIR_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P1_DIR_P13_GET(val) ((((val) & PORT_P1_DIR_P13) >> 13) & 0x1) ++#define PORT_P1_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P13) | (((val) & 0x1) << 13)) ++/* Port 1 Pin #Direction Control (12) */ ++#define PORT_P1_DIR_P12 (0x1 << 12) ++#define PORT_P1_DIR_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P1_DIR_P12_GET(val) ((((val) & PORT_P1_DIR_P12) >> 12) & 0x1) ++#define PORT_P1_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P12) | (((val) & 0x1) << 12)) ++/* Port 1 Pin #Direction Control (11) */ ++#define PORT_P1_DIR_P11 (0x1 << 11) ++#define PORT_P1_DIR_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P1_DIR_P11_GET(val) ((((val) & PORT_P1_DIR_P11) >> 11) & 0x1) ++#define PORT_P1_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P11) | (((val) & 0x1) << 11)) ++/* Port 1 Pin #Direction Control (10) */ ++#define PORT_P1_DIR_P10 (0x1 << 10) ++#define PORT_P1_DIR_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P1_DIR_P10_GET(val) ((((val) & PORT_P1_DIR_P10) >> 10) & 0x1) ++#define PORT_P1_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P10) | (((val) & 0x1) << 10)) ++/* Port 1 Pin #Direction Control (9) */ ++#define PORT_P1_DIR_P9 (0x1 << 9) ++#define PORT_P1_DIR_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P1_DIR_P9_GET(val) ((((val) & PORT_P1_DIR_P9) >> 9) & 0x1) ++#define PORT_P1_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P9) | (((val) & 0x1) << 9)) ++/* Port 1 Pin #Direction Control (8) */ ++#define PORT_P1_DIR_P8 (0x1 << 8) ++#define PORT_P1_DIR_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P1_DIR_P8_GET(val) ((((val) & PORT_P1_DIR_P8) >> 8) & 0x1) ++#define PORT_P1_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P8) | (((val) & 0x1) << 8)) ++/* Port 1 Pin #Direction Control (7) */ ++#define PORT_P1_DIR_P7 (0x1 << 7) ++#define PORT_P1_DIR_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P1_DIR_P7_GET(val) ((((val) & PORT_P1_DIR_P7) >> 7) & 0x1) ++#define PORT_P1_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P7) | (((val) & 0x1) << 7)) ++/* Port 1 Pin #Direction Control (6) */ ++#define PORT_P1_DIR_P6 (0x1 << 6) ++#define PORT_P1_DIR_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P1_DIR_P6_GET(val) ((((val) & PORT_P1_DIR_P6) >> 6) & 0x1) ++#define PORT_P1_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P6) | (((val) & 0x1) << 6)) ++/* Port 1 Pin #Direction Control (5) */ ++#define PORT_P1_DIR_P5 (0x1 << 5) ++#define PORT_P1_DIR_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P1_DIR_P5_GET(val) ((((val) & PORT_P1_DIR_P5) >> 5) & 0x1) ++#define PORT_P1_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P5) | (((val) & 0x1) << 5)) ++/* Port 1 Pin #Direction Control (4) */ ++#define PORT_P1_DIR_P4 (0x1 << 4) ++#define PORT_P1_DIR_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P1_DIR_P4_GET(val) ((((val) & PORT_P1_DIR_P4) >> 4) & 0x1) ++#define PORT_P1_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P4) | (((val) & 0x1) << 4)) ++/* Port 1 Pin #Direction Control (3) */ ++#define PORT_P1_DIR_P3 (0x1 << 3) ++#define PORT_P1_DIR_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P1_DIR_P3_GET(val) ((((val) & PORT_P1_DIR_P3) >> 3) & 0x1) ++#define PORT_P1_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P3) | (((val) & 0x1) << 3)) ++/* Port 1 Pin #Direction Control (2) */ ++#define PORT_P1_DIR_P2 (0x1 << 2) ++#define PORT_P1_DIR_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P1_DIR_P2_GET(val) ((((val) & PORT_P1_DIR_P2) >> 2) & 0x1) ++#define PORT_P1_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P2) | (((val) & 0x1) << 2)) ++/* Port 1 Pin #Direction Control (1) */ ++#define PORT_P1_DIR_P1 (0x1 << 1) ++#define PORT_P1_DIR_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P1_DIR_P1_GET(val) ((((val) & PORT_P1_DIR_P1) >> 1) & 0x1) ++#define PORT_P1_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P1) | (((val) & 0x1) << 1)) ++/* Port 1 Pin #Direction Control (0) */ ++#define PORT_P1_DIR_P0 (0x1) ++#define PORT_P1_DIR_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P1_DIR_P0_GET(val) ((((val) & PORT_P1_DIR_P0) >> 0) & 0x1) ++#define PORT_P1_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_DIR_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 1 Alternate Function Select Register 0 ++ ******************************************************************************/ ++ ++/* Alternate Function at Port 1 Bit # (19) */ ++#define PORT_P1_ALTSEL0_P19 (0x1 << 19) ++#define PORT_P1_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_ALTSEL0_P19_GET(val) ((((val) & PORT_P1_ALTSEL0_P19) >> 19) & 0x1) ++#define PORT_P1_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P19) | (((val) & 0x1) << 19)) ++/* Alternate Function at Port 1 Bit # (18) */ ++#define PORT_P1_ALTSEL0_P18 (0x1 << 18) ++#define PORT_P1_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_ALTSEL0_P18_GET(val) ((((val) & PORT_P1_ALTSEL0_P18) >> 18) & 0x1) ++#define PORT_P1_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P18) | (((val) & 0x1) << 18)) ++/* Alternate Function at Port 1 Bit # (17) */ ++#define PORT_P1_ALTSEL0_P17 (0x1 << 17) ++#define PORT_P1_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_ALTSEL0_P17_GET(val) ((((val) & PORT_P1_ALTSEL0_P17) >> 17) & 0x1) ++#define PORT_P1_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P17) | (((val) & 0x1) << 17)) ++/* Alternate Function at Port 1 Bit # (16) */ ++#define PORT_P1_ALTSEL0_P16 (0x1 << 16) ++#define PORT_P1_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_ALTSEL0_P16_GET(val) ((((val) & PORT_P1_ALTSEL0_P16) >> 16) & 0x1) ++#define PORT_P1_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P16) | (((val) & 0x1) << 16)) ++/* Alternate Function at Port 1 Bit # (15) */ ++#define PORT_P1_ALTSEL0_P15 (0x1 << 15) ++#define PORT_P1_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_ALTSEL0_P15_GET(val) ((((val) & PORT_P1_ALTSEL0_P15) >> 15) & 0x1) ++#define PORT_P1_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P15) | (((val) & 0x1) << 15)) ++/* Alternate Function at Port 1 Bit # (14) */ ++#define PORT_P1_ALTSEL0_P14 (0x1 << 14) ++#define PORT_P1_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P1_ALTSEL0_P14_GET(val) ((((val) & PORT_P1_ALTSEL0_P14) >> 14) & 0x1) ++#define PORT_P1_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P14) | (((val) & 0x1) << 14)) ++/* Alternate Function at Port 1 Bit # (13) */ ++#define PORT_P1_ALTSEL0_P13 (0x1 << 13) ++#define PORT_P1_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P1_ALTSEL0_P13_GET(val) ((((val) & PORT_P1_ALTSEL0_P13) >> 13) & 0x1) ++#define PORT_P1_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P13) | (((val) & 0x1) << 13)) ++/* Alternate Function at Port 1 Bit # (12) */ ++#define PORT_P1_ALTSEL0_P12 (0x1 << 12) ++#define PORT_P1_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P1_ALTSEL0_P12_GET(val) ((((val) & PORT_P1_ALTSEL0_P12) >> 12) & 0x1) ++#define PORT_P1_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P12) | (((val) & 0x1) << 12)) ++/* Alternate Function at Port 1 Bit # (11) */ ++#define PORT_P1_ALTSEL0_P11 (0x1 << 11) ++#define PORT_P1_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P1_ALTSEL0_P11_GET(val) ((((val) & PORT_P1_ALTSEL0_P11) >> 11) & 0x1) ++#define PORT_P1_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P11) | (((val) & 0x1) << 11)) ++/* Alternate Function at Port 1 Bit # (10) */ ++#define PORT_P1_ALTSEL0_P10 (0x1 << 10) ++#define PORT_P1_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P1_ALTSEL0_P10_GET(val) ((((val) & PORT_P1_ALTSEL0_P10) >> 10) & 0x1) ++#define PORT_P1_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P10) | (((val) & 0x1) << 10)) ++/* Alternate Function at Port 1 Bit # (9) */ ++#define PORT_P1_ALTSEL0_P9 (0x1 << 9) ++#define PORT_P1_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P1_ALTSEL0_P9_GET(val) ((((val) & PORT_P1_ALTSEL0_P9) >> 9) & 0x1) ++#define PORT_P1_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P9) | (((val) & 0x1) << 9)) ++/* Alternate Function at Port 1 Bit # (8) */ ++#define PORT_P1_ALTSEL0_P8 (0x1 << 8) ++#define PORT_P1_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P1_ALTSEL0_P8_GET(val) ((((val) & PORT_P1_ALTSEL0_P8) >> 8) & 0x1) ++#define PORT_P1_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P8) | (((val) & 0x1) << 8)) ++/* Alternate Function at Port 1 Bit # (7) */ ++#define PORT_P1_ALTSEL0_P7 (0x1 << 7) ++#define PORT_P1_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P1_ALTSEL0_P7_GET(val) ((((val) & PORT_P1_ALTSEL0_P7) >> 7) & 0x1) ++#define PORT_P1_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P7) | (((val) & 0x1) << 7)) ++/* Alternate Function at Port 1 Bit # (6) */ ++#define PORT_P1_ALTSEL0_P6 (0x1 << 6) ++#define PORT_P1_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P1_ALTSEL0_P6_GET(val) ((((val) & PORT_P1_ALTSEL0_P6) >> 6) & 0x1) ++#define PORT_P1_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P6) | (((val) & 0x1) << 6)) ++/* Alternate Function at Port 1 Bit # (5) */ ++#define PORT_P1_ALTSEL0_P5 (0x1 << 5) ++#define PORT_P1_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P1_ALTSEL0_P5_GET(val) ((((val) & PORT_P1_ALTSEL0_P5) >> 5) & 0x1) ++#define PORT_P1_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P5) | (((val) & 0x1) << 5)) ++/* Alternate Function at Port 1 Bit # (4) */ ++#define PORT_P1_ALTSEL0_P4 (0x1 << 4) ++#define PORT_P1_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P1_ALTSEL0_P4_GET(val) ((((val) & PORT_P1_ALTSEL0_P4) >> 4) & 0x1) ++#define PORT_P1_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P4) | (((val) & 0x1) << 4)) ++/* Alternate Function at Port 1 Bit # (3) */ ++#define PORT_P1_ALTSEL0_P3 (0x1 << 3) ++#define PORT_P1_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P1_ALTSEL0_P3_GET(val) ((((val) & PORT_P1_ALTSEL0_P3) >> 3) & 0x1) ++#define PORT_P1_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P3) | (((val) & 0x1) << 3)) ++/* Alternate Function at Port 1 Bit # (2) */ ++#define PORT_P1_ALTSEL0_P2 (0x1 << 2) ++#define PORT_P1_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P1_ALTSEL0_P2_GET(val) ((((val) & PORT_P1_ALTSEL0_P2) >> 2) & 0x1) ++#define PORT_P1_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P2) | (((val) & 0x1) << 2)) ++/* Alternate Function at Port 1 Bit # (1) */ ++#define PORT_P1_ALTSEL0_P1 (0x1 << 1) ++#define PORT_P1_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P1_ALTSEL0_P1_GET(val) ((((val) & PORT_P1_ALTSEL0_P1) >> 1) & 0x1) ++#define PORT_P1_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P1) | (((val) & 0x1) << 1)) ++/* Alternate Function at Port 1 Bit # (0) */ ++#define PORT_P1_ALTSEL0_P0 (0x1) ++#define PORT_P1_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P1_ALTSEL0_P0_GET(val) ((((val) & PORT_P1_ALTSEL0_P0) >> 0) & 0x1) ++#define PORT_P1_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_ALTSEL0_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 1 Pull Up Device Enable Register ++ ******************************************************************************/ ++ ++/* Pull Up Device Enable at Port 1 Bit # (19) */ ++#define PORT_P1_PUEN_P19 (0x1 << 19) ++#define PORT_P1_PUEN_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_PUEN_P19_GET(val) ((((val) & PORT_P1_PUEN_P19) >> 19) & 0x1) ++#define PORT_P1_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P19) | (((val) & 0x1) << 19)) ++/* Pull Up Device Enable at Port 1 Bit # (18) */ ++#define PORT_P1_PUEN_P18 (0x1 << 18) ++#define PORT_P1_PUEN_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_PUEN_P18_GET(val) ((((val) & PORT_P1_PUEN_P18) >> 18) & 0x1) ++#define PORT_P1_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P18) | (((val) & 0x1) << 18)) ++/* Pull Up Device Enable at Port 1 Bit # (17) */ ++#define PORT_P1_PUEN_P17 (0x1 << 17) ++#define PORT_P1_PUEN_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_PUEN_P17_GET(val) ((((val) & PORT_P1_PUEN_P17) >> 17) & 0x1) ++#define PORT_P1_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P17) | (((val) & 0x1) << 17)) ++/* Pull Up Device Enable at Port 1 Bit # (16) */ ++#define PORT_P1_PUEN_P16 (0x1 << 16) ++#define PORT_P1_PUEN_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_PUEN_P16_GET(val) ((((val) & PORT_P1_PUEN_P16) >> 16) & 0x1) ++#define PORT_P1_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P16) | (((val) & 0x1) << 16)) ++/* Pull Up Device Enable at Port 1 Bit # (15) */ ++#define PORT_P1_PUEN_P15 (0x1 << 15) ++#define PORT_P1_PUEN_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_PUEN_P15_GET(val) ((((val) & PORT_P1_PUEN_P15) >> 15) & 0x1) ++#define PORT_P1_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P15) | (((val) & 0x1) << 15)) ++/* Pull Up Device Enable at Port 1 Bit # (14) */ ++#define PORT_P1_PUEN_P14 (0x1 << 14) ++#define PORT_P1_PUEN_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P1_PUEN_P14_GET(val) ((((val) & PORT_P1_PUEN_P14) >> 14) & 0x1) ++#define PORT_P1_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P14) | (((val) & 0x1) << 14)) ++/* Pull Up Device Enable at Port 1 Bit # (13) */ ++#define PORT_P1_PUEN_P13 (0x1 << 13) ++#define PORT_P1_PUEN_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P1_PUEN_P13_GET(val) ((((val) & PORT_P1_PUEN_P13) >> 13) & 0x1) ++#define PORT_P1_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P13) | (((val) & 0x1) << 13)) ++/* Pull Up Device Enable at Port 1 Bit # (12) */ ++#define PORT_P1_PUEN_P12 (0x1 << 12) ++#define PORT_P1_PUEN_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P1_PUEN_P12_GET(val) ((((val) & PORT_P1_PUEN_P12) >> 12) & 0x1) ++#define PORT_P1_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P12) | (((val) & 0x1) << 12)) ++/* Pull Up Device Enable at Port 1 Bit # (11) */ ++#define PORT_P1_PUEN_P11 (0x1 << 11) ++#define PORT_P1_PUEN_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P1_PUEN_P11_GET(val) ((((val) & PORT_P1_PUEN_P11) >> 11) & 0x1) ++#define PORT_P1_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P11) | (((val) & 0x1) << 11)) ++/* Pull Up Device Enable at Port 1 Bit # (10) */ ++#define PORT_P1_PUEN_P10 (0x1 << 10) ++#define PORT_P1_PUEN_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P1_PUEN_P10_GET(val) ((((val) & PORT_P1_PUEN_P10) >> 10) & 0x1) ++#define PORT_P1_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P10) | (((val) & 0x1) << 10)) ++/* Pull Up Device Enable at Port 1 Bit # (9) */ ++#define PORT_P1_PUEN_P9 (0x1 << 9) ++#define PORT_P1_PUEN_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P1_PUEN_P9_GET(val) ((((val) & PORT_P1_PUEN_P9) >> 9) & 0x1) ++#define PORT_P1_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P9) | (((val) & 0x1) << 9)) ++/* Pull Up Device Enable at Port 1 Bit # (8) */ ++#define PORT_P1_PUEN_P8 (0x1 << 8) ++#define PORT_P1_PUEN_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P1_PUEN_P8_GET(val) ((((val) & PORT_P1_PUEN_P8) >> 8) & 0x1) ++#define PORT_P1_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P8) | (((val) & 0x1) << 8)) ++/* Pull Up Device Enable at Port 1 Bit # (7) */ ++#define PORT_P1_PUEN_P7 (0x1 << 7) ++#define PORT_P1_PUEN_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P1_PUEN_P7_GET(val) ((((val) & PORT_P1_PUEN_P7) >> 7) & 0x1) ++#define PORT_P1_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P7) | (((val) & 0x1) << 7)) ++/* Pull Up Device Enable at Port 1 Bit # (6) */ ++#define PORT_P1_PUEN_P6 (0x1 << 6) ++#define PORT_P1_PUEN_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P1_PUEN_P6_GET(val) ((((val) & PORT_P1_PUEN_P6) >> 6) & 0x1) ++#define PORT_P1_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P6) | (((val) & 0x1) << 6)) ++/* Pull Up Device Enable at Port 1 Bit # (5) */ ++#define PORT_P1_PUEN_P5 (0x1 << 5) ++#define PORT_P1_PUEN_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P1_PUEN_P5_GET(val) ((((val) & PORT_P1_PUEN_P5) >> 5) & 0x1) ++#define PORT_P1_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P5) | (((val) & 0x1) << 5)) ++/* Pull Up Device Enable at Port 1 Bit # (4) */ ++#define PORT_P1_PUEN_P4 (0x1 << 4) ++#define PORT_P1_PUEN_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P1_PUEN_P4_GET(val) ((((val) & PORT_P1_PUEN_P4) >> 4) & 0x1) ++#define PORT_P1_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P4) | (((val) & 0x1) << 4)) ++/* Pull Up Device Enable at Port 1 Bit # (3) */ ++#define PORT_P1_PUEN_P3 (0x1 << 3) ++#define PORT_P1_PUEN_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P1_PUEN_P3_GET(val) ((((val) & PORT_P1_PUEN_P3) >> 3) & 0x1) ++#define PORT_P1_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P3) | (((val) & 0x1) << 3)) ++/* Pull Up Device Enable at Port 1 Bit # (2) */ ++#define PORT_P1_PUEN_P2 (0x1 << 2) ++#define PORT_P1_PUEN_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P1_PUEN_P2_GET(val) ((((val) & PORT_P1_PUEN_P2) >> 2) & 0x1) ++#define PORT_P1_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P2) | (((val) & 0x1) << 2)) ++/* Pull Up Device Enable at Port 1 Bit # (1) */ ++#define PORT_P1_PUEN_P1 (0x1 << 1) ++#define PORT_P1_PUEN_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P1_PUEN_P1_GET(val) ((((val) & PORT_P1_PUEN_P1) >> 1) & 0x1) ++#define PORT_P1_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P1) | (((val) & 0x1) << 1)) ++/* Pull Up Device Enable at Port 1 Bit # (0) */ ++#define PORT_P1_PUEN_P0 (0x1) ++#define PORT_P1_PUEN_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P1_PUEN_P0_GET(val) ((((val) & PORT_P1_PUEN_P0) >> 0) & 0x1) ++#define PORT_P1_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P1_PUEN_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * External Interrupt Control Register 0 ++ ******************************************************************************/ ++ ++/* Type of Level or Edge Detection of EXINT15 (19) */ ++#define PORT_P1_EXINTCR0_EXINT15 (0x1 << 19) ++#define PORT_P1_EXINTCR0_EXINT15_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_EXINTCR0_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT15) >> 19) & 0x1) ++#define PORT_P1_EXINTCR0_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT15) | (((val) & 0x1) << 19)) ++/* Type of Level or Edge Detection of EXINT11 (18) */ ++#define PORT_P1_EXINTCR0_EXINT11 (0x1 << 18) ++#define PORT_P1_EXINTCR0_EXINT11_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_EXINTCR0_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT11) >> 18) & 0x1) ++#define PORT_P1_EXINTCR0_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT11) | (((val) & 0x1) << 18)) ++/* Type of Level or Edge Detection of EXINT12 (17) */ ++#define PORT_P1_EXINTCR0_EXINT12 (0x1 << 17) ++#define PORT_P1_EXINTCR0_EXINT12_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_EXINTCR0_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT12) >> 17) & 0x1) ++#define PORT_P1_EXINTCR0_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT12) | (((val) & 0x1) << 17)) ++/* Type of Level or Edge Detection of EXINT13 (16) */ ++#define PORT_P1_EXINTCR0_EXINT13 (0x1 << 16) ++#define PORT_P1_EXINTCR0_EXINT13_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_EXINTCR0_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT13) >> 16) & 0x1) ++#define PORT_P1_EXINTCR0_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT13) | (((val) & 0x1) << 16)) ++/* Type of Level or Edge Detection of EXINT14 (15) */ ++#define PORT_P1_EXINTCR0_EXINT14 (0x1 << 15) ++#define PORT_P1_EXINTCR0_EXINT14_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_EXINTCR0_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR0_EXINT14) >> 15) & 0x1) ++#define PORT_P1_EXINTCR0_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR0_EXINT14) | (((val) & 0x1) << 15)) ++ ++/******************************************************************************* ++ * External Interrupt Control Register 1 ++ ******************************************************************************/ ++ ++/* Type of Level or Edge Detection of EXINT15 (19) */ ++#define PORT_P1_EXINTCR1_EXINT15 (0x1 << 19) ++#define PORT_P1_EXINTCR1_EXINT15_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_EXINTCR1_EXINT15_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT15) >> 19) & 0x1) ++#define PORT_P1_EXINTCR1_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT15) | (((val) & 0x1) << 19)) ++/* Type of Level or Edge Detection of EXINT11 (18) */ ++#define PORT_P1_EXINTCR1_EXINT11 (0x1 << 18) ++#define PORT_P1_EXINTCR1_EXINT11_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_EXINTCR1_EXINT11_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT11) >> 18) & 0x1) ++#define PORT_P1_EXINTCR1_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT11) | (((val) & 0x1) << 18)) ++/* Type of Level or Edge Detection of EXINT12 (17) */ ++#define PORT_P1_EXINTCR1_EXINT12 (0x1 << 17) ++#define PORT_P1_EXINTCR1_EXINT12_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_EXINTCR1_EXINT12_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT12) >> 17) & 0x1) ++#define PORT_P1_EXINTCR1_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT12) | (((val) & 0x1) << 17)) ++/* Type of Level or Edge Detection of EXINT13 (16) */ ++#define PORT_P1_EXINTCR1_EXINT13 (0x1 << 16) ++#define PORT_P1_EXINTCR1_EXINT13_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_EXINTCR1_EXINT13_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT13) >> 16) & 0x1) ++#define PORT_P1_EXINTCR1_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT13) | (((val) & 0x1) << 16)) ++/* Type of Level or Edge Detection of EXINT14 (15) */ ++#define PORT_P1_EXINTCR1_EXINT14 (0x1 << 15) ++#define PORT_P1_EXINTCR1_EXINT14_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_EXINTCR1_EXINT14_GET(val) ((((val) & PORT_P1_EXINTCR1_EXINT14) >> 15) & 0x1) ++#define PORT_P1_EXINTCR1_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_EXINTCR1_EXINT14) | (((val) & 0x1) << 15)) ++ ++/******************************************************************************* ++ * P1_IRNEN Register ++ ******************************************************************************/ ++ ++/* EXINT15 Interrupt Request Enable (19) */ ++#define PORT_P1_IRNEN_EXINT15 (0x1 << 19) ++#define PORT_P1_IRNEN_EXINT15_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_IRNEN_EXINT15_GET(val) ((((val) & PORT_P1_IRNEN_EXINT15) >> 19) & 0x1) ++#define PORT_P1_IRNEN_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT15) | (((val) & 0x1) << 19)) ++/* EXINT11 Interrupt Request Enable (18) */ ++#define PORT_P1_IRNEN_EXINT11 (0x1 << 18) ++#define PORT_P1_IRNEN_EXINT11_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_IRNEN_EXINT11_GET(val) ((((val) & PORT_P1_IRNEN_EXINT11) >> 18) & 0x1) ++#define PORT_P1_IRNEN_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT11) | (((val) & 0x1) << 18)) ++/* EXINT12 Interrupt Request Enable (17) */ ++#define PORT_P1_IRNEN_EXINT12 (0x1 << 17) ++#define PORT_P1_IRNEN_EXINT12_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_IRNEN_EXINT12_GET(val) ((((val) & PORT_P1_IRNEN_EXINT12) >> 17) & 0x1) ++#define PORT_P1_IRNEN_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT12) | (((val) & 0x1) << 17)) ++/* EXINT13 Interrupt Request Enable (16) */ ++#define PORT_P1_IRNEN_EXINT13 (0x1 << 16) ++#define PORT_P1_IRNEN_EXINT13_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_IRNEN_EXINT13_GET(val) ((((val) & PORT_P1_IRNEN_EXINT13) >> 16) & 0x1) ++#define PORT_P1_IRNEN_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT13) | (((val) & 0x1) << 16)) ++/* EXINT14 Interrupt Request Enable (15) */ ++#define PORT_P1_IRNEN_EXINT14 (0x1 << 15) ++#define PORT_P1_IRNEN_EXINT14_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_IRNEN_EXINT14_GET(val) ((((val) & PORT_P1_IRNEN_EXINT14) >> 15) & 0x1) ++#define PORT_P1_IRNEN_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNEN_EXINT14) | (((val) & 0x1) << 15)) ++ ++/******************************************************************************* ++ * P1_IRNICR Register ++ ******************************************************************************/ ++ ++/* EXINT15 Interrupt Request (19) */ ++#define PORT_P1_IRNICR_EXINT15 (0x1 << 19) ++#define PORT_P1_IRNICR_EXINT15_GET(val) ((((val) & PORT_P1_IRNICR_EXINT15) >> 19) & 0x1) ++/* EXINT11 Interrupt Request (18) */ ++#define PORT_P1_IRNICR_EXINT11 (0x1 << 18) ++#define PORT_P1_IRNICR_EXINT11_GET(val) ((((val) & PORT_P1_IRNICR_EXINT11) >> 18) & 0x1) ++/* EXINT12 Interrupt Request (17) */ ++#define PORT_P1_IRNICR_EXINT12 (0x1 << 17) ++#define PORT_P1_IRNICR_EXINT12_GET(val) ((((val) & PORT_P1_IRNICR_EXINT12) >> 17) & 0x1) ++/* EXINT13 Interrupt Request (16) */ ++#define PORT_P1_IRNICR_EXINT13 (0x1 << 16) ++#define PORT_P1_IRNICR_EXINT13_GET(val) ((((val) & PORT_P1_IRNICR_EXINT13) >> 16) & 0x1) ++/* EXINT14 Interrupt Request (15) */ ++#define PORT_P1_IRNICR_EXINT14 (0x1 << 15) ++#define PORT_P1_IRNICR_EXINT14_GET(val) ((((val) & PORT_P1_IRNICR_EXINT14) >> 15) & 0x1) ++ ++/******************************************************************************* ++ * P1_IRNCR Register ++ ******************************************************************************/ ++ ++/* EXINT15 Interrupt Request (19) */ ++#define PORT_P1_IRNCR_EXINT15 (0x1 << 19) ++#define PORT_P1_IRNCR_EXINT15_GET(val) ((((val) & PORT_P1_IRNCR_EXINT15) >> 19) & 0x1) ++/* EXINT11 Interrupt Request (18) */ ++#define PORT_P1_IRNCR_EXINT11 (0x1 << 18) ++#define PORT_P1_IRNCR_EXINT11_GET(val) ((((val) & PORT_P1_IRNCR_EXINT11) >> 18) & 0x1) ++/* EXINT12 Interrupt Request (17) */ ++#define PORT_P1_IRNCR_EXINT12 (0x1 << 17) ++#define PORT_P1_IRNCR_EXINT12_GET(val) ((((val) & PORT_P1_IRNCR_EXINT12) >> 17) & 0x1) ++/* EXINT13 Interrupt Request (16) */ ++#define PORT_P1_IRNCR_EXINT13 (0x1 << 16) ++#define PORT_P1_IRNCR_EXINT13_GET(val) ((((val) & PORT_P1_IRNCR_EXINT13) >> 16) & 0x1) ++/* EXINT14 Interrupt Request (15) */ ++#define PORT_P1_IRNCR_EXINT14 (0x1 << 15) ++#define PORT_P1_IRNCR_EXINT14_GET(val) ((((val) & PORT_P1_IRNCR_EXINT14) >> 15) & 0x1) ++ ++/******************************************************************************* ++ * P1 External Event Detection Configuration Register ++ ******************************************************************************/ ++ ++/* EXINT15 configured for Edge or Level Detection (19) */ ++#define PORT_P1_IRNCFG_EXINT15 (0x1 << 19) ++#define PORT_P1_IRNCFG_EXINT15_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_IRNCFG_EXINT15_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT15) >> 19) & 0x1) ++#define PORT_P1_IRNCFG_EXINT15_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT15) | (((val) & 0x1) << 19)) ++/* EXINT11 configured for Edge or Level Detection (18) */ ++#define PORT_P1_IRNCFG_EXINT11 (0x1 << 18) ++#define PORT_P1_IRNCFG_EXINT11_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_IRNCFG_EXINT11_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT11) >> 18) & 0x1) ++#define PORT_P1_IRNCFG_EXINT11_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT11) | (((val) & 0x1) << 18)) ++/* EXINT12 configured for Edge or Level Detection (17) */ ++#define PORT_P1_IRNCFG_EXINT12 (0x1 << 17) ++#define PORT_P1_IRNCFG_EXINT12_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_IRNCFG_EXINT12_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT12) >> 17) & 0x1) ++#define PORT_P1_IRNCFG_EXINT12_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT12) | (((val) & 0x1) << 17)) ++/* EXINT13 configured for Edge or Level Detection (16) */ ++#define PORT_P1_IRNCFG_EXINT13 (0x1 << 16) ++#define PORT_P1_IRNCFG_EXINT13_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_IRNCFG_EXINT13_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT13) >> 16) & 0x1) ++#define PORT_P1_IRNCFG_EXINT13_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT13) | (((val) & 0x1) << 16)) ++/* EXINT14 configured for Edge or Level Detection (15) */ ++#define PORT_P1_IRNCFG_EXINT14 (0x1 << 15) ++#define PORT_P1_IRNCFG_EXINT14_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_IRNCFG_EXINT14_GET(val) ((((val) & PORT_P1_IRNCFG_EXINT14) >> 15) & 0x1) ++#define PORT_P1_IRNCFG_EXINT14_SET(reg,val) (reg) = ((reg & ~PORT_P1_IRNCFG_EXINT14) | (((val) & 0x1) << 15)) ++ ++/******************************************************************************* ++ * P1_IRNENSET Register ++ ******************************************************************************/ ++ ++/* Set Interrupt Node Enable Flag EXINT15 (19) */ ++#define PORT_P1_IRNENSET_EXINT15 (0x1 << 19) ++#define PORT_P1_IRNENSET_EXINT15_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_IRNENSET_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT15) | (val) & 1) << 19) ++/* Set Interrupt Node Enable Flag EXINT11 (18) */ ++#define PORT_P1_IRNENSET_EXINT11 (0x1 << 18) ++#define PORT_P1_IRNENSET_EXINT11_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_IRNENSET_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT11) | (val) & 1) << 18) ++/* Set Interrupt Node Enable Flag EXINT12 (17) */ ++#define PORT_P1_IRNENSET_EXINT12 (0x1 << 17) ++#define PORT_P1_IRNENSET_EXINT12_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_IRNENSET_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT12) | (val) & 1) << 17) ++/* Set Interrupt Node Enable Flag EXINT13 (16) */ ++#define PORT_P1_IRNENSET_EXINT13 (0x1 << 16) ++#define PORT_P1_IRNENSET_EXINT13_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_IRNENSET_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT13) | (val) & 1) << 16) ++/* Set Interrupt Node Enable Flag EXINT14 (15) */ ++#define PORT_P1_IRNENSET_EXINT14 (0x1 << 15) ++#define PORT_P1_IRNENSET_EXINT14_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_IRNENSET_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENSET_EXINT14) | (val) & 1) << 15) ++ ++/******************************************************************************* ++ * P1_IRNENCLR Register ++ ******************************************************************************/ ++ ++/* Clear Interrupt Node Enable Flag EXINT15 (19) */ ++#define PORT_P1_IRNENCLR_EXINT15 (0x1 << 19) ++#define PORT_P1_IRNENCLR_EXINT15_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P1_IRNENCLR_EXINT15_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT15) | (val) & 1) << 19) ++/* Clear Interrupt Node Enable Flag EXINT11 (18) */ ++#define PORT_P1_IRNENCLR_EXINT11 (0x1 << 18) ++#define PORT_P1_IRNENCLR_EXINT11_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P1_IRNENCLR_EXINT11_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT11) | (val) & 1) << 18) ++/* Clear Interrupt Node Enable Flag EXINT12 (17) */ ++#define PORT_P1_IRNENCLR_EXINT12 (0x1 << 17) ++#define PORT_P1_IRNENCLR_EXINT12_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P1_IRNENCLR_EXINT12_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT12) | (val) & 1) << 17) ++/* Clear Interrupt Node Enable Flag EXINT13 (16) */ ++#define PORT_P1_IRNENCLR_EXINT13 (0x1 << 16) ++#define PORT_P1_IRNENCLR_EXINT13_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P1_IRNENCLR_EXINT13_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT13) | (val) & 1) << 16) ++/* Clear Interrupt Node Enable Flag EXINT14 (15) */ ++#define PORT_P1_IRNENCLR_EXINT14 (0x1 << 15) ++#define PORT_P1_IRNENCLR_EXINT14_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P1_IRNENCLR_EXINT14_SET(reg,val) (reg) = (((reg & ~PORT_P1_IRNENCLR_EXINT14) | (val) & 1) << 15) ++ ++/******************************************************************************* ++ * Port 2 Data Output Register ++ ******************************************************************************/ ++ ++/* Port 2 Pin # Output Value (19) */ ++#define PORT_P2_OUT_P19 (0x1 << 19) ++#define PORT_P2_OUT_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P2_OUT_P19_GET(val) ((((val) & PORT_P2_OUT_P19) >> 19) & 0x1) ++#define PORT_P2_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P19) | (((val) & 0x1) << 19)) ++/* Port 2 Pin # Output Value (18) */ ++#define PORT_P2_OUT_P18 (0x1 << 18) ++#define PORT_P2_OUT_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P2_OUT_P18_GET(val) ((((val) & PORT_P2_OUT_P18) >> 18) & 0x1) ++#define PORT_P2_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P18) | (((val) & 0x1) << 18)) ++/* Port 2 Pin # Output Value (17) */ ++#define PORT_P2_OUT_P17 (0x1 << 17) ++#define PORT_P2_OUT_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P2_OUT_P17_GET(val) ((((val) & PORT_P2_OUT_P17) >> 17) & 0x1) ++#define PORT_P2_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P17) | (((val) & 0x1) << 17)) ++/* Port 2 Pin # Output Value (16) */ ++#define PORT_P2_OUT_P16 (0x1 << 16) ++#define PORT_P2_OUT_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P2_OUT_P16_GET(val) ((((val) & PORT_P2_OUT_P16) >> 16) & 0x1) ++#define PORT_P2_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P16) | (((val) & 0x1) << 16)) ++/* Port 2 Pin # Output Value (15) */ ++#define PORT_P2_OUT_P15 (0x1 << 15) ++#define PORT_P2_OUT_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P2_OUT_P15_GET(val) ((((val) & PORT_P2_OUT_P15) >> 15) & 0x1) ++#define PORT_P2_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P15) | (((val) & 0x1) << 15)) ++/* Port 2 Pin # Output Value (14) */ ++#define PORT_P2_OUT_P14 (0x1 << 14) ++#define PORT_P2_OUT_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P2_OUT_P14_GET(val) ((((val) & PORT_P2_OUT_P14) >> 14) & 0x1) ++#define PORT_P2_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P14) | (((val) & 0x1) << 14)) ++/* Port 2 Pin # Output Value (13) */ ++#define PORT_P2_OUT_P13 (0x1 << 13) ++#define PORT_P2_OUT_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P2_OUT_P13_GET(val) ((((val) & PORT_P2_OUT_P13) >> 13) & 0x1) ++#define PORT_P2_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P13) | (((val) & 0x1) << 13)) ++/* Port 2 Pin # Output Value (12) */ ++#define PORT_P2_OUT_P12 (0x1 << 12) ++#define PORT_P2_OUT_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P2_OUT_P12_GET(val) ((((val) & PORT_P2_OUT_P12) >> 12) & 0x1) ++#define PORT_P2_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P12) | (((val) & 0x1) << 12)) ++/* Port 2 Pin # Output Value (11) */ ++#define PORT_P2_OUT_P11 (0x1 << 11) ++#define PORT_P2_OUT_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P2_OUT_P11_GET(val) ((((val) & PORT_P2_OUT_P11) >> 11) & 0x1) ++#define PORT_P2_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P11) | (((val) & 0x1) << 11)) ++/* Port 2 Pin # Output Value (10) */ ++#define PORT_P2_OUT_P10 (0x1 << 10) ++#define PORT_P2_OUT_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P2_OUT_P10_GET(val) ((((val) & PORT_P2_OUT_P10) >> 10) & 0x1) ++#define PORT_P2_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P10) | (((val) & 0x1) << 10)) ++/* Port 2 Pin # Output Value (9) */ ++#define PORT_P2_OUT_P9 (0x1 << 9) ++#define PORT_P2_OUT_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P2_OUT_P9_GET(val) ((((val) & PORT_P2_OUT_P9) >> 9) & 0x1) ++#define PORT_P2_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P9) | (((val) & 0x1) << 9)) ++/* Port 2 Pin # Output Value (8) */ ++#define PORT_P2_OUT_P8 (0x1 << 8) ++#define PORT_P2_OUT_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P2_OUT_P8_GET(val) ((((val) & PORT_P2_OUT_P8) >> 8) & 0x1) ++#define PORT_P2_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P8) | (((val) & 0x1) << 8)) ++/* Port 2 Pin # Output Value (7) */ ++#define PORT_P2_OUT_P7 (0x1 << 7) ++#define PORT_P2_OUT_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P2_OUT_P7_GET(val) ((((val) & PORT_P2_OUT_P7) >> 7) & 0x1) ++#define PORT_P2_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P7) | (((val) & 0x1) << 7)) ++/* Port 2 Pin # Output Value (6) */ ++#define PORT_P2_OUT_P6 (0x1 << 6) ++#define PORT_P2_OUT_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P2_OUT_P6_GET(val) ((((val) & PORT_P2_OUT_P6) >> 6) & 0x1) ++#define PORT_P2_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P6) | (((val) & 0x1) << 6)) ++/* Port 2 Pin # Output Value (5) */ ++#define PORT_P2_OUT_P5 (0x1 << 5) ++#define PORT_P2_OUT_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P2_OUT_P5_GET(val) ((((val) & PORT_P2_OUT_P5) >> 5) & 0x1) ++#define PORT_P2_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P5) | (((val) & 0x1) << 5)) ++/* Port 2 Pin # Output Value (4) */ ++#define PORT_P2_OUT_P4 (0x1 << 4) ++#define PORT_P2_OUT_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P2_OUT_P4_GET(val) ((((val) & PORT_P2_OUT_P4) >> 4) & 0x1) ++#define PORT_P2_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P4) | (((val) & 0x1) << 4)) ++/* Port 2 Pin # Output Value (3) */ ++#define PORT_P2_OUT_P3 (0x1 << 3) ++#define PORT_P2_OUT_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P2_OUT_P3_GET(val) ((((val) & PORT_P2_OUT_P3) >> 3) & 0x1) ++#define PORT_P2_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P3) | (((val) & 0x1) << 3)) ++/* Port 2 Pin # Output Value (2) */ ++#define PORT_P2_OUT_P2 (0x1 << 2) ++#define PORT_P2_OUT_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P2_OUT_P2_GET(val) ((((val) & PORT_P2_OUT_P2) >> 2) & 0x1) ++#define PORT_P2_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P2) | (((val) & 0x1) << 2)) ++/* Port 2 Pin # Output Value (1) */ ++#define PORT_P2_OUT_P1 (0x1 << 1) ++#define PORT_P2_OUT_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P2_OUT_P1_GET(val) ((((val) & PORT_P2_OUT_P1) >> 1) & 0x1) ++#define PORT_P2_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P1) | (((val) & 0x1) << 1)) ++/* Port 2 Pin # Output Value (0) */ ++#define PORT_P2_OUT_P0 (0x1) ++#define PORT_P2_OUT_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P2_OUT_P0_GET(val) ((((val) & PORT_P2_OUT_P0) >> 0) & 0x1) ++#define PORT_P2_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_OUT_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 2 Data Input Register ++ ******************************************************************************/ ++ ++/* Port 2 Pin # Latched Input Value (19) */ ++#define PORT_P2_IN_P19 (0x1 << 19) ++#define PORT_P2_IN_P19_GET(val) ((((val) & PORT_P2_IN_P19) >> 19) & 0x1) ++/* Port 2 Pin # Latched Input Value (18) */ ++#define PORT_P2_IN_P18 (0x1 << 18) ++#define PORT_P2_IN_P18_GET(val) ((((val) & PORT_P2_IN_P18) >> 18) & 0x1) ++/* Port 2 Pin # Latched Input Value (17) */ ++#define PORT_P2_IN_P17 (0x1 << 17) ++#define PORT_P2_IN_P17_GET(val) ((((val) & PORT_P2_IN_P17) >> 17) & 0x1) ++/* Port 2 Pin # Latched Input Value (16) */ ++#define PORT_P2_IN_P16 (0x1 << 16) ++#define PORT_P2_IN_P16_GET(val) ((((val) & PORT_P2_IN_P16) >> 16) & 0x1) ++/* Port 2 Pin # Latched Input Value (15) */ ++#define PORT_P2_IN_P15 (0x1 << 15) ++#define PORT_P2_IN_P15_GET(val) ((((val) & PORT_P2_IN_P15) >> 15) & 0x1) ++/* Port 2 Pin # Latched Input Value (14) */ ++#define PORT_P2_IN_P14 (0x1 << 14) ++#define PORT_P2_IN_P14_GET(val) ((((val) & PORT_P2_IN_P14) >> 14) & 0x1) ++/* Port 2 Pin # Latched Input Value (13) */ ++#define PORT_P2_IN_P13 (0x1 << 13) ++#define PORT_P2_IN_P13_GET(val) ((((val) & PORT_P2_IN_P13) >> 13) & 0x1) ++/* Port 2 Pin # Latched Input Value (12) */ ++#define PORT_P2_IN_P12 (0x1 << 12) ++#define PORT_P2_IN_P12_GET(val) ((((val) & PORT_P2_IN_P12) >> 12) & 0x1) ++/* Port 2 Pin # Latched Input Value (11) */ ++#define PORT_P2_IN_P11 (0x1 << 11) ++#define PORT_P2_IN_P11_GET(val) ((((val) & PORT_P2_IN_P11) >> 11) & 0x1) ++/* Port 2 Pin # Latched Input Value (10) */ ++#define PORT_P2_IN_P10 (0x1 << 10) ++#define PORT_P2_IN_P10_GET(val) ((((val) & PORT_P2_IN_P10) >> 10) & 0x1) ++/* Port 2 Pin # Latched Input Value (9) */ ++#define PORT_P2_IN_P9 (0x1 << 9) ++#define PORT_P2_IN_P9_GET(val) ((((val) & PORT_P2_IN_P9) >> 9) & 0x1) ++/* Port 2 Pin # Latched Input Value (8) */ ++#define PORT_P2_IN_P8 (0x1 << 8) ++#define PORT_P2_IN_P8_GET(val) ((((val) & PORT_P2_IN_P8) >> 8) & 0x1) ++/* Port 2 Pin # Latched Input Value (7) */ ++#define PORT_P2_IN_P7 (0x1 << 7) ++#define PORT_P2_IN_P7_GET(val) ((((val) & PORT_P2_IN_P7) >> 7) & 0x1) ++/* Port 2 Pin # Latched Input Value (6) */ ++#define PORT_P2_IN_P6 (0x1 << 6) ++#define PORT_P2_IN_P6_GET(val) ((((val) & PORT_P2_IN_P6) >> 6) & 0x1) ++/* Port 2 Pin # Latched Input Value (5) */ ++#define PORT_P2_IN_P5 (0x1 << 5) ++#define PORT_P2_IN_P5_GET(val) ((((val) & PORT_P2_IN_P5) >> 5) & 0x1) ++/* Port 2 Pin # Latched Input Value (4) */ ++#define PORT_P2_IN_P4 (0x1 << 4) ++#define PORT_P2_IN_P4_GET(val) ((((val) & PORT_P2_IN_P4) >> 4) & 0x1) ++/* Port 2 Pin # Latched Input Value (3) */ ++#define PORT_P2_IN_P3 (0x1 << 3) ++#define PORT_P2_IN_P3_GET(val) ((((val) & PORT_P2_IN_P3) >> 3) & 0x1) ++/* Port 2 Pin # Latched Input Value (2) */ ++#define PORT_P2_IN_P2 (0x1 << 2) ++#define PORT_P2_IN_P2_GET(val) ((((val) & PORT_P2_IN_P2) >> 2) & 0x1) ++/* Port 2 Pin # Latched Input Value (1) */ ++#define PORT_P2_IN_P1 (0x1 << 1) ++#define PORT_P2_IN_P1_GET(val) ((((val) & PORT_P2_IN_P1) >> 1) & 0x1) ++/* Port 2 Pin # Latched Input Value (0) */ ++#define PORT_P2_IN_P0 (0x1) ++#define PORT_P2_IN_P0_GET(val) ((((val) & PORT_P2_IN_P0) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Port 2 Direction Register ++ ******************************************************************************/ ++ ++/* Port 2 Pin #Direction Control (19) */ ++#define PORT_P2_DIR_P19 (0x1 << 19) ++#define PORT_P2_DIR_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P2_DIR_P19_GET(val) ((((val) & PORT_P2_DIR_P19) >> 19) & 0x1) ++#define PORT_P2_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P19) | (((val) & 0x1) << 19)) ++/* Port 2 Pin #Direction Control (18) */ ++#define PORT_P2_DIR_P18 (0x1 << 18) ++#define PORT_P2_DIR_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P2_DIR_P18_GET(val) ((((val) & PORT_P2_DIR_P18) >> 18) & 0x1) ++#define PORT_P2_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P18) | (((val) & 0x1) << 18)) ++/* Port 2 Pin #Direction Control (17) */ ++#define PORT_P2_DIR_P17 (0x1 << 17) ++#define PORT_P2_DIR_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P2_DIR_P17_GET(val) ((((val) & PORT_P2_DIR_P17) >> 17) & 0x1) ++#define PORT_P2_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P17) | (((val) & 0x1) << 17)) ++/* Port 2 Pin #Direction Control (16) */ ++#define PORT_P2_DIR_P16 (0x1 << 16) ++#define PORT_P2_DIR_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P2_DIR_P16_GET(val) ((((val) & PORT_P2_DIR_P16) >> 16) & 0x1) ++#define PORT_P2_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P16) | (((val) & 0x1) << 16)) ++/* Port 2 Pin #Direction Control (15) */ ++#define PORT_P2_DIR_P15 (0x1 << 15) ++#define PORT_P2_DIR_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P2_DIR_P15_GET(val) ((((val) & PORT_P2_DIR_P15) >> 15) & 0x1) ++#define PORT_P2_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P15) | (((val) & 0x1) << 15)) ++/* Port 2 Pin #Direction Control (14) */ ++#define PORT_P2_DIR_P14 (0x1 << 14) ++#define PORT_P2_DIR_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P2_DIR_P14_GET(val) ((((val) & PORT_P2_DIR_P14) >> 14) & 0x1) ++#define PORT_P2_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P14) | (((val) & 0x1) << 14)) ++/* Port 2 Pin #Direction Control (13) */ ++#define PORT_P2_DIR_P13 (0x1 << 13) ++#define PORT_P2_DIR_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P2_DIR_P13_GET(val) ((((val) & PORT_P2_DIR_P13) >> 13) & 0x1) ++#define PORT_P2_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P13) | (((val) & 0x1) << 13)) ++/* Port 2 Pin #Direction Control (12) */ ++#define PORT_P2_DIR_P12 (0x1 << 12) ++#define PORT_P2_DIR_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P2_DIR_P12_GET(val) ((((val) & PORT_P2_DIR_P12) >> 12) & 0x1) ++#define PORT_P2_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P12) | (((val) & 0x1) << 12)) ++/* Port 2 Pin #Direction Control (11) */ ++#define PORT_P2_DIR_P11 (0x1 << 11) ++#define PORT_P2_DIR_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P2_DIR_P11_GET(val) ((((val) & PORT_P2_DIR_P11) >> 11) & 0x1) ++#define PORT_P2_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P11) | (((val) & 0x1) << 11)) ++/* Port 2 Pin #Direction Control (10) */ ++#define PORT_P2_DIR_P10 (0x1 << 10) ++#define PORT_P2_DIR_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P2_DIR_P10_GET(val) ((((val) & PORT_P2_DIR_P10) >> 10) & 0x1) ++#define PORT_P2_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P10) | (((val) & 0x1) << 10)) ++/* Port 2 Pin #Direction Control (9) */ ++#define PORT_P2_DIR_P9 (0x1 << 9) ++#define PORT_P2_DIR_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P2_DIR_P9_GET(val) ((((val) & PORT_P2_DIR_P9) >> 9) & 0x1) ++#define PORT_P2_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P9) | (((val) & 0x1) << 9)) ++/* Port 2 Pin #Direction Control (8) */ ++#define PORT_P2_DIR_P8 (0x1 << 8) ++#define PORT_P2_DIR_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P2_DIR_P8_GET(val) ((((val) & PORT_P2_DIR_P8) >> 8) & 0x1) ++#define PORT_P2_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P8) | (((val) & 0x1) << 8)) ++/* Port 2 Pin #Direction Control (7) */ ++#define PORT_P2_DIR_P7 (0x1 << 7) ++#define PORT_P2_DIR_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P2_DIR_P7_GET(val) ((((val) & PORT_P2_DIR_P7) >> 7) & 0x1) ++#define PORT_P2_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P7) | (((val) & 0x1) << 7)) ++/* Port 2 Pin #Direction Control (6) */ ++#define PORT_P2_DIR_P6 (0x1 << 6) ++#define PORT_P2_DIR_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P2_DIR_P6_GET(val) ((((val) & PORT_P2_DIR_P6) >> 6) & 0x1) ++#define PORT_P2_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P6) | (((val) & 0x1) << 6)) ++/* Port 2 Pin #Direction Control (5) */ ++#define PORT_P2_DIR_P5 (0x1 << 5) ++#define PORT_P2_DIR_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P2_DIR_P5_GET(val) ((((val) & PORT_P2_DIR_P5) >> 5) & 0x1) ++#define PORT_P2_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P5) | (((val) & 0x1) << 5)) ++/* Port 2 Pin #Direction Control (4) */ ++#define PORT_P2_DIR_P4 (0x1 << 4) ++#define PORT_P2_DIR_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P2_DIR_P4_GET(val) ((((val) & PORT_P2_DIR_P4) >> 4) & 0x1) ++#define PORT_P2_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P4) | (((val) & 0x1) << 4)) ++/* Port 2 Pin #Direction Control (3) */ ++#define PORT_P2_DIR_P3 (0x1 << 3) ++#define PORT_P2_DIR_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P2_DIR_P3_GET(val) ((((val) & PORT_P2_DIR_P3) >> 3) & 0x1) ++#define PORT_P2_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P3) | (((val) & 0x1) << 3)) ++/* Port 2 Pin #Direction Control (2) */ ++#define PORT_P2_DIR_P2 (0x1 << 2) ++#define PORT_P2_DIR_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P2_DIR_P2_GET(val) ((((val) & PORT_P2_DIR_P2) >> 2) & 0x1) ++#define PORT_P2_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P2) | (((val) & 0x1) << 2)) ++/* Port 2 Pin #Direction Control (1) */ ++#define PORT_P2_DIR_P1 (0x1 << 1) ++#define PORT_P2_DIR_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P2_DIR_P1_GET(val) ((((val) & PORT_P2_DIR_P1) >> 1) & 0x1) ++#define PORT_P2_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P1) | (((val) & 0x1) << 1)) ++/* Port 2 Pin #Direction Control (0) */ ++#define PORT_P2_DIR_P0 (0x1) ++#define PORT_P2_DIR_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P2_DIR_P0_GET(val) ((((val) & PORT_P2_DIR_P0) >> 0) & 0x1) ++#define PORT_P2_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_DIR_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 2 Alternate Function Select Register 0 ++ ******************************************************************************/ ++ ++/* Alternate Function at Port 2 Bit # (19) */ ++#define PORT_P2_ALTSEL0_P19 (0x1 << 19) ++#define PORT_P2_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P2_ALTSEL0_P19_GET(val) ((((val) & PORT_P2_ALTSEL0_P19) >> 19) & 0x1) ++#define PORT_P2_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P19) | (((val) & 0x1) << 19)) ++/* Alternate Function at Port 2 Bit # (18) */ ++#define PORT_P2_ALTSEL0_P18 (0x1 << 18) ++#define PORT_P2_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P2_ALTSEL0_P18_GET(val) ((((val) & PORT_P2_ALTSEL0_P18) >> 18) & 0x1) ++#define PORT_P2_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P18) | (((val) & 0x1) << 18)) ++/* Alternate Function at Port 2 Bit # (17) */ ++#define PORT_P2_ALTSEL0_P17 (0x1 << 17) ++#define PORT_P2_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P2_ALTSEL0_P17_GET(val) ((((val) & PORT_P2_ALTSEL0_P17) >> 17) & 0x1) ++#define PORT_P2_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P17) | (((val) & 0x1) << 17)) ++/* Alternate Function at Port 2 Bit # (16) */ ++#define PORT_P2_ALTSEL0_P16 (0x1 << 16) ++#define PORT_P2_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P2_ALTSEL0_P16_GET(val) ((((val) & PORT_P2_ALTSEL0_P16) >> 16) & 0x1) ++#define PORT_P2_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P16) | (((val) & 0x1) << 16)) ++/* Alternate Function at Port 2 Bit # (15) */ ++#define PORT_P2_ALTSEL0_P15 (0x1 << 15) ++#define PORT_P2_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P2_ALTSEL0_P15_GET(val) ((((val) & PORT_P2_ALTSEL0_P15) >> 15) & 0x1) ++#define PORT_P2_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P15) | (((val) & 0x1) << 15)) ++/* Alternate Function at Port 2 Bit # (14) */ ++#define PORT_P2_ALTSEL0_P14 (0x1 << 14) ++#define PORT_P2_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P2_ALTSEL0_P14_GET(val) ((((val) & PORT_P2_ALTSEL0_P14) >> 14) & 0x1) ++#define PORT_P2_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P14) | (((val) & 0x1) << 14)) ++/* Alternate Function at Port 2 Bit # (13) */ ++#define PORT_P2_ALTSEL0_P13 (0x1 << 13) ++#define PORT_P2_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P2_ALTSEL0_P13_GET(val) ((((val) & PORT_P2_ALTSEL0_P13) >> 13) & 0x1) ++#define PORT_P2_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P13) | (((val) & 0x1) << 13)) ++/* Alternate Function at Port 2 Bit # (12) */ ++#define PORT_P2_ALTSEL0_P12 (0x1 << 12) ++#define PORT_P2_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P2_ALTSEL0_P12_GET(val) ((((val) & PORT_P2_ALTSEL0_P12) >> 12) & 0x1) ++#define PORT_P2_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P12) | (((val) & 0x1) << 12)) ++/* Alternate Function at Port 2 Bit # (11) */ ++#define PORT_P2_ALTSEL0_P11 (0x1 << 11) ++#define PORT_P2_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P2_ALTSEL0_P11_GET(val) ((((val) & PORT_P2_ALTSEL0_P11) >> 11) & 0x1) ++#define PORT_P2_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P11) | (((val) & 0x1) << 11)) ++/* Alternate Function at Port 2 Bit # (10) */ ++#define PORT_P2_ALTSEL0_P10 (0x1 << 10) ++#define PORT_P2_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P2_ALTSEL0_P10_GET(val) ((((val) & PORT_P2_ALTSEL0_P10) >> 10) & 0x1) ++#define PORT_P2_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P10) | (((val) & 0x1) << 10)) ++/* Alternate Function at Port 2 Bit # (9) */ ++#define PORT_P2_ALTSEL0_P9 (0x1 << 9) ++#define PORT_P2_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P2_ALTSEL0_P9_GET(val) ((((val) & PORT_P2_ALTSEL0_P9) >> 9) & 0x1) ++#define PORT_P2_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P9) | (((val) & 0x1) << 9)) ++/* Alternate Function at Port 2 Bit # (8) */ ++#define PORT_P2_ALTSEL0_P8 (0x1 << 8) ++#define PORT_P2_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P2_ALTSEL0_P8_GET(val) ((((val) & PORT_P2_ALTSEL0_P8) >> 8) & 0x1) ++#define PORT_P2_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P8) | (((val) & 0x1) << 8)) ++/* Alternate Function at Port 2 Bit # (7) */ ++#define PORT_P2_ALTSEL0_P7 (0x1 << 7) ++#define PORT_P2_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P2_ALTSEL0_P7_GET(val) ((((val) & PORT_P2_ALTSEL0_P7) >> 7) & 0x1) ++#define PORT_P2_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P7) | (((val) & 0x1) << 7)) ++/* Alternate Function at Port 2 Bit # (6) */ ++#define PORT_P2_ALTSEL0_P6 (0x1 << 6) ++#define PORT_P2_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P2_ALTSEL0_P6_GET(val) ((((val) & PORT_P2_ALTSEL0_P6) >> 6) & 0x1) ++#define PORT_P2_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P6) | (((val) & 0x1) << 6)) ++/* Alternate Function at Port 2 Bit # (5) */ ++#define PORT_P2_ALTSEL0_P5 (0x1 << 5) ++#define PORT_P2_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P2_ALTSEL0_P5_GET(val) ((((val) & PORT_P2_ALTSEL0_P5) >> 5) & 0x1) ++#define PORT_P2_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P5) | (((val) & 0x1) << 5)) ++/* Alternate Function at Port 2 Bit # (4) */ ++#define PORT_P2_ALTSEL0_P4 (0x1 << 4) ++#define PORT_P2_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P2_ALTSEL0_P4_GET(val) ((((val) & PORT_P2_ALTSEL0_P4) >> 4) & 0x1) ++#define PORT_P2_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P4) | (((val) & 0x1) << 4)) ++/* Alternate Function at Port 2 Bit # (3) */ ++#define PORT_P2_ALTSEL0_P3 (0x1 << 3) ++#define PORT_P2_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P2_ALTSEL0_P3_GET(val) ((((val) & PORT_P2_ALTSEL0_P3) >> 3) & 0x1) ++#define PORT_P2_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P3) | (((val) & 0x1) << 3)) ++/* Alternate Function at Port 2 Bit # (2) */ ++#define PORT_P2_ALTSEL0_P2 (0x1 << 2) ++#define PORT_P2_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P2_ALTSEL0_P2_GET(val) ((((val) & PORT_P2_ALTSEL0_P2) >> 2) & 0x1) ++#define PORT_P2_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P2) | (((val) & 0x1) << 2)) ++/* Alternate Function at Port 2 Bit # (1) */ ++#define PORT_P2_ALTSEL0_P1 (0x1 << 1) ++#define PORT_P2_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P2_ALTSEL0_P1_GET(val) ((((val) & PORT_P2_ALTSEL0_P1) >> 1) & 0x1) ++#define PORT_P2_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P1) | (((val) & 0x1) << 1)) ++/* Alternate Function at Port 2 Bit # (0) */ ++#define PORT_P2_ALTSEL0_P0 (0x1) ++#define PORT_P2_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P2_ALTSEL0_P0_GET(val) ((((val) & PORT_P2_ALTSEL0_P0) >> 0) & 0x1) ++#define PORT_P2_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_ALTSEL0_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 2 Pull Up Device Enable Register ++ ******************************************************************************/ ++ ++/* Pull Up Device Enable at Port 2 Bit # (19) */ ++#define PORT_P2_PUEN_P19 (0x1 << 19) ++#define PORT_P2_PUEN_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P2_PUEN_P19_GET(val) ((((val) & PORT_P2_PUEN_P19) >> 19) & 0x1) ++#define PORT_P2_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P19) | (((val) & 0x1) << 19)) ++/* Pull Up Device Enable at Port 2 Bit # (18) */ ++#define PORT_P2_PUEN_P18 (0x1 << 18) ++#define PORT_P2_PUEN_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P2_PUEN_P18_GET(val) ((((val) & PORT_P2_PUEN_P18) >> 18) & 0x1) ++#define PORT_P2_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P18) | (((val) & 0x1) << 18)) ++/* Pull Up Device Enable at Port 2 Bit # (17) */ ++#define PORT_P2_PUEN_P17 (0x1 << 17) ++#define PORT_P2_PUEN_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P2_PUEN_P17_GET(val) ((((val) & PORT_P2_PUEN_P17) >> 17) & 0x1) ++#define PORT_P2_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P17) | (((val) & 0x1) << 17)) ++/* Pull Up Device Enable at Port 2 Bit # (16) */ ++#define PORT_P2_PUEN_P16 (0x1 << 16) ++#define PORT_P2_PUEN_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P2_PUEN_P16_GET(val) ((((val) & PORT_P2_PUEN_P16) >> 16) & 0x1) ++#define PORT_P2_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P16) | (((val) & 0x1) << 16)) ++/* Pull Up Device Enable at Port 2 Bit # (15) */ ++#define PORT_P2_PUEN_P15 (0x1 << 15) ++#define PORT_P2_PUEN_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P2_PUEN_P15_GET(val) ((((val) & PORT_P2_PUEN_P15) >> 15) & 0x1) ++#define PORT_P2_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P15) | (((val) & 0x1) << 15)) ++/* Pull Up Device Enable at Port 2 Bit # (14) */ ++#define PORT_P2_PUEN_P14 (0x1 << 14) ++#define PORT_P2_PUEN_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P2_PUEN_P14_GET(val) ((((val) & PORT_P2_PUEN_P14) >> 14) & 0x1) ++#define PORT_P2_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P14) | (((val) & 0x1) << 14)) ++/* Pull Up Device Enable at Port 2 Bit # (13) */ ++#define PORT_P2_PUEN_P13 (0x1 << 13) ++#define PORT_P2_PUEN_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P2_PUEN_P13_GET(val) ((((val) & PORT_P2_PUEN_P13) >> 13) & 0x1) ++#define PORT_P2_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P13) | (((val) & 0x1) << 13)) ++/* Pull Up Device Enable at Port 2 Bit # (12) */ ++#define PORT_P2_PUEN_P12 (0x1 << 12) ++#define PORT_P2_PUEN_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P2_PUEN_P12_GET(val) ((((val) & PORT_P2_PUEN_P12) >> 12) & 0x1) ++#define PORT_P2_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P12) | (((val) & 0x1) << 12)) ++/* Pull Up Device Enable at Port 2 Bit # (11) */ ++#define PORT_P2_PUEN_P11 (0x1 << 11) ++#define PORT_P2_PUEN_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P2_PUEN_P11_GET(val) ((((val) & PORT_P2_PUEN_P11) >> 11) & 0x1) ++#define PORT_P2_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P11) | (((val) & 0x1) << 11)) ++/* Pull Up Device Enable at Port 2 Bit # (10) */ ++#define PORT_P2_PUEN_P10 (0x1 << 10) ++#define PORT_P2_PUEN_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P2_PUEN_P10_GET(val) ((((val) & PORT_P2_PUEN_P10) >> 10) & 0x1) ++#define PORT_P2_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P10) | (((val) & 0x1) << 10)) ++/* Pull Up Device Enable at Port 2 Bit # (9) */ ++#define PORT_P2_PUEN_P9 (0x1 << 9) ++#define PORT_P2_PUEN_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P2_PUEN_P9_GET(val) ((((val) & PORT_P2_PUEN_P9) >> 9) & 0x1) ++#define PORT_P2_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P9) | (((val) & 0x1) << 9)) ++/* Pull Up Device Enable at Port 2 Bit # (8) */ ++#define PORT_P2_PUEN_P8 (0x1 << 8) ++#define PORT_P2_PUEN_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P2_PUEN_P8_GET(val) ((((val) & PORT_P2_PUEN_P8) >> 8) & 0x1) ++#define PORT_P2_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P8) | (((val) & 0x1) << 8)) ++/* Pull Up Device Enable at Port 2 Bit # (7) */ ++#define PORT_P2_PUEN_P7 (0x1 << 7) ++#define PORT_P2_PUEN_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P2_PUEN_P7_GET(val) ((((val) & PORT_P2_PUEN_P7) >> 7) & 0x1) ++#define PORT_P2_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P7) | (((val) & 0x1) << 7)) ++/* Pull Up Device Enable at Port 2 Bit # (6) */ ++#define PORT_P2_PUEN_P6 (0x1 << 6) ++#define PORT_P2_PUEN_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P2_PUEN_P6_GET(val) ((((val) & PORT_P2_PUEN_P6) >> 6) & 0x1) ++#define PORT_P2_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P6) | (((val) & 0x1) << 6)) ++/* Pull Up Device Enable at Port 2 Bit # (5) */ ++#define PORT_P2_PUEN_P5 (0x1 << 5) ++#define PORT_P2_PUEN_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P2_PUEN_P5_GET(val) ((((val) & PORT_P2_PUEN_P5) >> 5) & 0x1) ++#define PORT_P2_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P5) | (((val) & 0x1) << 5)) ++/* Pull Up Device Enable at Port 2 Bit # (4) */ ++#define PORT_P2_PUEN_P4 (0x1 << 4) ++#define PORT_P2_PUEN_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P2_PUEN_P4_GET(val) ((((val) & PORT_P2_PUEN_P4) >> 4) & 0x1) ++#define PORT_P2_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P4) | (((val) & 0x1) << 4)) ++/* Pull Up Device Enable at Port 2 Bit # (3) */ ++#define PORT_P2_PUEN_P3 (0x1 << 3) ++#define PORT_P2_PUEN_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P2_PUEN_P3_GET(val) ((((val) & PORT_P2_PUEN_P3) >> 3) & 0x1) ++#define PORT_P2_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P3) | (((val) & 0x1) << 3)) ++/* Pull Up Device Enable at Port 2 Bit # (2) */ ++#define PORT_P2_PUEN_P2 (0x1 << 2) ++#define PORT_P2_PUEN_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P2_PUEN_P2_GET(val) ((((val) & PORT_P2_PUEN_P2) >> 2) & 0x1) ++#define PORT_P2_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P2) | (((val) & 0x1) << 2)) ++/* Pull Up Device Enable at Port 2 Bit # (1) */ ++#define PORT_P2_PUEN_P1 (0x1 << 1) ++#define PORT_P2_PUEN_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P2_PUEN_P1_GET(val) ((((val) & PORT_P2_PUEN_P1) >> 1) & 0x1) ++#define PORT_P2_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P1) | (((val) & 0x1) << 1)) ++/* Pull Up Device Enable at Port 2 Bit # (0) */ ++#define PORT_P2_PUEN_P0 (0x1) ++#define PORT_P2_PUEN_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P2_PUEN_P0_GET(val) ((((val) & PORT_P2_PUEN_P0) >> 0) & 0x1) ++#define PORT_P2_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P2_PUEN_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 3 Data Output Register ++ ******************************************************************************/ ++ ++/* Port 3 Pin # Output Value (19) */ ++#define PORT_P3_OUT_P19 (0x1 << 19) ++#define PORT_P3_OUT_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P3_OUT_P19_GET(val) ((((val) & PORT_P3_OUT_P19) >> 19) & 0x1) ++#define PORT_P3_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P19) | (((val) & 0x1) << 19)) ++/* Port 3 Pin # Output Value (18) */ ++#define PORT_P3_OUT_P18 (0x1 << 18) ++#define PORT_P3_OUT_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P3_OUT_P18_GET(val) ((((val) & PORT_P3_OUT_P18) >> 18) & 0x1) ++#define PORT_P3_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P18) | (((val) & 0x1) << 18)) ++/* Port 3 Pin # Output Value (17) */ ++#define PORT_P3_OUT_P17 (0x1 << 17) ++#define PORT_P3_OUT_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P3_OUT_P17_GET(val) ((((val) & PORT_P3_OUT_P17) >> 17) & 0x1) ++#define PORT_P3_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P17) | (((val) & 0x1) << 17)) ++/* Port 3 Pin # Output Value (16) */ ++#define PORT_P3_OUT_P16 (0x1 << 16) ++#define PORT_P3_OUT_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P3_OUT_P16_GET(val) ((((val) & PORT_P3_OUT_P16) >> 16) & 0x1) ++#define PORT_P3_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P16) | (((val) & 0x1) << 16)) ++/* Port 3 Pin # Output Value (15) */ ++#define PORT_P3_OUT_P15 (0x1 << 15) ++#define PORT_P3_OUT_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P3_OUT_P15_GET(val) ((((val) & PORT_P3_OUT_P15) >> 15) & 0x1) ++#define PORT_P3_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P15) | (((val) & 0x1) << 15)) ++/* Port 3 Pin # Output Value (14) */ ++#define PORT_P3_OUT_P14 (0x1 << 14) ++#define PORT_P3_OUT_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P3_OUT_P14_GET(val) ((((val) & PORT_P3_OUT_P14) >> 14) & 0x1) ++#define PORT_P3_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P14) | (((val) & 0x1) << 14)) ++/* Port 3 Pin # Output Value (13) */ ++#define PORT_P3_OUT_P13 (0x1 << 13) ++#define PORT_P3_OUT_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P3_OUT_P13_GET(val) ((((val) & PORT_P3_OUT_P13) >> 13) & 0x1) ++#define PORT_P3_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P13) | (((val) & 0x1) << 13)) ++/* Port 3 Pin # Output Value (12) */ ++#define PORT_P3_OUT_P12 (0x1 << 12) ++#define PORT_P3_OUT_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P3_OUT_P12_GET(val) ((((val) & PORT_P3_OUT_P12) >> 12) & 0x1) ++#define PORT_P3_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P12) | (((val) & 0x1) << 12)) ++/* Port 3 Pin # Output Value (11) */ ++#define PORT_P3_OUT_P11 (0x1 << 11) ++#define PORT_P3_OUT_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P3_OUT_P11_GET(val) ((((val) & PORT_P3_OUT_P11) >> 11) & 0x1) ++#define PORT_P3_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P11) | (((val) & 0x1) << 11)) ++/* Port 3 Pin # Output Value (10) */ ++#define PORT_P3_OUT_P10 (0x1 << 10) ++#define PORT_P3_OUT_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P3_OUT_P10_GET(val) ((((val) & PORT_P3_OUT_P10) >> 10) & 0x1) ++#define PORT_P3_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P10) | (((val) & 0x1) << 10)) ++/* Port 3 Pin # Output Value (9) */ ++#define PORT_P3_OUT_P9 (0x1 << 9) ++#define PORT_P3_OUT_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P3_OUT_P9_GET(val) ((((val) & PORT_P3_OUT_P9) >> 9) & 0x1) ++#define PORT_P3_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P9) | (((val) & 0x1) << 9)) ++/* Port 3 Pin # Output Value (8) */ ++#define PORT_P3_OUT_P8 (0x1 << 8) ++#define PORT_P3_OUT_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P3_OUT_P8_GET(val) ((((val) & PORT_P3_OUT_P8) >> 8) & 0x1) ++#define PORT_P3_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P8) | (((val) & 0x1) << 8)) ++/* Port 3 Pin # Output Value (7) */ ++#define PORT_P3_OUT_P7 (0x1 << 7) ++#define PORT_P3_OUT_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P3_OUT_P7_GET(val) ((((val) & PORT_P3_OUT_P7) >> 7) & 0x1) ++#define PORT_P3_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P7) | (((val) & 0x1) << 7)) ++/* Port 3 Pin # Output Value (6) */ ++#define PORT_P3_OUT_P6 (0x1 << 6) ++#define PORT_P3_OUT_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P3_OUT_P6_GET(val) ((((val) & PORT_P3_OUT_P6) >> 6) & 0x1) ++#define PORT_P3_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P6) | (((val) & 0x1) << 6)) ++/* Port 3 Pin # Output Value (5) */ ++#define PORT_P3_OUT_P5 (0x1 << 5) ++#define PORT_P3_OUT_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P3_OUT_P5_GET(val) ((((val) & PORT_P3_OUT_P5) >> 5) & 0x1) ++#define PORT_P3_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P5) | (((val) & 0x1) << 5)) ++/* Port 3 Pin # Output Value (4) */ ++#define PORT_P3_OUT_P4 (0x1 << 4) ++#define PORT_P3_OUT_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P3_OUT_P4_GET(val) ((((val) & PORT_P3_OUT_P4) >> 4) & 0x1) ++#define PORT_P3_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P4) | (((val) & 0x1) << 4)) ++/* Port 3 Pin # Output Value (3) */ ++#define PORT_P3_OUT_P3 (0x1 << 3) ++#define PORT_P3_OUT_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P3_OUT_P3_GET(val) ((((val) & PORT_P3_OUT_P3) >> 3) & 0x1) ++#define PORT_P3_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P3) | (((val) & 0x1) << 3)) ++/* Port 3 Pin # Output Value (2) */ ++#define PORT_P3_OUT_P2 (0x1 << 2) ++#define PORT_P3_OUT_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P3_OUT_P2_GET(val) ((((val) & PORT_P3_OUT_P2) >> 2) & 0x1) ++#define PORT_P3_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P2) | (((val) & 0x1) << 2)) ++/* Port 3 Pin # Output Value (1) */ ++#define PORT_P3_OUT_P1 (0x1 << 1) ++#define PORT_P3_OUT_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P3_OUT_P1_GET(val) ((((val) & PORT_P3_OUT_P1) >> 1) & 0x1) ++#define PORT_P3_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P1) | (((val) & 0x1) << 1)) ++/* Port 3 Pin # Output Value (0) */ ++#define PORT_P3_OUT_P0 (0x1) ++#define PORT_P3_OUT_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P3_OUT_P0_GET(val) ((((val) & PORT_P3_OUT_P0) >> 0) & 0x1) ++#define PORT_P3_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_OUT_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 3 Data Input Register ++ ******************************************************************************/ ++ ++/* Port 3 Pin # Latched Input Value (19) */ ++#define PORT_P3_IN_P19 (0x1 << 19) ++#define PORT_P3_IN_P19_GET(val) ((((val) & PORT_P3_IN_P19) >> 19) & 0x1) ++/* Port 3 Pin # Latched Input Value (18) */ ++#define PORT_P3_IN_P18 (0x1 << 18) ++#define PORT_P3_IN_P18_GET(val) ((((val) & PORT_P3_IN_P18) >> 18) & 0x1) ++/* Port 3 Pin # Latched Input Value (17) */ ++#define PORT_P3_IN_P17 (0x1 << 17) ++#define PORT_P3_IN_P17_GET(val) ((((val) & PORT_P3_IN_P17) >> 17) & 0x1) ++/* Port 3 Pin # Latched Input Value (16) */ ++#define PORT_P3_IN_P16 (0x1 << 16) ++#define PORT_P3_IN_P16_GET(val) ((((val) & PORT_P3_IN_P16) >> 16) & 0x1) ++/* Port 3 Pin # Latched Input Value (15) */ ++#define PORT_P3_IN_P15 (0x1 << 15) ++#define PORT_P3_IN_P15_GET(val) ((((val) & PORT_P3_IN_P15) >> 15) & 0x1) ++/* Port 3 Pin # Latched Input Value (14) */ ++#define PORT_P3_IN_P14 (0x1 << 14) ++#define PORT_P3_IN_P14_GET(val) ((((val) & PORT_P3_IN_P14) >> 14) & 0x1) ++/* Port 3 Pin # Latched Input Value (13) */ ++#define PORT_P3_IN_P13 (0x1 << 13) ++#define PORT_P3_IN_P13_GET(val) ((((val) & PORT_P3_IN_P13) >> 13) & 0x1) ++/* Port 3 Pin # Latched Input Value (12) */ ++#define PORT_P3_IN_P12 (0x1 << 12) ++#define PORT_P3_IN_P12_GET(val) ((((val) & PORT_P3_IN_P12) >> 12) & 0x1) ++/* Port 3 Pin # Latched Input Value (11) */ ++#define PORT_P3_IN_P11 (0x1 << 11) ++#define PORT_P3_IN_P11_GET(val) ((((val) & PORT_P3_IN_P11) >> 11) & 0x1) ++/* Port 3 Pin # Latched Input Value (10) */ ++#define PORT_P3_IN_P10 (0x1 << 10) ++#define PORT_P3_IN_P10_GET(val) ((((val) & PORT_P3_IN_P10) >> 10) & 0x1) ++/* Port 3 Pin # Latched Input Value (9) */ ++#define PORT_P3_IN_P9 (0x1 << 9) ++#define PORT_P3_IN_P9_GET(val) ((((val) & PORT_P3_IN_P9) >> 9) & 0x1) ++/* Port 3 Pin # Latched Input Value (8) */ ++#define PORT_P3_IN_P8 (0x1 << 8) ++#define PORT_P3_IN_P8_GET(val) ((((val) & PORT_P3_IN_P8) >> 8) & 0x1) ++/* Port 3 Pin # Latched Input Value (7) */ ++#define PORT_P3_IN_P7 (0x1 << 7) ++#define PORT_P3_IN_P7_GET(val) ((((val) & PORT_P3_IN_P7) >> 7) & 0x1) ++/* Port 3 Pin # Latched Input Value (6) */ ++#define PORT_P3_IN_P6 (0x1 << 6) ++#define PORT_P3_IN_P6_GET(val) ((((val) & PORT_P3_IN_P6) >> 6) & 0x1) ++/* Port 3 Pin # Latched Input Value (5) */ ++#define PORT_P3_IN_P5 (0x1 << 5) ++#define PORT_P3_IN_P5_GET(val) ((((val) & PORT_P3_IN_P5) >> 5) & 0x1) ++/* Port 3 Pin # Latched Input Value (4) */ ++#define PORT_P3_IN_P4 (0x1 << 4) ++#define PORT_P3_IN_P4_GET(val) ((((val) & PORT_P3_IN_P4) >> 4) & 0x1) ++/* Port 3 Pin # Latched Input Value (3) */ ++#define PORT_P3_IN_P3 (0x1 << 3) ++#define PORT_P3_IN_P3_GET(val) ((((val) & PORT_P3_IN_P3) >> 3) & 0x1) ++/* Port 3 Pin # Latched Input Value (2) */ ++#define PORT_P3_IN_P2 (0x1 << 2) ++#define PORT_P3_IN_P2_GET(val) ((((val) & PORT_P3_IN_P2) >> 2) & 0x1) ++/* Port 3 Pin # Latched Input Value (1) */ ++#define PORT_P3_IN_P1 (0x1 << 1) ++#define PORT_P3_IN_P1_GET(val) ((((val) & PORT_P3_IN_P1) >> 1) & 0x1) ++/* Port 3 Pin # Latched Input Value (0) */ ++#define PORT_P3_IN_P0 (0x1) ++#define PORT_P3_IN_P0_GET(val) ((((val) & PORT_P3_IN_P0) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Port 3 Direction Register ++ ******************************************************************************/ ++ ++/* Port 3 Pin #Direction Control (19) */ ++#define PORT_P3_DIR_P19 (0x1 << 19) ++#define PORT_P3_DIR_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P3_DIR_P19_GET(val) ((((val) & PORT_P3_DIR_P19) >> 19) & 0x1) ++#define PORT_P3_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P19) | (((val) & 0x1) << 19)) ++/* Port 3 Pin #Direction Control (18) */ ++#define PORT_P3_DIR_P18 (0x1 << 18) ++#define PORT_P3_DIR_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P3_DIR_P18_GET(val) ((((val) & PORT_P3_DIR_P18) >> 18) & 0x1) ++#define PORT_P3_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P18) | (((val) & 0x1) << 18)) ++/* Port 3 Pin #Direction Control (17) */ ++#define PORT_P3_DIR_P17 (0x1 << 17) ++#define PORT_P3_DIR_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P3_DIR_P17_GET(val) ((((val) & PORT_P3_DIR_P17) >> 17) & 0x1) ++#define PORT_P3_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P17) | (((val) & 0x1) << 17)) ++/* Port 3 Pin #Direction Control (16) */ ++#define PORT_P3_DIR_P16 (0x1 << 16) ++#define PORT_P3_DIR_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P3_DIR_P16_GET(val) ((((val) & PORT_P3_DIR_P16) >> 16) & 0x1) ++#define PORT_P3_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P16) | (((val) & 0x1) << 16)) ++/* Port 3 Pin #Direction Control (15) */ ++#define PORT_P3_DIR_P15 (0x1 << 15) ++#define PORT_P3_DIR_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P3_DIR_P15_GET(val) ((((val) & PORT_P3_DIR_P15) >> 15) & 0x1) ++#define PORT_P3_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P15) | (((val) & 0x1) << 15)) ++/* Port 3 Pin #Direction Control (14) */ ++#define PORT_P3_DIR_P14 (0x1 << 14) ++#define PORT_P3_DIR_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P3_DIR_P14_GET(val) ((((val) & PORT_P3_DIR_P14) >> 14) & 0x1) ++#define PORT_P3_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P14) | (((val) & 0x1) << 14)) ++/* Port 3 Pin #Direction Control (13) */ ++#define PORT_P3_DIR_P13 (0x1 << 13) ++#define PORT_P3_DIR_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P3_DIR_P13_GET(val) ((((val) & PORT_P3_DIR_P13) >> 13) & 0x1) ++#define PORT_P3_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P13) | (((val) & 0x1) << 13)) ++/* Port 3 Pin #Direction Control (12) */ ++#define PORT_P3_DIR_P12 (0x1 << 12) ++#define PORT_P3_DIR_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P3_DIR_P12_GET(val) ((((val) & PORT_P3_DIR_P12) >> 12) & 0x1) ++#define PORT_P3_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P12) | (((val) & 0x1) << 12)) ++/* Port 3 Pin #Direction Control (11) */ ++#define PORT_P3_DIR_P11 (0x1 << 11) ++#define PORT_P3_DIR_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P3_DIR_P11_GET(val) ((((val) & PORT_P3_DIR_P11) >> 11) & 0x1) ++#define PORT_P3_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P11) | (((val) & 0x1) << 11)) ++/* Port 3 Pin #Direction Control (10) */ ++#define PORT_P3_DIR_P10 (0x1 << 10) ++#define PORT_P3_DIR_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P3_DIR_P10_GET(val) ((((val) & PORT_P3_DIR_P10) >> 10) & 0x1) ++#define PORT_P3_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P10) | (((val) & 0x1) << 10)) ++/* Port 3 Pin #Direction Control (9) */ ++#define PORT_P3_DIR_P9 (0x1 << 9) ++#define PORT_P3_DIR_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P3_DIR_P9_GET(val) ((((val) & PORT_P3_DIR_P9) >> 9) & 0x1) ++#define PORT_P3_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P9) | (((val) & 0x1) << 9)) ++/* Port 3 Pin #Direction Control (8) */ ++#define PORT_P3_DIR_P8 (0x1 << 8) ++#define PORT_P3_DIR_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P3_DIR_P8_GET(val) ((((val) & PORT_P3_DIR_P8) >> 8) & 0x1) ++#define PORT_P3_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P8) | (((val) & 0x1) << 8)) ++/* Port 3 Pin #Direction Control (7) */ ++#define PORT_P3_DIR_P7 (0x1 << 7) ++#define PORT_P3_DIR_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P3_DIR_P7_GET(val) ((((val) & PORT_P3_DIR_P7) >> 7) & 0x1) ++#define PORT_P3_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P7) | (((val) & 0x1) << 7)) ++/* Port 3 Pin #Direction Control (6) */ ++#define PORT_P3_DIR_P6 (0x1 << 6) ++#define PORT_P3_DIR_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P3_DIR_P6_GET(val) ((((val) & PORT_P3_DIR_P6) >> 6) & 0x1) ++#define PORT_P3_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P6) | (((val) & 0x1) << 6)) ++/* Port 3 Pin #Direction Control (5) */ ++#define PORT_P3_DIR_P5 (0x1 << 5) ++#define PORT_P3_DIR_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P3_DIR_P5_GET(val) ((((val) & PORT_P3_DIR_P5) >> 5) & 0x1) ++#define PORT_P3_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P5) | (((val) & 0x1) << 5)) ++/* Port 3 Pin #Direction Control (4) */ ++#define PORT_P3_DIR_P4 (0x1 << 4) ++#define PORT_P3_DIR_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P3_DIR_P4_GET(val) ((((val) & PORT_P3_DIR_P4) >> 4) & 0x1) ++#define PORT_P3_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P4) | (((val) & 0x1) << 4)) ++/* Port 3 Pin #Direction Control (3) */ ++#define PORT_P3_DIR_P3 (0x1 << 3) ++#define PORT_P3_DIR_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P3_DIR_P3_GET(val) ((((val) & PORT_P3_DIR_P3) >> 3) & 0x1) ++#define PORT_P3_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P3) | (((val) & 0x1) << 3)) ++/* Port 3 Pin #Direction Control (2) */ ++#define PORT_P3_DIR_P2 (0x1 << 2) ++#define PORT_P3_DIR_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P3_DIR_P2_GET(val) ((((val) & PORT_P3_DIR_P2) >> 2) & 0x1) ++#define PORT_P3_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P2) | (((val) & 0x1) << 2)) ++/* Port 3 Pin #Direction Control (1) */ ++#define PORT_P3_DIR_P1 (0x1 << 1) ++#define PORT_P3_DIR_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P3_DIR_P1_GET(val) ((((val) & PORT_P3_DIR_P1) >> 1) & 0x1) ++#define PORT_P3_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P1) | (((val) & 0x1) << 1)) ++/* Port 3 Pin #Direction Control (0) */ ++#define PORT_P3_DIR_P0 (0x1) ++#define PORT_P3_DIR_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P3_DIR_P0_GET(val) ((((val) & PORT_P3_DIR_P0) >> 0) & 0x1) ++#define PORT_P3_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_DIR_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 3 Alternate Function Select Register 0 ++ ******************************************************************************/ ++ ++/* Alternate Function at Port 3 Bit # (19) */ ++#define PORT_P3_ALTSEL0_P19 (0x1 << 19) ++#define PORT_P3_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P3_ALTSEL0_P19_GET(val) ((((val) & PORT_P3_ALTSEL0_P19) >> 19) & 0x1) ++#define PORT_P3_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P19) | (((val) & 0x1) << 19)) ++/* Alternate Function at Port 3 Bit # (18) */ ++#define PORT_P3_ALTSEL0_P18 (0x1 << 18) ++#define PORT_P3_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P3_ALTSEL0_P18_GET(val) ((((val) & PORT_P3_ALTSEL0_P18) >> 18) & 0x1) ++#define PORT_P3_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P18) | (((val) & 0x1) << 18)) ++/* Alternate Function at Port 3 Bit # (17) */ ++#define PORT_P3_ALTSEL0_P17 (0x1 << 17) ++#define PORT_P3_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P3_ALTSEL0_P17_GET(val) ((((val) & PORT_P3_ALTSEL0_P17) >> 17) & 0x1) ++#define PORT_P3_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P17) | (((val) & 0x1) << 17)) ++/* Alternate Function at Port 3 Bit # (16) */ ++#define PORT_P3_ALTSEL0_P16 (0x1 << 16) ++#define PORT_P3_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P3_ALTSEL0_P16_GET(val) ((((val) & PORT_P3_ALTSEL0_P16) >> 16) & 0x1) ++#define PORT_P3_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P16) | (((val) & 0x1) << 16)) ++/* Alternate Function at Port 3 Bit # (15) */ ++#define PORT_P3_ALTSEL0_P15 (0x1 << 15) ++#define PORT_P3_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P3_ALTSEL0_P15_GET(val) ((((val) & PORT_P3_ALTSEL0_P15) >> 15) & 0x1) ++#define PORT_P3_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P15) | (((val) & 0x1) << 15)) ++/* Alternate Function at Port 3 Bit # (14) */ ++#define PORT_P3_ALTSEL0_P14 (0x1 << 14) ++#define PORT_P3_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P3_ALTSEL0_P14_GET(val) ((((val) & PORT_P3_ALTSEL0_P14) >> 14) & 0x1) ++#define PORT_P3_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P14) | (((val) & 0x1) << 14)) ++/* Alternate Function at Port 3 Bit # (13) */ ++#define PORT_P3_ALTSEL0_P13 (0x1 << 13) ++#define PORT_P3_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P3_ALTSEL0_P13_GET(val) ((((val) & PORT_P3_ALTSEL0_P13) >> 13) & 0x1) ++#define PORT_P3_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P13) | (((val) & 0x1) << 13)) ++/* Alternate Function at Port 3 Bit # (12) */ ++#define PORT_P3_ALTSEL0_P12 (0x1 << 12) ++#define PORT_P3_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P3_ALTSEL0_P12_GET(val) ((((val) & PORT_P3_ALTSEL0_P12) >> 12) & 0x1) ++#define PORT_P3_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P12) | (((val) & 0x1) << 12)) ++/* Alternate Function at Port 3 Bit # (11) */ ++#define PORT_P3_ALTSEL0_P11 (0x1 << 11) ++#define PORT_P3_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P3_ALTSEL0_P11_GET(val) ((((val) & PORT_P3_ALTSEL0_P11) >> 11) & 0x1) ++#define PORT_P3_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P11) | (((val) & 0x1) << 11)) ++/* Alternate Function at Port 3 Bit # (10) */ ++#define PORT_P3_ALTSEL0_P10 (0x1 << 10) ++#define PORT_P3_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P3_ALTSEL0_P10_GET(val) ((((val) & PORT_P3_ALTSEL0_P10) >> 10) & 0x1) ++#define PORT_P3_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P10) | (((val) & 0x1) << 10)) ++/* Alternate Function at Port 3 Bit # (9) */ ++#define PORT_P3_ALTSEL0_P9 (0x1 << 9) ++#define PORT_P3_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P3_ALTSEL0_P9_GET(val) ((((val) & PORT_P3_ALTSEL0_P9) >> 9) & 0x1) ++#define PORT_P3_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P9) | (((val) & 0x1) << 9)) ++/* Alternate Function at Port 3 Bit # (8) */ ++#define PORT_P3_ALTSEL0_P8 (0x1 << 8) ++#define PORT_P3_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P3_ALTSEL0_P8_GET(val) ((((val) & PORT_P3_ALTSEL0_P8) >> 8) & 0x1) ++#define PORT_P3_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P8) | (((val) & 0x1) << 8)) ++/* Alternate Function at Port 3 Bit # (7) */ ++#define PORT_P3_ALTSEL0_P7 (0x1 << 7) ++#define PORT_P3_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P3_ALTSEL0_P7_GET(val) ((((val) & PORT_P3_ALTSEL0_P7) >> 7) & 0x1) ++#define PORT_P3_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P7) | (((val) & 0x1) << 7)) ++/* Alternate Function at Port 3 Bit # (6) */ ++#define PORT_P3_ALTSEL0_P6 (0x1 << 6) ++#define PORT_P3_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P3_ALTSEL0_P6_GET(val) ((((val) & PORT_P3_ALTSEL0_P6) >> 6) & 0x1) ++#define PORT_P3_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P6) | (((val) & 0x1) << 6)) ++/* Alternate Function at Port 3 Bit # (5) */ ++#define PORT_P3_ALTSEL0_P5 (0x1 << 5) ++#define PORT_P3_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P3_ALTSEL0_P5_GET(val) ((((val) & PORT_P3_ALTSEL0_P5) >> 5) & 0x1) ++#define PORT_P3_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P5) | (((val) & 0x1) << 5)) ++/* Alternate Function at Port 3 Bit # (4) */ ++#define PORT_P3_ALTSEL0_P4 (0x1 << 4) ++#define PORT_P3_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P3_ALTSEL0_P4_GET(val) ((((val) & PORT_P3_ALTSEL0_P4) >> 4) & 0x1) ++#define PORT_P3_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P4) | (((val) & 0x1) << 4)) ++/* Alternate Function at Port 3 Bit # (3) */ ++#define PORT_P3_ALTSEL0_P3 (0x1 << 3) ++#define PORT_P3_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P3_ALTSEL0_P3_GET(val) ((((val) & PORT_P3_ALTSEL0_P3) >> 3) & 0x1) ++#define PORT_P3_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P3) | (((val) & 0x1) << 3)) ++/* Alternate Function at Port 3 Bit # (2) */ ++#define PORT_P3_ALTSEL0_P2 (0x1 << 2) ++#define PORT_P3_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P3_ALTSEL0_P2_GET(val) ((((val) & PORT_P3_ALTSEL0_P2) >> 2) & 0x1) ++#define PORT_P3_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P2) | (((val) & 0x1) << 2)) ++/* Alternate Function at Port 3 Bit # (1) */ ++#define PORT_P3_ALTSEL0_P1 (0x1 << 1) ++#define PORT_P3_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P3_ALTSEL0_P1_GET(val) ((((val) & PORT_P3_ALTSEL0_P1) >> 1) & 0x1) ++#define PORT_P3_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P1) | (((val) & 0x1) << 1)) ++/* Alternate Function at Port 3 Bit # (0) */ ++#define PORT_P3_ALTSEL0_P0 (0x1) ++#define PORT_P3_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P3_ALTSEL0_P0_GET(val) ((((val) & PORT_P3_ALTSEL0_P0) >> 0) & 0x1) ++#define PORT_P3_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_ALTSEL0_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 3 Pull Up Device Enable Register ++ ******************************************************************************/ ++ ++/* Pull Up Device Enable at Port 3 Bit # (19) */ ++#define PORT_P3_PUEN_P19 (0x1 << 19) ++#define PORT_P3_PUEN_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P3_PUEN_P19_GET(val) ((((val) & PORT_P3_PUEN_P19) >> 19) & 0x1) ++#define PORT_P3_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P19) | (((val) & 0x1) << 19)) ++/* Pull Up Device Enable at Port 3 Bit # (18) */ ++#define PORT_P3_PUEN_P18 (0x1 << 18) ++#define PORT_P3_PUEN_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P3_PUEN_P18_GET(val) ((((val) & PORT_P3_PUEN_P18) >> 18) & 0x1) ++#define PORT_P3_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P18) | (((val) & 0x1) << 18)) ++/* Pull Up Device Enable at Port 3 Bit # (17) */ ++#define PORT_P3_PUEN_P17 (0x1 << 17) ++#define PORT_P3_PUEN_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P3_PUEN_P17_GET(val) ((((val) & PORT_P3_PUEN_P17) >> 17) & 0x1) ++#define PORT_P3_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P17) | (((val) & 0x1) << 17)) ++/* Pull Up Device Enable at Port 3 Bit # (16) */ ++#define PORT_P3_PUEN_P16 (0x1 << 16) ++#define PORT_P3_PUEN_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P3_PUEN_P16_GET(val) ((((val) & PORT_P3_PUEN_P16) >> 16) & 0x1) ++#define PORT_P3_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P16) | (((val) & 0x1) << 16)) ++/* Pull Up Device Enable at Port 3 Bit # (15) */ ++#define PORT_P3_PUEN_P15 (0x1 << 15) ++#define PORT_P3_PUEN_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P3_PUEN_P15_GET(val) ((((val) & PORT_P3_PUEN_P15) >> 15) & 0x1) ++#define PORT_P3_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P15) | (((val) & 0x1) << 15)) ++/* Pull Up Device Enable at Port 3 Bit # (14) */ ++#define PORT_P3_PUEN_P14 (0x1 << 14) ++#define PORT_P3_PUEN_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P3_PUEN_P14_GET(val) ((((val) & PORT_P3_PUEN_P14) >> 14) & 0x1) ++#define PORT_P3_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P14) | (((val) & 0x1) << 14)) ++/* Pull Up Device Enable at Port 3 Bit # (13) */ ++#define PORT_P3_PUEN_P13 (0x1 << 13) ++#define PORT_P3_PUEN_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P3_PUEN_P13_GET(val) ((((val) & PORT_P3_PUEN_P13) >> 13) & 0x1) ++#define PORT_P3_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P13) | (((val) & 0x1) << 13)) ++/* Pull Up Device Enable at Port 3 Bit # (12) */ ++#define PORT_P3_PUEN_P12 (0x1 << 12) ++#define PORT_P3_PUEN_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P3_PUEN_P12_GET(val) ((((val) & PORT_P3_PUEN_P12) >> 12) & 0x1) ++#define PORT_P3_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P12) | (((val) & 0x1) << 12)) ++/* Pull Up Device Enable at Port 3 Bit # (11) */ ++#define PORT_P3_PUEN_P11 (0x1 << 11) ++#define PORT_P3_PUEN_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P3_PUEN_P11_GET(val) ((((val) & PORT_P3_PUEN_P11) >> 11) & 0x1) ++#define PORT_P3_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P11) | (((val) & 0x1) << 11)) ++/* Pull Up Device Enable at Port 3 Bit # (10) */ ++#define PORT_P3_PUEN_P10 (0x1 << 10) ++#define PORT_P3_PUEN_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P3_PUEN_P10_GET(val) ((((val) & PORT_P3_PUEN_P10) >> 10) & 0x1) ++#define PORT_P3_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P10) | (((val) & 0x1) << 10)) ++/* Pull Up Device Enable at Port 3 Bit # (9) */ ++#define PORT_P3_PUEN_P9 (0x1 << 9) ++#define PORT_P3_PUEN_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P3_PUEN_P9_GET(val) ((((val) & PORT_P3_PUEN_P9) >> 9) & 0x1) ++#define PORT_P3_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P9) | (((val) & 0x1) << 9)) ++/* Pull Up Device Enable at Port 3 Bit # (8) */ ++#define PORT_P3_PUEN_P8 (0x1 << 8) ++#define PORT_P3_PUEN_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P3_PUEN_P8_GET(val) ((((val) & PORT_P3_PUEN_P8) >> 8) & 0x1) ++#define PORT_P3_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P8) | (((val) & 0x1) << 8)) ++/* Pull Up Device Enable at Port 3 Bit # (7) */ ++#define PORT_P3_PUEN_P7 (0x1 << 7) ++#define PORT_P3_PUEN_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P3_PUEN_P7_GET(val) ((((val) & PORT_P3_PUEN_P7) >> 7) & 0x1) ++#define PORT_P3_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P7) | (((val) & 0x1) << 7)) ++/* Pull Up Device Enable at Port 3 Bit # (6) */ ++#define PORT_P3_PUEN_P6 (0x1 << 6) ++#define PORT_P3_PUEN_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P3_PUEN_P6_GET(val) ((((val) & PORT_P3_PUEN_P6) >> 6) & 0x1) ++#define PORT_P3_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P6) | (((val) & 0x1) << 6)) ++/* Pull Up Device Enable at Port 3 Bit # (5) */ ++#define PORT_P3_PUEN_P5 (0x1 << 5) ++#define PORT_P3_PUEN_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P3_PUEN_P5_GET(val) ((((val) & PORT_P3_PUEN_P5) >> 5) & 0x1) ++#define PORT_P3_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P5) | (((val) & 0x1) << 5)) ++/* Pull Up Device Enable at Port 3 Bit # (4) */ ++#define PORT_P3_PUEN_P4 (0x1 << 4) ++#define PORT_P3_PUEN_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P3_PUEN_P4_GET(val) ((((val) & PORT_P3_PUEN_P4) >> 4) & 0x1) ++#define PORT_P3_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P4) | (((val) & 0x1) << 4)) ++/* Pull Up Device Enable at Port 3 Bit # (3) */ ++#define PORT_P3_PUEN_P3 (0x1 << 3) ++#define PORT_P3_PUEN_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P3_PUEN_P3_GET(val) ((((val) & PORT_P3_PUEN_P3) >> 3) & 0x1) ++#define PORT_P3_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P3) | (((val) & 0x1) << 3)) ++/* Pull Up Device Enable at Port 3 Bit # (2) */ ++#define PORT_P3_PUEN_P2 (0x1 << 2) ++#define PORT_P3_PUEN_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P3_PUEN_P2_GET(val) ((((val) & PORT_P3_PUEN_P2) >> 2) & 0x1) ++#define PORT_P3_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P2) | (((val) & 0x1) << 2)) ++/* Pull Up Device Enable at Port 3 Bit # (1) */ ++#define PORT_P3_PUEN_P1 (0x1 << 1) ++#define PORT_P3_PUEN_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P3_PUEN_P1_GET(val) ((((val) & PORT_P3_PUEN_P1) >> 1) & 0x1) ++#define PORT_P3_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P1) | (((val) & 0x1) << 1)) ++/* Pull Up Device Enable at Port 3 Bit # (0) */ ++#define PORT_P3_PUEN_P0 (0x1) ++#define PORT_P3_PUEN_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P3_PUEN_P0_GET(val) ((((val) & PORT_P3_PUEN_P0) >> 0) & 0x1) ++#define PORT_P3_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P3_PUEN_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 4 Data Output Register ++ ******************************************************************************/ ++ ++/* Port 4 Pin # Output Value (23) */ ++#define PORT_P4_OUT_P23 (0x1 << 23) ++#define PORT_P4_OUT_P23_VAL(val) (((val) & 0x1) << 23) ++#define PORT_P4_OUT_P23_GET(val) ((((val) & PORT_P4_OUT_P23) >> 23) & 0x1) ++#define PORT_P4_OUT_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P23) | (((val) & 0x1) << 23)) ++/* Port 4 Pin # Output Value (22) */ ++#define PORT_P4_OUT_P22 (0x1 << 22) ++#define PORT_P4_OUT_P22_VAL(val) (((val) & 0x1) << 22) ++#define PORT_P4_OUT_P22_GET(val) ((((val) & PORT_P4_OUT_P22) >> 22) & 0x1) ++#define PORT_P4_OUT_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P22) | (((val) & 0x1) << 22)) ++/* Port 4 Pin # Output Value (21) */ ++#define PORT_P4_OUT_P21 (0x1 << 21) ++#define PORT_P4_OUT_P21_VAL(val) (((val) & 0x1) << 21) ++#define PORT_P4_OUT_P21_GET(val) ((((val) & PORT_P4_OUT_P21) >> 21) & 0x1) ++#define PORT_P4_OUT_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P21) | (((val) & 0x1) << 21)) ++/* Port 4 Pin # Output Value (20) */ ++#define PORT_P4_OUT_P20 (0x1 << 20) ++#define PORT_P4_OUT_P20_VAL(val) (((val) & 0x1) << 20) ++#define PORT_P4_OUT_P20_GET(val) ((((val) & PORT_P4_OUT_P20) >> 20) & 0x1) ++#define PORT_P4_OUT_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P20) | (((val) & 0x1) << 20)) ++/* Port 4 Pin # Output Value (19) */ ++#define PORT_P4_OUT_P19 (0x1 << 19) ++#define PORT_P4_OUT_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P4_OUT_P19_GET(val) ((((val) & PORT_P4_OUT_P19) >> 19) & 0x1) ++#define PORT_P4_OUT_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P19) | (((val) & 0x1) << 19)) ++/* Port 4 Pin # Output Value (18) */ ++#define PORT_P4_OUT_P18 (0x1 << 18) ++#define PORT_P4_OUT_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P4_OUT_P18_GET(val) ((((val) & PORT_P4_OUT_P18) >> 18) & 0x1) ++#define PORT_P4_OUT_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P18) | (((val) & 0x1) << 18)) ++/* Port 4 Pin # Output Value (17) */ ++#define PORT_P4_OUT_P17 (0x1 << 17) ++#define PORT_P4_OUT_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P4_OUT_P17_GET(val) ((((val) & PORT_P4_OUT_P17) >> 17) & 0x1) ++#define PORT_P4_OUT_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P17) | (((val) & 0x1) << 17)) ++/* Port 4 Pin # Output Value (16) */ ++#define PORT_P4_OUT_P16 (0x1 << 16) ++#define PORT_P4_OUT_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P4_OUT_P16_GET(val) ((((val) & PORT_P4_OUT_P16) >> 16) & 0x1) ++#define PORT_P4_OUT_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P16) | (((val) & 0x1) << 16)) ++/* Port 4 Pin # Output Value (15) */ ++#define PORT_P4_OUT_P15 (0x1 << 15) ++#define PORT_P4_OUT_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P4_OUT_P15_GET(val) ((((val) & PORT_P4_OUT_P15) >> 15) & 0x1) ++#define PORT_P4_OUT_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P15) | (((val) & 0x1) << 15)) ++/* Port 4 Pin # Output Value (14) */ ++#define PORT_P4_OUT_P14 (0x1 << 14) ++#define PORT_P4_OUT_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P4_OUT_P14_GET(val) ((((val) & PORT_P4_OUT_P14) >> 14) & 0x1) ++#define PORT_P4_OUT_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P14) | (((val) & 0x1) << 14)) ++/* Port 4 Pin # Output Value (13) */ ++#define PORT_P4_OUT_P13 (0x1 << 13) ++#define PORT_P4_OUT_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P4_OUT_P13_GET(val) ((((val) & PORT_P4_OUT_P13) >> 13) & 0x1) ++#define PORT_P4_OUT_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P13) | (((val) & 0x1) << 13)) ++/* Port 4 Pin # Output Value (12) */ ++#define PORT_P4_OUT_P12 (0x1 << 12) ++#define PORT_P4_OUT_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P4_OUT_P12_GET(val) ((((val) & PORT_P4_OUT_P12) >> 12) & 0x1) ++#define PORT_P4_OUT_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P12) | (((val) & 0x1) << 12)) ++/* Port 4 Pin # Output Value (11) */ ++#define PORT_P4_OUT_P11 (0x1 << 11) ++#define PORT_P4_OUT_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P4_OUT_P11_GET(val) ((((val) & PORT_P4_OUT_P11) >> 11) & 0x1) ++#define PORT_P4_OUT_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P11) | (((val) & 0x1) << 11)) ++/* Port 4 Pin # Output Value (10) */ ++#define PORT_P4_OUT_P10 (0x1 << 10) ++#define PORT_P4_OUT_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P4_OUT_P10_GET(val) ((((val) & PORT_P4_OUT_P10) >> 10) & 0x1) ++#define PORT_P4_OUT_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P10) | (((val) & 0x1) << 10)) ++/* Port 4 Pin # Output Value (9) */ ++#define PORT_P4_OUT_P9 (0x1 << 9) ++#define PORT_P4_OUT_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P4_OUT_P9_GET(val) ((((val) & PORT_P4_OUT_P9) >> 9) & 0x1) ++#define PORT_P4_OUT_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P9) | (((val) & 0x1) << 9)) ++/* Port 4 Pin # Output Value (8) */ ++#define PORT_P4_OUT_P8 (0x1 << 8) ++#define PORT_P4_OUT_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P4_OUT_P8_GET(val) ((((val) & PORT_P4_OUT_P8) >> 8) & 0x1) ++#define PORT_P4_OUT_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P8) | (((val) & 0x1) << 8)) ++/* Port 4 Pin # Output Value (7) */ ++#define PORT_P4_OUT_P7 (0x1 << 7) ++#define PORT_P4_OUT_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P4_OUT_P7_GET(val) ((((val) & PORT_P4_OUT_P7) >> 7) & 0x1) ++#define PORT_P4_OUT_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P7) | (((val) & 0x1) << 7)) ++/* Port 4 Pin # Output Value (6) */ ++#define PORT_P4_OUT_P6 (0x1 << 6) ++#define PORT_P4_OUT_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P4_OUT_P6_GET(val) ((((val) & PORT_P4_OUT_P6) >> 6) & 0x1) ++#define PORT_P4_OUT_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P6) | (((val) & 0x1) << 6)) ++/* Port 4 Pin # Output Value (5) */ ++#define PORT_P4_OUT_P5 (0x1 << 5) ++#define PORT_P4_OUT_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P4_OUT_P5_GET(val) ((((val) & PORT_P4_OUT_P5) >> 5) & 0x1) ++#define PORT_P4_OUT_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P5) | (((val) & 0x1) << 5)) ++/* Port 4 Pin # Output Value (4) */ ++#define PORT_P4_OUT_P4 (0x1 << 4) ++#define PORT_P4_OUT_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P4_OUT_P4_GET(val) ((((val) & PORT_P4_OUT_P4) >> 4) & 0x1) ++#define PORT_P4_OUT_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P4) | (((val) & 0x1) << 4)) ++/* Port 4 Pin # Output Value (3) */ ++#define PORT_P4_OUT_P3 (0x1 << 3) ++#define PORT_P4_OUT_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P4_OUT_P3_GET(val) ((((val) & PORT_P4_OUT_P3) >> 3) & 0x1) ++#define PORT_P4_OUT_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P3) | (((val) & 0x1) << 3)) ++/* Port 4 Pin # Output Value (2) */ ++#define PORT_P4_OUT_P2 (0x1 << 2) ++#define PORT_P4_OUT_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P4_OUT_P2_GET(val) ((((val) & PORT_P4_OUT_P2) >> 2) & 0x1) ++#define PORT_P4_OUT_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P2) | (((val) & 0x1) << 2)) ++/* Port 4 Pin # Output Value (1) */ ++#define PORT_P4_OUT_P1 (0x1 << 1) ++#define PORT_P4_OUT_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P4_OUT_P1_GET(val) ((((val) & PORT_P4_OUT_P1) >> 1) & 0x1) ++#define PORT_P4_OUT_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P1) | (((val) & 0x1) << 1)) ++/* Port 4 Pin # Output Value (0) */ ++#define PORT_P4_OUT_P0 (0x1) ++#define PORT_P4_OUT_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P4_OUT_P0_GET(val) ((((val) & PORT_P4_OUT_P0) >> 0) & 0x1) ++#define PORT_P4_OUT_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_OUT_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 4 Data Input Register ++ ******************************************************************************/ ++ ++/* Port 4 Pin # Latched Input Value (23) */ ++#define PORT_P4_IN_P23 (0x1 << 23) ++#define PORT_P4_IN_P23_GET(val) ((((val) & PORT_P4_IN_P23) >> 23) & 0x1) ++/* Port 4 Pin # Latched Input Value (22) */ ++#define PORT_P4_IN_P22 (0x1 << 22) ++#define PORT_P4_IN_P22_GET(val) ((((val) & PORT_P4_IN_P22) >> 22) & 0x1) ++/* Port 4 Pin # Latched Input Value (21) */ ++#define PORT_P4_IN_P21 (0x1 << 21) ++#define PORT_P4_IN_P21_GET(val) ((((val) & PORT_P4_IN_P21) >> 21) & 0x1) ++/* Port 4 Pin # Latched Input Value (20) */ ++#define PORT_P4_IN_P20 (0x1 << 20) ++#define PORT_P4_IN_P20_GET(val) ((((val) & PORT_P4_IN_P20) >> 20) & 0x1) ++/* Port 4 Pin # Latched Input Value (19) */ ++#define PORT_P4_IN_P19 (0x1 << 19) ++#define PORT_P4_IN_P19_GET(val) ((((val) & PORT_P4_IN_P19) >> 19) & 0x1) ++/* Port 4 Pin # Latched Input Value (18) */ ++#define PORT_P4_IN_P18 (0x1 << 18) ++#define PORT_P4_IN_P18_GET(val) ((((val) & PORT_P4_IN_P18) >> 18) & 0x1) ++/* Port 4 Pin # Latched Input Value (17) */ ++#define PORT_P4_IN_P17 (0x1 << 17) ++#define PORT_P4_IN_P17_GET(val) ((((val) & PORT_P4_IN_P17) >> 17) & 0x1) ++/* Port 4 Pin # Latched Input Value (16) */ ++#define PORT_P4_IN_P16 (0x1 << 16) ++#define PORT_P4_IN_P16_GET(val) ((((val) & PORT_P4_IN_P16) >> 16) & 0x1) ++/* Port 4 Pin # Latched Input Value (15) */ ++#define PORT_P4_IN_P15 (0x1 << 15) ++#define PORT_P4_IN_P15_GET(val) ((((val) & PORT_P4_IN_P15) >> 15) & 0x1) ++/* Port 4 Pin # Latched Input Value (14) */ ++#define PORT_P4_IN_P14 (0x1 << 14) ++#define PORT_P4_IN_P14_GET(val) ((((val) & PORT_P4_IN_P14) >> 14) & 0x1) ++/* Port 4 Pin # Latched Input Value (13) */ ++#define PORT_P4_IN_P13 (0x1 << 13) ++#define PORT_P4_IN_P13_GET(val) ((((val) & PORT_P4_IN_P13) >> 13) & 0x1) ++/* Port 4 Pin # Latched Input Value (12) */ ++#define PORT_P4_IN_P12 (0x1 << 12) ++#define PORT_P4_IN_P12_GET(val) ((((val) & PORT_P4_IN_P12) >> 12) & 0x1) ++/* Port 4 Pin # Latched Input Value (11) */ ++#define PORT_P4_IN_P11 (0x1 << 11) ++#define PORT_P4_IN_P11_GET(val) ((((val) & PORT_P4_IN_P11) >> 11) & 0x1) ++/* Port 4 Pin # Latched Input Value (10) */ ++#define PORT_P4_IN_P10 (0x1 << 10) ++#define PORT_P4_IN_P10_GET(val) ((((val) & PORT_P4_IN_P10) >> 10) & 0x1) ++/* Port 4 Pin # Latched Input Value (9) */ ++#define PORT_P4_IN_P9 (0x1 << 9) ++#define PORT_P4_IN_P9_GET(val) ((((val) & PORT_P4_IN_P9) >> 9) & 0x1) ++/* Port 4 Pin # Latched Input Value (8) */ ++#define PORT_P4_IN_P8 (0x1 << 8) ++#define PORT_P4_IN_P8_GET(val) ((((val) & PORT_P4_IN_P8) >> 8) & 0x1) ++/* Port 4 Pin # Latched Input Value (7) */ ++#define PORT_P4_IN_P7 (0x1 << 7) ++#define PORT_P4_IN_P7_GET(val) ((((val) & PORT_P4_IN_P7) >> 7) & 0x1) ++/* Port 4 Pin # Latched Input Value (6) */ ++#define PORT_P4_IN_P6 (0x1 << 6) ++#define PORT_P4_IN_P6_GET(val) ((((val) & PORT_P4_IN_P6) >> 6) & 0x1) ++/* Port 4 Pin # Latched Input Value (5) */ ++#define PORT_P4_IN_P5 (0x1 << 5) ++#define PORT_P4_IN_P5_GET(val) ((((val) & PORT_P4_IN_P5) >> 5) & 0x1) ++/* Port 4 Pin # Latched Input Value (4) */ ++#define PORT_P4_IN_P4 (0x1 << 4) ++#define PORT_P4_IN_P4_GET(val) ((((val) & PORT_P4_IN_P4) >> 4) & 0x1) ++/* Port 4 Pin # Latched Input Value (3) */ ++#define PORT_P4_IN_P3 (0x1 << 3) ++#define PORT_P4_IN_P3_GET(val) ((((val) & PORT_P4_IN_P3) >> 3) & 0x1) ++/* Port 4 Pin # Latched Input Value (2) */ ++#define PORT_P4_IN_P2 (0x1 << 2) ++#define PORT_P4_IN_P2_GET(val) ((((val) & PORT_P4_IN_P2) >> 2) & 0x1) ++/* Port 4 Pin # Latched Input Value (1) */ ++#define PORT_P4_IN_P1 (0x1 << 1) ++#define PORT_P4_IN_P1_GET(val) ((((val) & PORT_P4_IN_P1) >> 1) & 0x1) ++/* Port 4 Pin # Latched Input Value (0) */ ++#define PORT_P4_IN_P0 (0x1) ++#define PORT_P4_IN_P0_GET(val) ((((val) & PORT_P4_IN_P0) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * Port 4 Direction Register ++ ******************************************************************************/ ++ ++/* Port 4 Pin #Direction Control (23) */ ++#define PORT_P4_DIR_P23 (0x1 << 23) ++#define PORT_P4_DIR_P23_VAL(val) (((val) & 0x1) << 23) ++#define PORT_P4_DIR_P23_GET(val) ((((val) & PORT_P4_DIR_P23) >> 23) & 0x1) ++#define PORT_P4_DIR_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P23) | (((val) & 0x1) << 23)) ++/* Port 4 Pin #Direction Control (22) */ ++#define PORT_P4_DIR_P22 (0x1 << 22) ++#define PORT_P4_DIR_P22_VAL(val) (((val) & 0x1) << 22) ++#define PORT_P4_DIR_P22_GET(val) ((((val) & PORT_P4_DIR_P22) >> 22) & 0x1) ++#define PORT_P4_DIR_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P22) | (((val) & 0x1) << 22)) ++/* Port 4 Pin #Direction Control (21) */ ++#define PORT_P4_DIR_P21 (0x1 << 21) ++#define PORT_P4_DIR_P21_VAL(val) (((val) & 0x1) << 21) ++#define PORT_P4_DIR_P21_GET(val) ((((val) & PORT_P4_DIR_P21) >> 21) & 0x1) ++#define PORT_P4_DIR_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P21) | (((val) & 0x1) << 21)) ++/* Port 4 Pin #Direction Control (20) */ ++#define PORT_P4_DIR_P20 (0x1 << 20) ++#define PORT_P4_DIR_P20_VAL(val) (((val) & 0x1) << 20) ++#define PORT_P4_DIR_P20_GET(val) ((((val) & PORT_P4_DIR_P20) >> 20) & 0x1) ++#define PORT_P4_DIR_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P20) | (((val) & 0x1) << 20)) ++/* Port 4 Pin #Direction Control (19) */ ++#define PORT_P4_DIR_P19 (0x1 << 19) ++#define PORT_P4_DIR_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P4_DIR_P19_GET(val) ((((val) & PORT_P4_DIR_P19) >> 19) & 0x1) ++#define PORT_P4_DIR_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P19) | (((val) & 0x1) << 19)) ++/* Port 4 Pin #Direction Control (18) */ ++#define PORT_P4_DIR_P18 (0x1 << 18) ++#define PORT_P4_DIR_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P4_DIR_P18_GET(val) ((((val) & PORT_P4_DIR_P18) >> 18) & 0x1) ++#define PORT_P4_DIR_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P18) | (((val) & 0x1) << 18)) ++/* Port 4 Pin #Direction Control (17) */ ++#define PORT_P4_DIR_P17 (0x1 << 17) ++#define PORT_P4_DIR_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P4_DIR_P17_GET(val) ((((val) & PORT_P4_DIR_P17) >> 17) & 0x1) ++#define PORT_P4_DIR_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P17) | (((val) & 0x1) << 17)) ++/* Port 4 Pin #Direction Control (16) */ ++#define PORT_P4_DIR_P16 (0x1 << 16) ++#define PORT_P4_DIR_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P4_DIR_P16_GET(val) ((((val) & PORT_P4_DIR_P16) >> 16) & 0x1) ++#define PORT_P4_DIR_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P16) | (((val) & 0x1) << 16)) ++/* Port 4 Pin #Direction Control (15) */ ++#define PORT_P4_DIR_P15 (0x1 << 15) ++#define PORT_P4_DIR_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P4_DIR_P15_GET(val) ((((val) & PORT_P4_DIR_P15) >> 15) & 0x1) ++#define PORT_P4_DIR_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P15) | (((val) & 0x1) << 15)) ++/* Port 4 Pin #Direction Control (14) */ ++#define PORT_P4_DIR_P14 (0x1 << 14) ++#define PORT_P4_DIR_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P4_DIR_P14_GET(val) ((((val) & PORT_P4_DIR_P14) >> 14) & 0x1) ++#define PORT_P4_DIR_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P14) | (((val) & 0x1) << 14)) ++/* Port 4 Pin #Direction Control (13) */ ++#define PORT_P4_DIR_P13 (0x1 << 13) ++#define PORT_P4_DIR_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P4_DIR_P13_GET(val) ((((val) & PORT_P4_DIR_P13) >> 13) & 0x1) ++#define PORT_P4_DIR_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P13) | (((val) & 0x1) << 13)) ++/* Port 4 Pin #Direction Control (12) */ ++#define PORT_P4_DIR_P12 (0x1 << 12) ++#define PORT_P4_DIR_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P4_DIR_P12_GET(val) ((((val) & PORT_P4_DIR_P12) >> 12) & 0x1) ++#define PORT_P4_DIR_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P12) | (((val) & 0x1) << 12)) ++/* Port 4 Pin #Direction Control (11) */ ++#define PORT_P4_DIR_P11 (0x1 << 11) ++#define PORT_P4_DIR_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P4_DIR_P11_GET(val) ((((val) & PORT_P4_DIR_P11) >> 11) & 0x1) ++#define PORT_P4_DIR_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P11) | (((val) & 0x1) << 11)) ++/* Port 4 Pin #Direction Control (10) */ ++#define PORT_P4_DIR_P10 (0x1 << 10) ++#define PORT_P4_DIR_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P4_DIR_P10_GET(val) ((((val) & PORT_P4_DIR_P10) >> 10) & 0x1) ++#define PORT_P4_DIR_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P10) | (((val) & 0x1) << 10)) ++/* Port 4 Pin #Direction Control (9) */ ++#define PORT_P4_DIR_P9 (0x1 << 9) ++#define PORT_P4_DIR_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P4_DIR_P9_GET(val) ((((val) & PORT_P4_DIR_P9) >> 9) & 0x1) ++#define PORT_P4_DIR_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P9) | (((val) & 0x1) << 9)) ++/* Port 4 Pin #Direction Control (8) */ ++#define PORT_P4_DIR_P8 (0x1 << 8) ++#define PORT_P4_DIR_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P4_DIR_P8_GET(val) ((((val) & PORT_P4_DIR_P8) >> 8) & 0x1) ++#define PORT_P4_DIR_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P8) | (((val) & 0x1) << 8)) ++/* Port 4 Pin #Direction Control (7) */ ++#define PORT_P4_DIR_P7 (0x1 << 7) ++#define PORT_P4_DIR_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P4_DIR_P7_GET(val) ((((val) & PORT_P4_DIR_P7) >> 7) & 0x1) ++#define PORT_P4_DIR_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P7) | (((val) & 0x1) << 7)) ++/* Port 4 Pin #Direction Control (6) */ ++#define PORT_P4_DIR_P6 (0x1 << 6) ++#define PORT_P4_DIR_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P4_DIR_P6_GET(val) ((((val) & PORT_P4_DIR_P6) >> 6) & 0x1) ++#define PORT_P4_DIR_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P6) | (((val) & 0x1) << 6)) ++/* Port 4 Pin #Direction Control (5) */ ++#define PORT_P4_DIR_P5 (0x1 << 5) ++#define PORT_P4_DIR_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P4_DIR_P5_GET(val) ((((val) & PORT_P4_DIR_P5) >> 5) & 0x1) ++#define PORT_P4_DIR_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P5) | (((val) & 0x1) << 5)) ++/* Port 4 Pin #Direction Control (4) */ ++#define PORT_P4_DIR_P4 (0x1 << 4) ++#define PORT_P4_DIR_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P4_DIR_P4_GET(val) ((((val) & PORT_P4_DIR_P4) >> 4) & 0x1) ++#define PORT_P4_DIR_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P4) | (((val) & 0x1) << 4)) ++/* Port 4 Pin #Direction Control (3) */ ++#define PORT_P4_DIR_P3 (0x1 << 3) ++#define PORT_P4_DIR_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P4_DIR_P3_GET(val) ((((val) & PORT_P4_DIR_P3) >> 3) & 0x1) ++#define PORT_P4_DIR_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P3) | (((val) & 0x1) << 3)) ++/* Port 4 Pin #Direction Control (2) */ ++#define PORT_P4_DIR_P2 (0x1 << 2) ++#define PORT_P4_DIR_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P4_DIR_P2_GET(val) ((((val) & PORT_P4_DIR_P2) >> 2) & 0x1) ++#define PORT_P4_DIR_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P2) | (((val) & 0x1) << 2)) ++/* Port 4 Pin #Direction Control (1) */ ++#define PORT_P4_DIR_P1 (0x1 << 1) ++#define PORT_P4_DIR_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P4_DIR_P1_GET(val) ((((val) & PORT_P4_DIR_P1) >> 1) & 0x1) ++#define PORT_P4_DIR_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P1) | (((val) & 0x1) << 1)) ++/* Port 4 Pin #Direction Control (0) */ ++#define PORT_P4_DIR_P0 (0x1) ++#define PORT_P4_DIR_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P4_DIR_P0_GET(val) ((((val) & PORT_P4_DIR_P0) >> 0) & 0x1) ++#define PORT_P4_DIR_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_DIR_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 4 Alternate Function Select Register 0 ++ ******************************************************************************/ ++ ++/* Alternate Function at Port 4 Bit # (23) */ ++#define PORT_P4_ALTSEL0_P23 (0x1 << 23) ++#define PORT_P4_ALTSEL0_P23_VAL(val) (((val) & 0x1) << 23) ++#define PORT_P4_ALTSEL0_P23_GET(val) ((((val) & PORT_P4_ALTSEL0_P23) >> 23) & 0x1) ++#define PORT_P4_ALTSEL0_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P23) | (((val) & 0x1) << 23)) ++/* Alternate Function at Port 4 Bit # (22) */ ++#define PORT_P4_ALTSEL0_P22 (0x1 << 22) ++#define PORT_P4_ALTSEL0_P22_VAL(val) (((val) & 0x1) << 22) ++#define PORT_P4_ALTSEL0_P22_GET(val) ((((val) & PORT_P4_ALTSEL0_P22) >> 22) & 0x1) ++#define PORT_P4_ALTSEL0_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P22) | (((val) & 0x1) << 22)) ++/* Alternate Function at Port 4 Bit # (21) */ ++#define PORT_P4_ALTSEL0_P21 (0x1 << 21) ++#define PORT_P4_ALTSEL0_P21_VAL(val) (((val) & 0x1) << 21) ++#define PORT_P4_ALTSEL0_P21_GET(val) ((((val) & PORT_P4_ALTSEL0_P21) >> 21) & 0x1) ++#define PORT_P4_ALTSEL0_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P21) | (((val) & 0x1) << 21)) ++/* Alternate Function at Port 4 Bit # (20) */ ++#define PORT_P4_ALTSEL0_P20 (0x1 << 20) ++#define PORT_P4_ALTSEL0_P20_VAL(val) (((val) & 0x1) << 20) ++#define PORT_P4_ALTSEL0_P20_GET(val) ((((val) & PORT_P4_ALTSEL0_P20) >> 20) & 0x1) ++#define PORT_P4_ALTSEL0_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P20) | (((val) & 0x1) << 20)) ++/* Alternate Function at Port 4 Bit # (19) */ ++#define PORT_P4_ALTSEL0_P19 (0x1 << 19) ++#define PORT_P4_ALTSEL0_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P4_ALTSEL0_P19_GET(val) ((((val) & PORT_P4_ALTSEL0_P19) >> 19) & 0x1) ++#define PORT_P4_ALTSEL0_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P19) | (((val) & 0x1) << 19)) ++/* Alternate Function at Port 4 Bit # (18) */ ++#define PORT_P4_ALTSEL0_P18 (0x1 << 18) ++#define PORT_P4_ALTSEL0_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P4_ALTSEL0_P18_GET(val) ((((val) & PORT_P4_ALTSEL0_P18) >> 18) & 0x1) ++#define PORT_P4_ALTSEL0_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P18) | (((val) & 0x1) << 18)) ++/* Alternate Function at Port 4 Bit # (17) */ ++#define PORT_P4_ALTSEL0_P17 (0x1 << 17) ++#define PORT_P4_ALTSEL0_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P4_ALTSEL0_P17_GET(val) ((((val) & PORT_P4_ALTSEL0_P17) >> 17) & 0x1) ++#define PORT_P4_ALTSEL0_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P17) | (((val) & 0x1) << 17)) ++/* Alternate Function at Port 4 Bit # (16) */ ++#define PORT_P4_ALTSEL0_P16 (0x1 << 16) ++#define PORT_P4_ALTSEL0_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P4_ALTSEL0_P16_GET(val) ((((val) & PORT_P4_ALTSEL0_P16) >> 16) & 0x1) ++#define PORT_P4_ALTSEL0_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P16) | (((val) & 0x1) << 16)) ++/* Alternate Function at Port 4 Bit # (15) */ ++#define PORT_P4_ALTSEL0_P15 (0x1 << 15) ++#define PORT_P4_ALTSEL0_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P4_ALTSEL0_P15_GET(val) ((((val) & PORT_P4_ALTSEL0_P15) >> 15) & 0x1) ++#define PORT_P4_ALTSEL0_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P15) | (((val) & 0x1) << 15)) ++/* Alternate Function at Port 4 Bit # (14) */ ++#define PORT_P4_ALTSEL0_P14 (0x1 << 14) ++#define PORT_P4_ALTSEL0_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P4_ALTSEL0_P14_GET(val) ((((val) & PORT_P4_ALTSEL0_P14) >> 14) & 0x1) ++#define PORT_P4_ALTSEL0_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P14) | (((val) & 0x1) << 14)) ++/* Alternate Function at Port 4 Bit # (13) */ ++#define PORT_P4_ALTSEL0_P13 (0x1 << 13) ++#define PORT_P4_ALTSEL0_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P4_ALTSEL0_P13_GET(val) ((((val) & PORT_P4_ALTSEL0_P13) >> 13) & 0x1) ++#define PORT_P4_ALTSEL0_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P13) | (((val) & 0x1) << 13)) ++/* Alternate Function at Port 4 Bit # (12) */ ++#define PORT_P4_ALTSEL0_P12 (0x1 << 12) ++#define PORT_P4_ALTSEL0_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P4_ALTSEL0_P12_GET(val) ((((val) & PORT_P4_ALTSEL0_P12) >> 12) & 0x1) ++#define PORT_P4_ALTSEL0_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P12) | (((val) & 0x1) << 12)) ++/* Alternate Function at Port 4 Bit # (11) */ ++#define PORT_P4_ALTSEL0_P11 (0x1 << 11) ++#define PORT_P4_ALTSEL0_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P4_ALTSEL0_P11_GET(val) ((((val) & PORT_P4_ALTSEL0_P11) >> 11) & 0x1) ++#define PORT_P4_ALTSEL0_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P11) | (((val) & 0x1) << 11)) ++/* Alternate Function at Port 4 Bit # (10) */ ++#define PORT_P4_ALTSEL0_P10 (0x1 << 10) ++#define PORT_P4_ALTSEL0_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P4_ALTSEL0_P10_GET(val) ((((val) & PORT_P4_ALTSEL0_P10) >> 10) & 0x1) ++#define PORT_P4_ALTSEL0_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P10) | (((val) & 0x1) << 10)) ++/* Alternate Function at Port 4 Bit # (9) */ ++#define PORT_P4_ALTSEL0_P9 (0x1 << 9) ++#define PORT_P4_ALTSEL0_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P4_ALTSEL0_P9_GET(val) ((((val) & PORT_P4_ALTSEL0_P9) >> 9) & 0x1) ++#define PORT_P4_ALTSEL0_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P9) | (((val) & 0x1) << 9)) ++/* Alternate Function at Port 4 Bit # (8) */ ++#define PORT_P4_ALTSEL0_P8 (0x1 << 8) ++#define PORT_P4_ALTSEL0_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P4_ALTSEL0_P8_GET(val) ((((val) & PORT_P4_ALTSEL0_P8) >> 8) & 0x1) ++#define PORT_P4_ALTSEL0_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P8) | (((val) & 0x1) << 8)) ++/* Alternate Function at Port 4 Bit # (7) */ ++#define PORT_P4_ALTSEL0_P7 (0x1 << 7) ++#define PORT_P4_ALTSEL0_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P4_ALTSEL0_P7_GET(val) ((((val) & PORT_P4_ALTSEL0_P7) >> 7) & 0x1) ++#define PORT_P4_ALTSEL0_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P7) | (((val) & 0x1) << 7)) ++/* Alternate Function at Port 4 Bit # (6) */ ++#define PORT_P4_ALTSEL0_P6 (0x1 << 6) ++#define PORT_P4_ALTSEL0_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P4_ALTSEL0_P6_GET(val) ((((val) & PORT_P4_ALTSEL0_P6) >> 6) & 0x1) ++#define PORT_P4_ALTSEL0_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P6) | (((val) & 0x1) << 6)) ++/* Alternate Function at Port 4 Bit # (5) */ ++#define PORT_P4_ALTSEL0_P5 (0x1 << 5) ++#define PORT_P4_ALTSEL0_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P4_ALTSEL0_P5_GET(val) ((((val) & PORT_P4_ALTSEL0_P5) >> 5) & 0x1) ++#define PORT_P4_ALTSEL0_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P5) | (((val) & 0x1) << 5)) ++/* Alternate Function at Port 4 Bit # (4) */ ++#define PORT_P4_ALTSEL0_P4 (0x1 << 4) ++#define PORT_P4_ALTSEL0_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P4_ALTSEL0_P4_GET(val) ((((val) & PORT_P4_ALTSEL0_P4) >> 4) & 0x1) ++#define PORT_P4_ALTSEL0_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P4) | (((val) & 0x1) << 4)) ++/* Alternate Function at Port 4 Bit # (3) */ ++#define PORT_P4_ALTSEL0_P3 (0x1 << 3) ++#define PORT_P4_ALTSEL0_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P4_ALTSEL0_P3_GET(val) ((((val) & PORT_P4_ALTSEL0_P3) >> 3) & 0x1) ++#define PORT_P4_ALTSEL0_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P3) | (((val) & 0x1) << 3)) ++/* Alternate Function at Port 4 Bit # (2) */ ++#define PORT_P4_ALTSEL0_P2 (0x1 << 2) ++#define PORT_P4_ALTSEL0_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P4_ALTSEL0_P2_GET(val) ((((val) & PORT_P4_ALTSEL0_P2) >> 2) & 0x1) ++#define PORT_P4_ALTSEL0_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P2) | (((val) & 0x1) << 2)) ++/* Alternate Function at Port 4 Bit # (1) */ ++#define PORT_P4_ALTSEL0_P1 (0x1 << 1) ++#define PORT_P4_ALTSEL0_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P4_ALTSEL0_P1_GET(val) ((((val) & PORT_P4_ALTSEL0_P1) >> 1) & 0x1) ++#define PORT_P4_ALTSEL0_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P1) | (((val) & 0x1) << 1)) ++/* Alternate Function at Port 4 Bit # (0) */ ++#define PORT_P4_ALTSEL0_P0 (0x1) ++#define PORT_P4_ALTSEL0_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P4_ALTSEL0_P0_GET(val) ((((val) & PORT_P4_ALTSEL0_P0) >> 0) & 0x1) ++#define PORT_P4_ALTSEL0_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_ALTSEL0_P0) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * Port 4 Pull Up Device Enable Register ++ ******************************************************************************/ ++ ++/* Pull Up Device Enable at Port 4 Bit # (23) */ ++#define PORT_P4_PUEN_P23 (0x1 << 23) ++#define PORT_P4_PUEN_P23_VAL(val) (((val) & 0x1) << 23) ++#define PORT_P4_PUEN_P23_GET(val) ((((val) & PORT_P4_PUEN_P23) >> 23) & 0x1) ++#define PORT_P4_PUEN_P23_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P23) | (((val) & 0x1) << 23)) ++/* Pull Up Device Enable at Port 4 Bit # (22) */ ++#define PORT_P4_PUEN_P22 (0x1 << 22) ++#define PORT_P4_PUEN_P22_VAL(val) (((val) & 0x1) << 22) ++#define PORT_P4_PUEN_P22_GET(val) ((((val) & PORT_P4_PUEN_P22) >> 22) & 0x1) ++#define PORT_P4_PUEN_P22_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P22) | (((val) & 0x1) << 22)) ++/* Pull Up Device Enable at Port 4 Bit # (21) */ ++#define PORT_P4_PUEN_P21 (0x1 << 21) ++#define PORT_P4_PUEN_P21_VAL(val) (((val) & 0x1) << 21) ++#define PORT_P4_PUEN_P21_GET(val) ((((val) & PORT_P4_PUEN_P21) >> 21) & 0x1) ++#define PORT_P4_PUEN_P21_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P21) | (((val) & 0x1) << 21)) ++/* Pull Up Device Enable at Port 4 Bit # (20) */ ++#define PORT_P4_PUEN_P20 (0x1 << 20) ++#define PORT_P4_PUEN_P20_VAL(val) (((val) & 0x1) << 20) ++#define PORT_P4_PUEN_P20_GET(val) ((((val) & PORT_P4_PUEN_P20) >> 20) & 0x1) ++#define PORT_P4_PUEN_P20_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P20) | (((val) & 0x1) << 20)) ++/* Pull Up Device Enable at Port 4 Bit # (19) */ ++#define PORT_P4_PUEN_P19 (0x1 << 19) ++#define PORT_P4_PUEN_P19_VAL(val) (((val) & 0x1) << 19) ++#define PORT_P4_PUEN_P19_GET(val) ((((val) & PORT_P4_PUEN_P19) >> 19) & 0x1) ++#define PORT_P4_PUEN_P19_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P19) | (((val) & 0x1) << 19)) ++/* Pull Up Device Enable at Port 4 Bit # (18) */ ++#define PORT_P4_PUEN_P18 (0x1 << 18) ++#define PORT_P4_PUEN_P18_VAL(val) (((val) & 0x1) << 18) ++#define PORT_P4_PUEN_P18_GET(val) ((((val) & PORT_P4_PUEN_P18) >> 18) & 0x1) ++#define PORT_P4_PUEN_P18_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P18) | (((val) & 0x1) << 18)) ++/* Pull Up Device Enable at Port 4 Bit # (17) */ ++#define PORT_P4_PUEN_P17 (0x1 << 17) ++#define PORT_P4_PUEN_P17_VAL(val) (((val) & 0x1) << 17) ++#define PORT_P4_PUEN_P17_GET(val) ((((val) & PORT_P4_PUEN_P17) >> 17) & 0x1) ++#define PORT_P4_PUEN_P17_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P17) | (((val) & 0x1) << 17)) ++/* Pull Up Device Enable at Port 4 Bit # (16) */ ++#define PORT_P4_PUEN_P16 (0x1 << 16) ++#define PORT_P4_PUEN_P16_VAL(val) (((val) & 0x1) << 16) ++#define PORT_P4_PUEN_P16_GET(val) ((((val) & PORT_P4_PUEN_P16) >> 16) & 0x1) ++#define PORT_P4_PUEN_P16_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P16) | (((val) & 0x1) << 16)) ++/* Pull Up Device Enable at Port 4 Bit # (15) */ ++#define PORT_P4_PUEN_P15 (0x1 << 15) ++#define PORT_P4_PUEN_P15_VAL(val) (((val) & 0x1) << 15) ++#define PORT_P4_PUEN_P15_GET(val) ((((val) & PORT_P4_PUEN_P15) >> 15) & 0x1) ++#define PORT_P4_PUEN_P15_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P15) | (((val) & 0x1) << 15)) ++/* Pull Up Device Enable at Port 4 Bit # (14) */ ++#define PORT_P4_PUEN_P14 (0x1 << 14) ++#define PORT_P4_PUEN_P14_VAL(val) (((val) & 0x1) << 14) ++#define PORT_P4_PUEN_P14_GET(val) ((((val) & PORT_P4_PUEN_P14) >> 14) & 0x1) ++#define PORT_P4_PUEN_P14_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P14) | (((val) & 0x1) << 14)) ++/* Pull Up Device Enable at Port 4 Bit # (13) */ ++#define PORT_P4_PUEN_P13 (0x1 << 13) ++#define PORT_P4_PUEN_P13_VAL(val) (((val) & 0x1) << 13) ++#define PORT_P4_PUEN_P13_GET(val) ((((val) & PORT_P4_PUEN_P13) >> 13) & 0x1) ++#define PORT_P4_PUEN_P13_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P13) | (((val) & 0x1) << 13)) ++/* Pull Up Device Enable at Port 4 Bit # (12) */ ++#define PORT_P4_PUEN_P12 (0x1 << 12) ++#define PORT_P4_PUEN_P12_VAL(val) (((val) & 0x1) << 12) ++#define PORT_P4_PUEN_P12_GET(val) ((((val) & PORT_P4_PUEN_P12) >> 12) & 0x1) ++#define PORT_P4_PUEN_P12_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P12) | (((val) & 0x1) << 12)) ++/* Pull Up Device Enable at Port 4 Bit # (11) */ ++#define PORT_P4_PUEN_P11 (0x1 << 11) ++#define PORT_P4_PUEN_P11_VAL(val) (((val) & 0x1) << 11) ++#define PORT_P4_PUEN_P11_GET(val) ((((val) & PORT_P4_PUEN_P11) >> 11) & 0x1) ++#define PORT_P4_PUEN_P11_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P11) | (((val) & 0x1) << 11)) ++/* Pull Up Device Enable at Port 4 Bit # (10) */ ++#define PORT_P4_PUEN_P10 (0x1 << 10) ++#define PORT_P4_PUEN_P10_VAL(val) (((val) & 0x1) << 10) ++#define PORT_P4_PUEN_P10_GET(val) ((((val) & PORT_P4_PUEN_P10) >> 10) & 0x1) ++#define PORT_P4_PUEN_P10_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P10) | (((val) & 0x1) << 10)) ++/* Pull Up Device Enable at Port 4 Bit # (9) */ ++#define PORT_P4_PUEN_P9 (0x1 << 9) ++#define PORT_P4_PUEN_P9_VAL(val) (((val) & 0x1) << 9) ++#define PORT_P4_PUEN_P9_GET(val) ((((val) & PORT_P4_PUEN_P9) >> 9) & 0x1) ++#define PORT_P4_PUEN_P9_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P9) | (((val) & 0x1) << 9)) ++/* Pull Up Device Enable at Port 4 Bit # (8) */ ++#define PORT_P4_PUEN_P8 (0x1 << 8) ++#define PORT_P4_PUEN_P8_VAL(val) (((val) & 0x1) << 8) ++#define PORT_P4_PUEN_P8_GET(val) ((((val) & PORT_P4_PUEN_P8) >> 8) & 0x1) ++#define PORT_P4_PUEN_P8_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P8) | (((val) & 0x1) << 8)) ++/* Pull Up Device Enable at Port 4 Bit # (7) */ ++#define PORT_P4_PUEN_P7 (0x1 << 7) ++#define PORT_P4_PUEN_P7_VAL(val) (((val) & 0x1) << 7) ++#define PORT_P4_PUEN_P7_GET(val) ((((val) & PORT_P4_PUEN_P7) >> 7) & 0x1) ++#define PORT_P4_PUEN_P7_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P7) | (((val) & 0x1) << 7)) ++/* Pull Up Device Enable at Port 4 Bit # (6) */ ++#define PORT_P4_PUEN_P6 (0x1 << 6) ++#define PORT_P4_PUEN_P6_VAL(val) (((val) & 0x1) << 6) ++#define PORT_P4_PUEN_P6_GET(val) ((((val) & PORT_P4_PUEN_P6) >> 6) & 0x1) ++#define PORT_P4_PUEN_P6_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P6) | (((val) & 0x1) << 6)) ++/* Pull Up Device Enable at Port 4 Bit # (5) */ ++#define PORT_P4_PUEN_P5 (0x1 << 5) ++#define PORT_P4_PUEN_P5_VAL(val) (((val) & 0x1) << 5) ++#define PORT_P4_PUEN_P5_GET(val) ((((val) & PORT_P4_PUEN_P5) >> 5) & 0x1) ++#define PORT_P4_PUEN_P5_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P5) | (((val) & 0x1) << 5)) ++/* Pull Up Device Enable at Port 4 Bit # (4) */ ++#define PORT_P4_PUEN_P4 (0x1 << 4) ++#define PORT_P4_PUEN_P4_VAL(val) (((val) & 0x1) << 4) ++#define PORT_P4_PUEN_P4_GET(val) ((((val) & PORT_P4_PUEN_P4) >> 4) & 0x1) ++#define PORT_P4_PUEN_P4_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P4) | (((val) & 0x1) << 4)) ++/* Pull Up Device Enable at Port 4 Bit # (3) */ ++#define PORT_P4_PUEN_P3 (0x1 << 3) ++#define PORT_P4_PUEN_P3_VAL(val) (((val) & 0x1) << 3) ++#define PORT_P4_PUEN_P3_GET(val) ((((val) & PORT_P4_PUEN_P3) >> 3) & 0x1) ++#define PORT_P4_PUEN_P3_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P3) | (((val) & 0x1) << 3)) ++/* Pull Up Device Enable at Port 4 Bit # (2) */ ++#define PORT_P4_PUEN_P2 (0x1 << 2) ++#define PORT_P4_PUEN_P2_VAL(val) (((val) & 0x1) << 2) ++#define PORT_P4_PUEN_P2_GET(val) ((((val) & PORT_P4_PUEN_P2) >> 2) & 0x1) ++#define PORT_P4_PUEN_P2_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P2) | (((val) & 0x1) << 2)) ++/* Pull Up Device Enable at Port 4 Bit # (1) */ ++#define PORT_P4_PUEN_P1 (0x1 << 1) ++#define PORT_P4_PUEN_P1_VAL(val) (((val) & 0x1) << 1) ++#define PORT_P4_PUEN_P1_GET(val) ((((val) & PORT_P4_PUEN_P1) >> 1) & 0x1) ++#define PORT_P4_PUEN_P1_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P1) | (((val) & 0x1) << 1)) ++/* Pull Up Device Enable at Port 4 Bit # (0) */ ++#define PORT_P4_PUEN_P0 (0x1) ++#define PORT_P4_PUEN_P0_VAL(val) (((val) & 0x1) << 0) ++#define PORT_P4_PUEN_P0_GET(val) ((((val) & PORT_P4_PUEN_P0) >> 0) & 0x1) ++#define PORT_P4_PUEN_P0_SET(reg,val) (reg) = ((reg & ~PORT_P4_PUEN_P0) | (((val) & 0x1) << 0)) ++ ++#endif /* __PORT_H */ +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/ssc_reg.h 2012-07-31 15:46:02.484476159 +0200 +@@ -0,0 +1,624 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __SSC_REG_H ++#define __SSC_REG_H ++ ++/** SSC register structure */ ++struct svip_reg_ssc { ++ volatile unsigned long clc; /* 0x00 */ ++ volatile unsigned long pisel; /* 0x04 */ ++ volatile unsigned long id; /* 0x08 */ ++ volatile unsigned long reserved0; /* 0x0c */ ++ volatile unsigned long mcon; /* 0x10 */ ++ volatile unsigned long state; /* 0x14 */ ++ volatile unsigned long whbstate; /* 0x18 */ ++ volatile unsigned long reserved1; /* 0x1c */ ++ volatile unsigned long tb; /* 0x20 */ ++ volatile unsigned long rb; /* 0x24 */ ++ volatile unsigned long reserved2[2]; /* 0x28 */ ++ volatile unsigned long rxfcon; /* 0x30 */ ++ volatile unsigned long txfcon; /* 0x34 */ ++ volatile unsigned long fstat; /* 0x38 */ ++ volatile unsigned long reserved3; /* 0x3c */ ++ volatile unsigned long br; /* 0x40 */ ++ volatile unsigned long brstat; /* 0x44 */ ++ volatile unsigned long reserved4[6]; /* 0x48 */ ++ volatile unsigned long sfcon; /* 0x60 */ ++ volatile unsigned long sfstat; /* 0x64 */ ++ volatile unsigned long reserved5[2]; /* 0x68 */ ++ volatile unsigned long gpocon; /* 0x70 */ ++ volatile unsigned long gpostat; /* 0x74 */ ++ volatile unsigned long whbgpostat; /* 0x78 */ ++ volatile unsigned long reserved6; /* 0x7c */ ++ volatile unsigned long rxreq; /* 0x80 */ ++ volatile unsigned long rxcnt; /* 0x84 */ ++ volatile unsigned long reserved7[25]; /* 0x88 */ ++ volatile unsigned long dma_con; /* 0xEC */ ++ volatile unsigned long reserved8; /* 0xf0 */ ++ volatile unsigned long irnen; /* 0xF4 */ ++ volatile unsigned long irncr; /* 0xF8 */ ++ volatile unsigned long irnicr; /* 0xFC */ ++}; ++ ++/******************************************************************************* ++ * CLC Register ++ ******************************************************************************/ ++ ++/* Clock Divider for Sleep Mode (23:16) */ ++#define SSC_CLC_SMC (0xff << 16) ++#define SSC_CLC_SMC_VAL(val) (((val) & 0xff) << 16) ++#define SSC_CLC_SMC_GET(val) ((((val) & SSC_CLC_SMC) >> 16) & 0xff) ++#define SSC_CLC_SMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SMC) | (((val) & 0xff) << 16)) ++/* Clock Divider for Normal Run Mode (15:8) */ ++#define SSC_CLC_RMC (0xff << 8) ++#define SSC_CLC_RMC_VAL(val) (((val) & 0xff) << 8) ++#define SSC_CLC_RMC_GET(val) ((((val) & SSC_CLC_RMC) >> 8) & 0xff) ++#define SSC_CLC_RMC_SET(reg,val) (reg) = ((reg & ~SSC_CLC_RMC) | (((val) & 0xff) << 8)) ++/* Fast Shut-Off Enable Bit (5) */ ++#define SSC_CLC_FSOE (0x1 << 5) ++#define SSC_CLC_FSOE_VAL(val) (((val) & 0x1) << 5) ++#define SSC_CLC_FSOE_GET(val) ((((val) & SSC_CLC_FSOE) >> 5) & 0x1) ++#define SSC_CLC_FSOE_SET(reg,val) (reg) = ((reg & ~SSC_CLC_FSOE) | (((val) & 0x1) << 5)) ++/* Suspend Bit Write Enable for OCDS (4) */ ++#define SSC_CLC_SBWE (0x1 << 4) ++#define SSC_CLC_SBWE_VAL(val) (((val) & 0x1) << 4) ++#define SSC_CLC_SBWE_SET(reg,val) (reg) = (((reg & ~SSC_CLC_SBWE) | (val) & 1) << 4) ++/* External Request Disable (3) */ ++#define SSC_CLC_EDIS (0x1 << 3) ++#define SSC_CLC_EDIS_VAL(val) (((val) & 0x1) << 3) ++#define SSC_CLC_EDIS_GET(val) ((((val) & SSC_CLC_EDIS) >> 3) & 0x1) ++#define SSC_CLC_EDIS_SET(reg,val) (reg) = ((reg & ~SSC_CLC_EDIS) | (((val) & 0x1) << 3)) ++/* Suspend Enable Bit for OCDS (2) */ ++#define SSC_CLC_SPEN (0x1 << 2) ++#define SSC_CLC_SPEN_VAL(val) (((val) & 0x1) << 2) ++#define SSC_CLC_SPEN_GET(val) ((((val) & SSC_CLC_SPEN) >> 2) & 0x1) ++#define SSC_CLC_SPEN_SET(reg,val) (reg) = ((reg & ~SSC_CLC_SPEN) | (((val) & 0x1) << 2)) ++/* Disable Status Bit (1) */ ++#define SSC_CLC_DISS (0x1 << 1) ++#define SSC_CLC_DISS_GET(val) ((((val) & SSC_CLC_DISS) >> 1) & 0x1) ++/* Disable Request Bit (0) */ ++#define SSC_CLC_DISR (0x1) ++#define SSC_CLC_DISR_VAL(val) (((val) & 0x1) << 0) ++#define SSC_CLC_DISR_GET(val) ((((val) & SSC_CLC_DISR) >> 0) & 0x1) ++#define SSC_CLC_DISR_SET(reg,val) (reg) = ((reg & ~SSC_CLC_DISR) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * ID Register ++ ******************************************************************************/ ++ ++/* Transmit FIFO Size (29:24) */ ++#define SSC_ID_TXFS (0x3f << 24) ++#define SSC_ID_TXFS_GET(val) ((((val) & SSC_ID_TXFS) >> 24) & 0x3f) ++/* Receive FIFO Size (21:16) */ ++#define SSC_ID_RXFS (0x3f << 16) ++#define SSC_ID_RXFS_GET(val) ((((val) & SSC_ID_RXFS) >> 16) & 0x3f) ++/* Module ID (15:8) */ ++#define SSC_ID_ID (0xff << 8) ++#define SSC_ID_ID_GET(val) ((((val) & SSC_ID_ID) >> 8) & 0xff) ++/* Configuration (5) */ ++#define SSC_ID_CFG (0x1 << 5) ++#define SSC_ID_CFG_GET(val) ((((val) & SSC_ID_CFG) >> 5) & 0x1) ++/* Revision (4:0) */ ++#define SSC_ID_REV (0x1f) ++#define SSC_ID_REV_GET(val) ((((val) & SSC_ID_REV) >> 0) & 0x1f) ++ ++/******************************************************************************* ++ * MCON Register ++ ******************************************************************************/ ++ ++/* Echo Mode (24) */ ++#define SSC_MCON_EM (0x1 << 24) ++#define SSC_MCON_EM_VAL(val) (((val) & 0x1) << 24) ++#define SSC_MCON_EM_GET(val) ((((val) & SSC_MCON_EM) >> 24) & 0x1) ++#define SSC_MCON_EM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_EM) | (((val) & 0x1) << 24)) ++/* Idle Bit Value (23) */ ++#define SSC_MCON_IDLE (0x1 << 23) ++#define SSC_MCON_IDLE_VAL(val) (((val) & 0x1) << 23) ++#define SSC_MCON_IDLE_GET(val) ((((val) & SSC_MCON_IDLE) >> 23) & 0x1) ++#define SSC_MCON_IDLE_SET(reg,val) (reg) = ((reg & ~SSC_MCON_IDLE) | (((val) & 0x1) << 23)) ++/* Enable Byte Valid Control (22) */ ++#define SSC_MCON_ENBV (0x1 << 22) ++#define SSC_MCON_ENBV_VAL(val) (((val) & 0x1) << 22) ++#define SSC_MCON_ENBV_GET(val) ((((val) & SSC_MCON_ENBV) >> 22) & 0x1) ++#define SSC_MCON_ENBV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_ENBV) | (((val) & 0x1) << 22)) ++/* Data Width Selection (20:16) */ ++#define SSC_MCON_BM (0x1f << 16) ++#define SSC_MCON_BM_VAL(val) (((val) & 0x1f) << 16) ++#define SSC_MCON_BM_GET(val) ((((val) & SSC_MCON_BM) >> 16) & 0x1f) ++#define SSC_MCON_BM_SET(reg,val) (reg) = ((reg & ~SSC_MCON_BM) | (((val) & 0x1f) << 16)) ++/* Receive Underflow Error Enable (12) */ ++#define SSC_MCON_RUEN (0x1 << 12) ++#define SSC_MCON_RUEN_VAL(val) (((val) & 0x1) << 12) ++#define SSC_MCON_RUEN_GET(val) ((((val) & SSC_MCON_RUEN) >> 12) & 0x1) ++#define SSC_MCON_RUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RUEN) | (((val) & 0x1) << 12)) ++/* Transmit Underflow Error Enable (11) */ ++#define SSC_MCON_TUEN (0x1 << 11) ++#define SSC_MCON_TUEN_VAL(val) (((val) & 0x1) << 11) ++#define SSC_MCON_TUEN_GET(val) ((((val) & SSC_MCON_TUEN) >> 11) & 0x1) ++#define SSC_MCON_TUEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TUEN) | (((val) & 0x1) << 11)) ++/* Abort Error Enable (10) */ ++#define SSC_MCON_AEN (0x1 << 10) ++#define SSC_MCON_AEN_VAL(val) (((val) & 0x1) << 10) ++#define SSC_MCON_AEN_GET(val) ((((val) & SSC_MCON_AEN) >> 10) & 0x1) ++#define SSC_MCON_AEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_AEN) | (((val) & 0x1) << 10)) ++/* Receive Overflow Error Enable (9) */ ++#define SSC_MCON_REN (0x1 << 9) ++#define SSC_MCON_REN_VAL(val) (((val) & 0x1) << 9) ++#define SSC_MCON_REN_GET(val) ((((val) & SSC_MCON_REN) >> 9) & 0x1) ++#define SSC_MCON_REN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_REN) | (((val) & 0x1) << 9)) ++/* Transmit Overflow Error Enable (8) */ ++#define SSC_MCON_TEN (0x1 << 8) ++#define SSC_MCON_TEN_VAL(val) (((val) & 0x1) << 8) ++#define SSC_MCON_TEN_GET(val) ((((val) & SSC_MCON_TEN) >> 8) & 0x1) ++#define SSC_MCON_TEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TEN) | (((val) & 0x1) << 8)) ++/* Loop Back Control (7) */ ++#define SSC_MCON_LB (0x1 << 7) ++#define SSC_MCON_LB_VAL(val) (((val) & 0x1) << 7) ++#define SSC_MCON_LB_GET(val) ((((val) & SSC_MCON_LB) >> 7) & 0x1) ++#define SSC_MCON_LB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_LB) | (((val) & 0x1) << 7)) ++/* Clock Polarity Control (6) */ ++#define SSC_MCON_PO (0x1 << 6) ++#define SSC_MCON_PO_VAL(val) (((val) & 0x1) << 6) ++#define SSC_MCON_PO_GET(val) ((((val) & SSC_MCON_PO) >> 6) & 0x1) ++#define SSC_MCON_PO_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PO) | (((val) & 0x1) << 6)) ++/* Clock Phase Control (5) */ ++#define SSC_MCON_PH (0x1 << 5) ++#define SSC_MCON_PH_VAL(val) (((val) & 0x1) << 5) ++#define SSC_MCON_PH_GET(val) ((((val) & SSC_MCON_PH) >> 5) & 0x1) ++#define SSC_MCON_PH_SET(reg,val) (reg) = ((reg & ~SSC_MCON_PH) | (((val) & 0x1) << 5)) ++/* Heading Control (4) */ ++#define SSC_MCON_HB (0x1 << 4) ++#define SSC_MCON_HB_VAL(val) (((val) & 0x1) << 4) ++#define SSC_MCON_HB_GET(val) ((((val) & SSC_MCON_HB) >> 4) & 0x1) ++#define SSC_MCON_HB_SET(reg,val) (reg) = ((reg & ~SSC_MCON_HB) | (((val) & 0x1) << 4)) ++/* Chip Select Enable (3) */ ++#define SSC_MCON_CSBEN (0x1 << 3) ++#define SSC_MCON_CSBEN_VAL(val) (((val) & 0x1) << 3) ++#define SSC_MCON_CSBEN_GET(val) ((((val) & SSC_MCON_CSBEN) >> 3) & 0x1) ++#define SSC_MCON_CSBEN_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBEN) | (((val) & 0x1) << 3)) ++/* Chip Select Invert (2) */ ++#define SSC_MCON_CSBINV (0x1 << 2) ++#define SSC_MCON_CSBINV_VAL(val) (((val) & 0x1) << 2) ++#define SSC_MCON_CSBINV_GET(val) ((((val) & SSC_MCON_CSBINV) >> 2) & 0x1) ++#define SSC_MCON_CSBINV_SET(reg,val) (reg) = ((reg & ~SSC_MCON_CSBINV) | (((val) & 0x1) << 2)) ++/* Receive Off (1) */ ++#define SSC_MCON_RXOFF (0x1 << 1) ++#define SSC_MCON_RXOFF_VAL(val) (((val) & 0x1) << 1) ++#define SSC_MCON_RXOFF_GET(val) ((((val) & SSC_MCON_RXOFF) >> 1) & 0x1) ++#define SSC_MCON_RXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_RXOFF) | (((val) & 0x1) << 1)) ++/* Transmit Off (0) */ ++#define SSC_MCON_TXOFF (0x1) ++#define SSC_MCON_TXOFF_VAL(val) (((val) & 0x1) << 0) ++#define SSC_MCON_TXOFF_GET(val) ((((val) & SSC_MCON_TXOFF) >> 0) & 0x1) ++#define SSC_MCON_TXOFF_SET(reg,val) (reg) = ((reg & ~SSC_MCON_TXOFF) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * STATE Register ++ ******************************************************************************/ ++ ++/* Receive End-of-Message (31) */ ++#define SSC_STATE_RXEOM (0x1 << 31) ++#define SSC_STATE_RXEOM_GET(val) ((((val) & SSC_STATE_RXEOM) >> 31) & 0x1) ++/* Receive Byte Valid (30:28) */ ++#define SSC_STATE_RXBV (0x7 << 28) ++#define SSC_STATE_RXBV_GET(val) ((((val) & SSC_STATE_RXBV) >> 28) & 0x7) ++/* Transmit End-of-Message (27) */ ++#define SSC_STATE_TXEOM (0x1 << 27) ++#define SSC_STATE_TXEOM_GET(val) ((((val) & SSC_STATE_TXEOM) >> 27) & 0x1) ++/* Transmit Byte Valid (26:24) */ ++#define SSC_STATE_TXBV (0x7 << 24) ++#define SSC_STATE_TXBV_GET(val) ((((val) & SSC_STATE_TXBV) >> 24) & 0x7) ++/* Bit Count Field (20:16) */ ++#define SSC_STATE_BC (0x1f << 16) ++#define SSC_STATE_BC_GET(val) ((((val) & SSC_STATE_BC) >> 16) & 0x1f) ++/* Busy Flag (13) */ ++#define SSC_STATE_BSY (0x1 << 13) ++#define SSC_STATE_BSY_GET(val) ((((val) & SSC_STATE_BSY) >> 13) & 0x1) ++/* Receive Underflow Error Flag (12) */ ++#define SSC_STATE_RUE (0x1 << 12) ++#define SSC_STATE_RUE_GET(val) ((((val) & SSC_STATE_RUE) >> 12) & 0x1) ++/* Transmit Underflow Error Flag (11) */ ++#define SSC_STATE_TUE (0x1 << 11) ++#define SSC_STATE_TUE_GET(val) ((((val) & SSC_STATE_TUE) >> 11) & 0x1) ++/* Abort Error Flag (10) */ ++#define SSC_STATE_AE (0x1 << 10) ++#define SSC_STATE_AE_GET(val) ((((val) & SSC_STATE_AE) >> 10) & 0x1) ++/* Receive Error Flag (9) */ ++#define SSC_STATE_RE (0x1 << 9) ++#define SSC_STATE_RE_GET(val) ((((val) & SSC_STATE_RE) >> 9) & 0x1) ++/* Transmit Error Flag (8) */ ++#define SSC_STATE_TE (0x1 << 8) ++#define SSC_STATE_TE_GET(val) ((((val) & SSC_STATE_TE) >> 8) & 0x1) ++/* Mode Error Flag (7) */ ++#define SSC_STATE_ME (0x1 << 7) ++#define SSC_STATE_ME_GET(val) ((((val) & SSC_STATE_ME) >> 7) & 0x1) ++/* Slave Selected (2) */ ++#define SSC_STATE_SSEL (0x1 << 2) ++#define SSC_STATE_SSEL_GET(val) ((((val) & SSC_STATE_SSEL) >> 2) & 0x1) ++/* Master Select Bit (1) */ ++#define SSC_STATE_MS (0x1 << 1) ++#define SSC_STATE_MS_GET(val) ((((val) & SSC_STATE_MS) >> 1) & 0x1) ++/* Enable Bit (0) */ ++#define SSC_STATE_EN (0x1) ++#define SSC_STATE_EN_GET(val) ((((val) & SSC_STATE_EN) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * WHBSTATE Register ++ ******************************************************************************/ ++ ++/* Set Transmit Underflow Error Flag Bit (15) */ ++#define SSC_WHBSTATE_SETTUE (0x1 << 15) ++#define SSC_WHBSTATE_SETTUE_VAL(val) (((val) & 0x1) << 15) ++#define SSC_WHBSTATE_SETTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTUE) | (val) & 1) << 15) ++/* Set Abort Error Flag Bit (14) */ ++#define SSC_WHBSTATE_SETAE (0x1 << 14) ++#define SSC_WHBSTATE_SETAE_VAL(val) (((val) & 0x1) << 14) ++#define SSC_WHBSTATE_SETAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETAE) | (val) & 1) << 14) ++/* Set Receive Error Flag Bit (13) */ ++#define SSC_WHBSTATE_SETRE (0x1 << 13) ++#define SSC_WHBSTATE_SETRE_VAL(val) (((val) & 0x1) << 13) ++#define SSC_WHBSTATE_SETRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRE) | (val) & 1) << 13) ++/* Set Transmit Error Flag Bit (12) */ ++#define SSC_WHBSTATE_SETTE (0x1 << 12) ++#define SSC_WHBSTATE_SETTE_VAL(val) (((val) & 0x1) << 12) ++#define SSC_WHBSTATE_SETTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETTE) | (val) & 1) << 12) ++/* Clear Transmit Underflow Error Flag Bit (11) */ ++#define SSC_WHBSTATE_CLRTUE (0x1 << 11) ++#define SSC_WHBSTATE_CLRTUE_VAL(val) (((val) & 0x1) << 11) ++#define SSC_WHBSTATE_CLRTUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTUE) | (val) & 1) << 11) ++/* Clear Abort Error Flag Bit (10) */ ++#define SSC_WHBSTATE_CLRAE (0x1 << 10) ++#define SSC_WHBSTATE_CLRAE_VAL(val) (((val) & 0x1) << 10) ++#define SSC_WHBSTATE_CLRAE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRAE) | (val) & 1) << 10) ++/* Clear Receive Error Flag Bit (9) */ ++#define SSC_WHBSTATE_CLRRE (0x1 << 9) ++#define SSC_WHBSTATE_CLRRE_VAL(val) (((val) & 0x1) << 9) ++#define SSC_WHBSTATE_CLRRE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRE) | (val) & 1) << 9) ++/* Clear Transmit Error Flag Bit (8) */ ++#define SSC_WHBSTATE_CLRTE (0x1 << 8) ++#define SSC_WHBSTATE_CLRTE_VAL(val) (((val) & 0x1) << 8) ++#define SSC_WHBSTATE_CLRTE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRTE) | (val) & 1) << 8) ++/* Set Mode Error Flag Bit (7) */ ++#define SSC_WHBSTATE_SETME (0x1 << 7) ++#define SSC_WHBSTATE_SETME_VAL(val) (((val) & 0x1) << 7) ++#define SSC_WHBSTATE_SETME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETME) | (val) & 1) << 7) ++/* Clear Mode Error Flag Bit (6) */ ++#define SSC_WHBSTATE_CLRME (0x1 << 6) ++#define SSC_WHBSTATE_CLRME_VAL(val) (((val) & 0x1) << 6) ++#define SSC_WHBSTATE_CLRME_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRME) | (val) & 1) << 6) ++/* Set Receive Underflow Error Bit (5) */ ++#define SSC_WHBSTATE_SETRUE (0x1 << 5) ++#define SSC_WHBSTATE_SETRUE_VAL(val) (((val) & 0x1) << 5) ++#define SSC_WHBSTATE_SETRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETRUE) | (val) & 1) << 5) ++/* Clear Receive Underflow Error Bit (4) */ ++#define SSC_WHBSTATE_CLRRUE (0x1 << 4) ++#define SSC_WHBSTATE_CLRRUE_VAL(val) (((val) & 0x1) << 4) ++#define SSC_WHBSTATE_CLRRUE_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRRUE) | (val) & 1) << 4) ++/* Set Master Select Bit (3) */ ++#define SSC_WHBSTATE_SETMS (0x1 << 3) ++#define SSC_WHBSTATE_SETMS_VAL(val) (((val) & 0x1) << 3) ++#define SSC_WHBSTATE_SETMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETMS) | (val) & 1) << 3) ++/* Clear Master Select Bit (2) */ ++#define SSC_WHBSTATE_CLRMS (0x1 << 2) ++#define SSC_WHBSTATE_CLRMS_VAL(val) (((val) & 0x1) << 2) ++#define SSC_WHBSTATE_CLRMS_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLRMS) | (val) & 1) << 2) ++/* Set Enable Bit (1) */ ++#define SSC_WHBSTATE_SETEN (0x1 << 1) ++#define SSC_WHBSTATE_SETEN_VAL(val) (((val) & 0x1) << 1) ++#define SSC_WHBSTATE_SETEN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_SETEN) | (val) & 1) << 1) ++/* Clear Enable Bit (0) */ ++#define SSC_WHBSTATE_CLREN (0x1) ++#define SSC_WHBSTATE_CLREN_VAL(val) (((val) & 0x1) << 0) ++#define SSC_WHBSTATE_CLREN_SET(reg,val) (reg) = (((reg & ~SSC_WHBSTATE_CLREN) | (val) & 1) << 0) ++ ++/******************************************************************************* ++ * TB Register ++ ******************************************************************************/ ++ ++/* Transmit Data Register Value (31:0) */ ++#define SSC_TB_TB_VAL (0xFFFFFFFFL) ++#define SSC_TB_TB_VAL_VAL(val) (((val) & 0xFFFFFFFFL) << 0) ++#define SSC_TB_TB_VAL_GET(val) ((((val) & SSC_TB_TB_VAL) >> 0) & 0xFFFFFFFFL) ++#define SSC_TB_TB_VAL_SET(reg,val) (reg) = ((reg & ~SSC_TB_TB_VAL) | (((val) & 0xFFFFFFFFL) << 0)) ++ ++/******************************************************************************* ++ * RB Register ++ ******************************************************************************/ ++ ++/* Receive Data Register Value (31:0) */ ++#define SSC_RB_RB_VAL (0xFFFFFFFFL) ++#define SSC_RB_RB_VAL_GET(val) ((((val) & SSC_RB_RB_VAL) >> 0) & 0xFFFFFFFFL) ++ ++/******************************************************************************* ++ * FSTAT Register ++ ******************************************************************************/ ++ ++/* Transmit FIFO Filling Level (13:8) */ ++#define SSC_FSTAT_TXFFL (0x3f << 8) ++#define SSC_FSTAT_TXFFL_GET(val) ((((val) & SSC_FSTAT_TXFFL) >> 8) & 0x3f) ++/* Receive FIFO Filling Level (5:0) */ ++#define SSC_FSTAT_RXFFL (0x3f) ++#define SSC_FSTAT_RXFFL_GET(val) ((((val) & SSC_FSTAT_RXFFL) >> 0) & 0x3f) ++ ++/******************************************************************************* ++ * PISEL Register ++ ******************************************************************************/ ++ ++/* Slave Mode Clock Input Select (2) */ ++#define SSC_PISEL_CIS (0x1 << 2) ++#define SSC_PISEL_CIS_VAL(val) (((val) & 0x1) << 2) ++#define SSC_PISEL_CIS_GET(val) ((((val) & SSC_PISEL_CIS) >> 2) & 0x1) ++#define SSC_PISEL_CIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_CIS) | (((val) & 0x1) << 2)) ++/* Slave Mode Receiver Input Select (1) */ ++#define SSC_PISEL_SIS (0x1 << 1) ++#define SSC_PISEL_SIS_VAL(val) (((val) & 0x1) << 1) ++#define SSC_PISEL_SIS_GET(val) ((((val) & SSC_PISEL_SIS) >> 1) & 0x1) ++#define SSC_PISEL_SIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_SIS) | (((val) & 0x1) << 1)) ++/* Master Mode Receiver Input Select (0) */ ++#define SSC_PISEL_MIS (0x1) ++#define SSC_PISEL_MIS_VAL(val) (((val) & 0x1) << 0) ++#define SSC_PISEL_MIS_GET(val) ((((val) & SSC_PISEL_MIS) >> 0) & 0x1) ++#define SSC_PISEL_MIS_SET(reg,val) (reg) = ((reg & ~SSC_PISEL_MIS) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * RXFCON Register ++ ******************************************************************************/ ++ ++/* Receive FIFO Interrupt Trigger Level (13:8) */ ++#define SSC_RXFCON_RXFITL (0x3f << 8) ++#define SSC_RXFCON_RXFITL_VAL(val) (((val) & 0x3f) << 8) ++#define SSC_RXFCON_RXFITL_GET(val) ((((val) & SSC_RXFCON_RXFITL) >> 8) & 0x3f) ++#define SSC_RXFCON_RXFITL_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFITL) | (((val) & 0x3f) << 8)) ++/* Receive FIFO Flush (1) */ ++#define SSC_RXFCON_RXFLU (0x1 << 1) ++#define SSC_RXFCON_RXFLU_VAL(val) (((val) & 0x1) << 1) ++#define SSC_RXFCON_RXFLU_SET(reg,val) (reg) = (((reg & ~SSC_RXFCON_RXFLU) | (val) & 1) << 1) ++/* Receive FIFO Enable (0) */ ++#define SSC_RXFCON_RXFEN (0x1) ++#define SSC_RXFCON_RXFEN_VAL(val) (((val) & 0x1) << 0) ++#define SSC_RXFCON_RXFEN_GET(val) ((((val) & SSC_RXFCON_RXFEN) >> 0) & 0x1) ++#define SSC_RXFCON_RXFEN_SET(reg,val) (reg) = ((reg & ~SSC_RXFCON_RXFEN) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * TXFCON Register ++ ******************************************************************************/ ++ ++/* Transmit FIFO Interrupt Trigger Level (13:8) */ ++#define SSC_TXFCON_TXFITL (0x3f << 8) ++#define SSC_TXFCON_TXFITL_VAL(val) (((val) & 0x3f) << 8) ++#define SSC_TXFCON_TXFITL_GET(val) ((((val) & SSC_TXFCON_TXFITL) >> 8) & 0x3f) ++#define SSC_TXFCON_TXFITL_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFITL) | (((val) & 0x3f) << 8)) ++/* Transmit FIFO Flush (1) */ ++#define SSC_TXFCON_TXFLU (0x1 << 1) ++#define SSC_TXFCON_TXFLU_VAL(val) (((val) & 0x1) << 1) ++#define SSC_TXFCON_TXFLU_SET(reg,val) (reg) = (((reg & ~SSC_TXFCON_TXFLU) | (val) & 1) << 1) ++/* Transmit FIFO Enable (0) */ ++#define SSC_TXFCON_TXFEN (0x1) ++#define SSC_TXFCON_TXFEN_VAL(val) (((val) & 0x1) << 0) ++#define SSC_TXFCON_TXFEN_GET(val) ((((val) & SSC_TXFCON_TXFEN) >> 0) & 0x1) ++#define SSC_TXFCON_TXFEN_SET(reg,val) (reg) = ((reg & ~SSC_TXFCON_TXFEN) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * BR Register ++ ******************************************************************************/ ++ ++/* Baudrate Timer Reload Register Value (15:0) */ ++#define SSC_BR_BR_VAL (0xffff) ++#define SSC_BR_BR_VAL_VAL(val) (((val) & 0xffff) << 0) ++#define SSC_BR_BR_VAL_GET(val) ((((val) & SSC_BR_BR_VAL) >> 0) & 0xffff) ++#define SSC_BR_BR_VAL_SET(reg,val) (reg) = ((reg & ~SSC_BR_BR_VAL) | (((val) & 0xffff) << 0)) ++ ++/******************************************************************************* ++ * BRSTAT Register ++ ******************************************************************************/ ++ ++/* Baudrate Timer Register Value (15:0) */ ++#define SSC_BRSTAT_BT_VAL (0xffff) ++#define SSC_BRSTAT_BT_VAL_GET(val) ((((val) & SSC_BRSTAT_BT_VAL) >> 0) & 0xffff) ++ ++/******************************************************************************* ++ * SFCON Register ++ ******************************************************************************/ ++ ++/* Pause Length (31:22) */ ++#define SSC_SFCON_PLEN (0x3ff << 22) ++#define SSC_SFCON_PLEN_VAL(val) (((val) & 0x3ff) << 22) ++#define SSC_SFCON_PLEN_GET(val) ((((val) & SSC_SFCON_PLEN) >> 22) & 0x3ff) ++#define SSC_SFCON_PLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_PLEN) | (((val) & 0x3ff) << 22)) ++/* Stop After Pause (20) */ ++#define SSC_SFCON_STOP (0x1 << 20) ++#define SSC_SFCON_STOP_VAL(val) (((val) & 0x1) << 20) ++#define SSC_SFCON_STOP_GET(val) ((((val) & SSC_SFCON_STOP) >> 20) & 0x1) ++#define SSC_SFCON_STOP_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_STOP) | (((val) & 0x1) << 20)) ++/* Idle Clock Configuration (19:18) */ ++#define SSC_SFCON_ICLK (0x3 << 18) ++#define SSC_SFCON_ICLK_VAL(val) (((val) & 0x3) << 18) ++#define SSC_SFCON_ICLK_GET(val) ((((val) & SSC_SFCON_ICLK) >> 18) & 0x3) ++#define SSC_SFCON_ICLK_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_ICLK) | (((val) & 0x3) << 18)) ++/* Idle Data Configuration (17:16) */ ++#define SSC_SFCON_IDAT (0x3 << 16) ++#define SSC_SFCON_IDAT_VAL(val) (((val) & 0x3) << 16) ++#define SSC_SFCON_IDAT_GET(val) ((((val) & SSC_SFCON_IDAT) >> 16) & 0x3) ++#define SSC_SFCON_IDAT_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IDAT) | (((val) & 0x3) << 16)) ++/* Data Length (15:4) */ ++#define SSC_SFCON_DLEN (0xfff << 4) ++#define SSC_SFCON_DLEN_VAL(val) (((val) & 0xfff) << 4) ++#define SSC_SFCON_DLEN_GET(val) ((((val) & SSC_SFCON_DLEN) >> 4) & 0xfff) ++#define SSC_SFCON_DLEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_DLEN) | (((val) & 0xfff) << 4)) ++/* Enable Interrupt After Pause (3) */ ++#define SSC_SFCON_IAEN (0x1 << 3) ++#define SSC_SFCON_IAEN_VAL(val) (((val) & 0x1) << 3) ++#define SSC_SFCON_IAEN_GET(val) ((((val) & SSC_SFCON_IAEN) >> 3) & 0x1) ++#define SSC_SFCON_IAEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IAEN) | (((val) & 0x1) << 3)) ++/* Enable Interrupt Before Pause (2) */ ++#define SSC_SFCON_IBEN (0x1 << 2) ++#define SSC_SFCON_IBEN_VAL(val) (((val) & 0x1) << 2) ++#define SSC_SFCON_IBEN_GET(val) ((((val) & SSC_SFCON_IBEN) >> 2) & 0x1) ++#define SSC_SFCON_IBEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_IBEN) | (((val) & 0x1) << 2)) ++/* Serial Frame Enable (0) */ ++#define SSC_SFCON_SFEN (0x1) ++#define SSC_SFCON_SFEN_VAL(val) (((val) & 0x1) << 0) ++#define SSC_SFCON_SFEN_GET(val) ((((val) & SSC_SFCON_SFEN) >> 0) & 0x1) ++#define SSC_SFCON_SFEN_SET(reg,val) (reg) = ((reg & ~SSC_SFCON_SFEN) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * SFSTAT Register ++ ******************************************************************************/ ++ ++/* Pause Count (31:22) */ ++#define SSC_SFSTAT_PCNT (0x3ff << 22) ++#define SSC_SFSTAT_PCNT_GET(val) ((((val) & SSC_SFSTAT_PCNT) >> 22) & 0x3ff) ++/* Data Bit Count (15:4) */ ++#define SSC_SFSTAT_DCNT (0xfff << 4) ++#define SSC_SFSTAT_DCNT_GET(val) ((((val) & SSC_SFSTAT_DCNT) >> 4) & 0xfff) ++/* Pause Busy (1) */ ++#define SSC_SFSTAT_PBSY (0x1 << 1) ++#define SSC_SFSTAT_PBSY_GET(val) ((((val) & SSC_SFSTAT_PBSY) >> 1) & 0x1) ++/* Data Busy (0) */ ++#define SSC_SFSTAT_DBSY (0x1) ++#define SSC_SFSTAT_DBSY_GET(val) ((((val) & SSC_SFSTAT_DBSY) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * GPOCON Register ++ ******************************************************************************/ ++ ++/* Output OUTn Is Chip Select (15:8) */ ++#define SSC_GPOCON_ISCSBN (0xff << 8) ++#define SSC_GPOCON_ISCSBN_VAL(val) (((val) & 0xff) << 8) ++#define SSC_GPOCON_ISCSBN_GET(val) ((((val) & SSC_GPOCON_ISCSBN) >> 8) & 0xff) ++#define SSC_GPOCON_ISCSBN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_ISCSBN) | (((val) & 0xff) << 8)) ++/* Invert Output OUTn (7:0) */ ++#define SSC_GPOCON_INVOUTN (0xff) ++#define SSC_GPOCON_INVOUTN_VAL(val) (((val) & 0xff) << 0) ++#define SSC_GPOCON_INVOUTN_GET(val) ((((val) & SSC_GPOCON_INVOUTN) >> 0) & 0xff) ++#define SSC_GPOCON_INVOUTN_SET(reg,val) (reg) = ((reg & ~SSC_GPOCON_INVOUTN) | (((val) & 0xff) << 0)) ++ ++/******************************************************************************* ++ * GPOSTAT Register ++ ******************************************************************************/ ++ ++/* Output Register Bit n (7:0) */ ++#define SSC_GPOSTAT_OUTN (0xff) ++#define SSC_GPOSTAT_OUTN_GET(val) ((((val) & SSC_GPOSTAT_OUTN) >> 0) & 0xff) ++ ++/******************************************************************************* ++ * WHBGPOSTAT ++ ******************************************************************************/ ++ ++/* Set Output Register Bit n (15:8) */ ++#define SSC_WHBGPOSTAT_SETOUTN (0xff << 8) ++#define SSC_WHBGPOSTAT_SETOUTN_VAL(val) (((val) & 0xff) << 8) ++#define SSC_WHBGPOSTAT_SETOUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_SETOUTN) | (val) & 1) << 8) ++/* Clear Output Register Bit n (7:0) */ ++#define SSC_WHBGPOSTAT_CLROUTN (0xff) ++#define SSC_WHBGPOSTAT_CLROUTN_VAL(val) (((val) & 0xff) << 0) ++#define SSC_WHBGPOSTAT_CLROUTN_SET(reg,val) (reg) = (((reg & ~SSC_WHBGPOSTAT_CLROUTN) | (val) & 1) << 0) ++ ++/******************************************************************************* ++ * RXREQ Register ++ ******************************************************************************/ ++ ++/* Receive Count Value (15:0) */ ++#define SSC_RXREQ_RXCNT (0xffff) ++#define SSC_RXREQ_RXCNT_VAL(val) (((val) & 0xffff) << 0) ++#define SSC_RXREQ_RXCNT_GET(val) ((((val) & SSC_RXREQ_RXCNT) >> 0) & 0xffff) ++#define SSC_RXREQ_RXCNT_SET(reg,val) (reg) = ((reg & ~SSC_RXREQ_RXCNT) | (((val) & 0xffff) << 0)) ++ ++/******************************************************************************* ++ * RXCNT Register ++ ******************************************************************************/ ++ ++/* Receive To Do Value (15:0) */ ++#define SSC_RXCNT_TODO (0xffff) ++#define SSC_RXCNT_TODO_GET(val) ((((val) & SSC_RXCNT_TODO) >> 0) & 0xffff) ++ ++/******************************************************************************* ++ * DMA_CON Register ++ ******************************************************************************/ ++ ++/* Receive Class (3:2) */ ++#define SSC_DMA_CON_RXCLS (0x3 << 2) ++#define SSC_DMA_CON_RXCLS_VAL(val) (((val) & 0x3) << 2) ++#define SSC_DMA_CON_RXCLS_GET(val) ((((val) & SSC_DMA_CON_RXCLS) >> 2) & 0x3) ++#define SSC_DMA_CON_RXCLS_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXCLS) | (((val) & 0x3) << 2)) ++/* Transmit Path On (1) */ ++#define SSC_DMA_CON_TXON (0x1 << 1) ++#define SSC_DMA_CON_TXON_VAL(val) (((val) & 0x1) << 1) ++#define SSC_DMA_CON_TXON_GET(val) ((((val) & SSC_DMA_CON_TXON) >> 1) & 0x1) ++#define SSC_DMA_CON_TXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_TXON) | (((val) & 0x1) << 1)) ++/* Receive Path On (0) */ ++#define SSC_DMA_CON_RXON (0x1) ++#define SSC_DMA_CON_RXON_VAL(val) (((val) & 0x1) << 0) ++#define SSC_DMA_CON_RXON_GET(val) ((((val) & SSC_DMA_CON_RXON) >> 0) & 0x1) ++#define SSC_DMA_CON_RXON_SET(reg,val) (reg) = ((reg & ~SSC_DMA_CON_RXON) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * IRNEN Register ++ ******************************************************************************/ ++ ++/* Frame End Interrupt Request Enable (3) */ ++#define SSC_IRNEN_F (0x1 << 3) ++#define SSC_IRNEN_F_VAL(val) (((val) & 0x1) << 3) ++#define SSC_IRNEN_F_GET(val) ((((val) & SSC_IRNEN_F) >> 3) & 0x1) ++#define SSC_IRNEN_F_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_F) | (((val) & 0x1) << 3)) ++/* Error Interrupt Request Enable (2) */ ++#define SSC_IRNEN_E (0x1 << 2) ++#define SSC_IRNEN_E_VAL(val) (((val) & 0x1) << 2) ++#define SSC_IRNEN_E_GET(val) ((((val) & SSC_IRNEN_E) >> 2) & 0x1) ++#define SSC_IRNEN_E_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_E) | (((val) & 0x1) << 2)) ++/* Receive Interrupt Request Enable (1) */ ++#define SSC_IRNEN_R (0x1 << 1) ++#define SSC_IRNEN_R_VAL(val) (((val) & 0x1) << 1) ++#define SSC_IRNEN_R_GET(val) ((((val) & SSC_IRNEN_R) >> 1) & 0x1) ++#define SSC_IRNEN_R_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_R) | (((val) & 0x1) << 1)) ++/* Transmit Interrupt Request Enable (0) */ ++#define SSC_IRNEN_T (0x1) ++#define SSC_IRNEN_T_VAL(val) (((val) & 0x1) << 0) ++#define SSC_IRNEN_T_GET(val) ((((val) & SSC_IRNEN_T) >> 0) & 0x1) ++#define SSC_IRNEN_T_SET(reg,val) (reg) = ((reg & ~SSC_IRNEN_T) | (((val) & 0x1) << 0)) ++ ++/******************************************************************************* ++ * IRNICR Register ++ ******************************************************************************/ ++ ++/* Frame End Interrupt Request (3) */ ++#define SSC_IRNICR_F (0x1 << 3) ++#define SSC_IRNICR_F_GET(val) ((((val) & SSC_IRNICR_F) >> 3) & 0x1) ++/* Error Interrupt Request (2) */ ++#define SSC_IRNICR_E (0x1 << 2) ++#define SSC_IRNICR_E_GET(val) ((((val) & SSC_IRNICR_E) >> 2) & 0x1) ++/* Receive Interrupt Request (1) */ ++#define SSC_IRNICR_R (0x1 << 1) ++#define SSC_IRNICR_R_GET(val) ((((val) & SSC_IRNICR_R) >> 1) & 0x1) ++/* Transmit Interrupt Request (0) */ ++#define SSC_IRNICR_T (0x1) ++#define SSC_IRNICR_T_GET(val) ((((val) & SSC_IRNICR_T) >> 0) & 0x1) ++ ++/******************************************************************************* ++ * IRNCR Register ++ ******************************************************************************/ ++ ++/* Frame End Interrupt Request (3) */ ++#define SSC_IRNCR_F (0x1 << 3) ++#define SSC_IRNCR_F_GET(val) ((((val) & SSC_IRNCR_F) >> 3) & 0x1) ++/* Error Interrupt Request (2) */ ++#define SSC_IRNCR_E (0x1 << 2) ++#define SSC_IRNCR_E_GET(val) ((((val) & SSC_IRNCR_E) >> 2) & 0x1) ++/* Receive Interrupt Request (1) */ ++#define SSC_IRNCR_R (0x1 << 1) ++#define SSC_IRNCR_R_GET(val) ((((val) & SSC_IRNCR_R) >> 1) & 0x1) ++/* Transmit Interrupt Request (0) */ ++#define SSC_IRNCR_T (0x1) ++#define SSC_IRNCR_T_GET(val) ((((val) & SSC_IRNCR_T) >> 0) & 0x1) ++ ++#endif /* __SSC_H */ +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_mux.h 2012-07-31 15:46:02.484476159 +0200 +@@ -0,0 +1,467 @@ ++/************************************************************************ ++ * ++ * Copyright (c) 2007 ++ * Infineon Technologies AG ++ * St. Martin Strasse 53; 81669 Muenchen; Germany ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ ************************************************************************/ ++ ++#ifndef __SVIP_MUX_H ++#define __SVIP_MUX_H ++ ++#define LTQ_MUX_P0_PINS 20 ++#define LTQ_MUX_P1_PINS 20 ++#define LTQ_MUX_P2_PINS 19 ++#define LTQ_MUX_P3_PINS 20 ++#define LTQ_MUX_P4_PINS 24 ++ ++struct ltq_mux_pin { ++ int dirin; ++ int puen; ++ int altsel0; ++ int altsel1; ++}; ++ ++struct ltq_mux_settings { ++ const struct ltq_mux_pin *mux_p0; ++ const struct ltq_mux_pin *mux_p1; ++ const struct ltq_mux_pin *mux_p2; ++ const struct ltq_mux_pin *mux_p3; ++ const struct ltq_mux_pin *mux_p4; ++}; ++ ++#define LTQ_MUX_P0_19_EXINT16 { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_19 { 0, 0, 1, 0 } ++ ++#define LTQ_MUX_P0_18_EJ_BRKIN { 1, 0, 0, 0 } ++#define LTQ_MUX_P0_18 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_18_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P0_17_EXINT10 { 1, 0, 0, 0 } ++#define LTQ_MUX_P0_17 { 0, 0, 0, 0 } ++#define LTQ_MUX_P0_17_ASC1_RXD { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P0_16_EXINT9 { 1, 0, 0, 0 } ++#define LTQ_MUX_P0_16 { 0, 0, 0, 0 } ++#define LTQ_MUX_P0_16_ASC1_TXD { 0, 0, 1, 0 } ++ ++#define LTQ_MUX_P0_15_EXINT8 { 1, 0, 0, 0 } ++#define LTQ_MUX_P0_15 { 0, 0, 0, 0 } ++#define LTQ_MUX_P0_15_ASC0_RXD { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P0_14_EXINT7 { 1, 0, 0, 0 } ++#define LTQ_MUX_P0_14 { 0, 0, 0, 0 } ++#define LTQ_MUX_P0_14_ASC0_TXD { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P0_13_SSC0_CS7 { 0, 1, 0, 0 } ++#define LTQ_MUX_P0_13_EXINT6 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_13 { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_13_SSC1_CS7 { 0, 0, 0, 1 } ++#define LTQ_MUX_P0_13_SSC1_INT { 0, 0, 1, 1 } ++ ++#define LTQ_MUX_P0_12_SSC0_CS6 { 0, 1, 0, 0 } ++#define LTQ_MUX_P0_12_EXINT5 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_12 { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_12_SSC1_CS6 { 0, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_11_SSC0_CS5 { 0, 1, 0, 0 } ++#define LTQ_MUX_P0_11_EXINT4 { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_11 { 1, 0, 0, 0 } ++#define LTQ_MUX_P0_11_SSC1_CS5 { 0, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_10_SSC0_CS4 { 0, 1, 0, 0 } ++#define LTQ_MUX_P0_10_EXINT3 { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_10 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_10_SSC1_CS4 { 0, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_9_SSC0_CS3 { 0, 1, 0, 0 } ++#define LTQ_MUX_P0_9_EXINT2 { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_9 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_9_SSC1_CS3 { 0, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_8_SSC0_CS2 { 0, 1, 0, 0 } ++#define LTQ_MUX_P0_8_EXINT1 { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_8 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_8_SSC1_CS2 { 0, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_7_SSC0_CS1 { 0, 1, 0, 0 } ++#define LTQ_MUX_P0_7_EXINT0 { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_7 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_7_SSC1_CS1 { 0, 0, 0, 1 } ++#define LTQ_MUX_P0_7_SSC1_CS0 { 1, 0, 0, 1 } ++#define LTQ_MUX_P0_7_SSC2_CS0 { 1, 0, 1, 1 } ++ ++#define LTQ_MUX_P0_6_SSC0_CS0 { 0, 1, 0, 0 } ++#define LTQ_MUX_P0_6 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_6_IN { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_6_SSC1_CS0 { 0, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_5_SSC1_SCLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P0_5 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_5_IN { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_5_SSC2_CLK { 1, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_4_SSC1_MRST { 1, 0, 0, 0 } ++#define LTQ_MUX_P0_4 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_4_IN { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_4_SSC2_MRST { 0, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_3_SSC1_MTSR { 0, 0, 0, 0 } ++#define LTQ_MUX_P0_3 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_3_IN { 1, 0, 1, 0 } ++#define LTQ_MUX_P0_3_SSC2_MTSR { 0, 0, 0, 1 } ++ ++#define LTQ_MUX_P0_2_SSC0_SCLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P0_2 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_2_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P0_1_SSC0_MRST { 1, 0, 0, 0 } ++#define LTQ_MUX_P0_1 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_1_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P0_0_SSC0_MTSR { 0, 0, 0, 0 } ++#define LTQ_MUX_P0_0 { 0, 0, 1, 0 } ++#define LTQ_MUX_P0_0_IN { 1, 0, 1, 0 } ++ ++ ++#define LTQ_MUX_P1_19_PCM3_TC1 { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_19_EXINT15 { 1, 0, 1, 0 } ++#define LTQ_MUX_P1_19 { 0, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_18_PCM3_FSC { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_18_EXINT11 { 1, 0, 1, 0 } ++#define LTQ_MUX_P1_18 { 0, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_17_PCM3_PCL { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_17_EXINT12 { 1, 0, 1, 0 } ++#define LTQ_MUX_P1_17 { 0, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_16_PCM3_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_16_EXINT13 { 1, 0, 1, 0 } ++#define LTQ_MUX_P1_16 { 0, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_15_PCM3_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_15_EXINT14 { 1, 0, 1, 0 } ++#define LTQ_MUX_P1_15 { 0, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_14_PCM2_TC1 { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_14 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_14_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_13_PCM2_FSC { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_13 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_13_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_12_PCM2_PCL { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_12 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_12_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_11_PCM2_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_11 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_11_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_10_PCM2_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_10 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_10_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_9_PCM1_TC1 { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_9 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_9_IN { 0, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_8_PCM1_FSC { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_8 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_8_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_7_PCM1_PCL { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_7 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_7_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_6_PCM1_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_6 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_6_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_5_PCM1_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_5 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_5_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_4_PCM0_TC1 { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_4 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_4_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_3_PCM0_FSC { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_3 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_3_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_2_PCM0_PCL { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_2 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_2_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_1_PCM0_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_1 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_1_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P1_0_PCM0_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P1_0 { 0, 0, 1, 0 } ++#define LTQ_MUX_P1_0_IN { 1, 0, 1, 0 } ++ ++ ++#define LTQ_MUX_P2_18_EBU_BC1 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_18 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_18_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_17_EBU_BC0 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_17 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_17_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_16_EBU_RDBY { 1, 0, 0, 0 } ++#define LTQ_MUX_P2_16 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_16_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_15_EBU_WAIT { 1, 0, 0, 0 } ++#define LTQ_MUX_P2_15 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_15_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_14_EBU_ALE { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_14 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_14_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_13_EBU_WR { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_13 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_13_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_12_EBU_RD { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_12 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_12_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_11_EBU_A11 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_11 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_11_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_10_EBU_A10 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_10 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_10_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_9_EBU_A9 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_9 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_9_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_8_EBU_A8 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_8 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_8_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_7_EBU_A7 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_7 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_7_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_6_EBU_A6 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_6 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_6_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_5_EBU_A5 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_5 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_5_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_4_EBU_A4 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_4 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_4_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_3_EBU_A3 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_3 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_3_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_2_EBU_A2 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_2 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_2_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_1_EBU_A1 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_1 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_1_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P2_0_EBU_A0 { 0, 0, 0, 0 } ++#define LTQ_MUX_P2_0 { 0, 0, 1, 0 } ++#define LTQ_MUX_P2_0_IN { 1, 0, 1, 0 } ++ ++ ++#define LTQ_MUX_P3_19_EBU_CS3 { 0, 0, 0, 0 } ++#define LTQ_MUX_P3_19 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_19_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_18_EBU_CS2 { 0, 0, 0, 0 } ++#define LTQ_MUX_P3_18 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_18_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_17_EBU_CS1 { 0, 0, 0, 0 } ++#define LTQ_MUX_P3_17 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_17_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_16_EBU_CS0 { 0, 0, 0, 0 } ++#define LTQ_MUX_P3_16 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_16_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_15_EBU_AD15 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_15 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_15_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_14_EBU_AD14 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_14 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_14_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_13_EBU_AD13 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_13 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_13_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_12_EBU_AD12 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_12 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_12_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_11_EBU_AD11 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_11 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_11_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_10_EBU_AD10 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_10 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_10_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_9_EBU_AD9 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_9 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_9_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_8_EBU_AD8 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_8 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_8_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_7_EBU_AD7 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_7 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_7_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_6_EBU_AD6 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_6 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_6_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_5_EBU_AD5 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_5 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_5_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_4_EBU_AD4 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_4 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_4_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_3_EBU_AD3 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_3 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_3_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_2_EBU_AD2 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_2 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_2_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_1_EBU_AD1 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_1 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_1_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P3_0_EBU_AD0 { 1, 0, 0, 0 } ++#define LTQ_MUX_P3_0 { 0, 0, 1, 0 } ++#define LTQ_MUX_P3_0_IN { 1, 0, 1, 0 } ++ ++ ++#define LTQ_MUX_P4_23_SSLIC7_CLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_23 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_23_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_22_SSLIC7_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_22 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_22_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_21_SSLIC7_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_21 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_21_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_20_SSLIC6_CLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_20 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_20_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_19_SSLIC6_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_19 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_19_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_18_SSLIC6_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_18 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_18_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_17_SSLIC5_CLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_17 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_17_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_16_SSLIC5_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_16 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_16_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_15_SSLIC5_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_15 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_15_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_14_SSLIC4_CLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_14 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_14_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_13_SSLIC4_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_13 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_13_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_12_SSLIC4_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_12 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_12_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_11_SSLIC3_CLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_11 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_11_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_10_SSLIC3_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_10 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_10_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_9_SSLIC3_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_9 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_9_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_8_SSLIC2_CLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_8 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_8_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_7_SSLIC2_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_7 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_7_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_6_SSLIC2_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_6 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_6_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_5_SSLIC1_CLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_5 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_5_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_4_SSLIC1_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_4 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_4_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_3_SSLIC1_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_3 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_3_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_2_SSLIC0_CLK { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_2 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_2_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_1_SSLIC0_RX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_1 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_1_IN { 1, 0, 1, 0 } ++ ++#define LTQ_MUX_P4_0_SSLIC0_TX { 0, 0, 0, 0 } ++#define LTQ_MUX_P4_0 { 0, 0, 1, 0 } ++#define LTQ_MUX_P4_0_IN { 1, 0, 1, 0 } ++ ++#endif +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/sys2_reg.h 2012-07-31 15:46:02.484476159 +0200 +@@ -0,0 +1,494 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ St. Martin Strasse 53; 81669 Munich, Germany ++ ++ Any use of this Software is subject to the conclusion of a respective ++ License Agreement. Without such a License Agreement no rights to the ++ Software are granted. ++ ++ ******************************************************************************/ ++ ++#ifndef __SYS2_REG_H ++#define __SYS2_REG_H ++ ++#define sys2_r32(reg) ltq_r32(&sys2->reg) ++#define sys2_w32(val, reg) ltq_w32(val, &sys2->reg) ++#define sys2_w32_mask(clear, set, reg) ltq_w32_mask(clear, set, &sys2->reg) ++ ++/** SYS2 register structure */ ++struct svip_reg_sys2 { ++ volatile unsigned long clksr; /* 0x0000 */ ++ volatile unsigned long clkenr; /* 0x0004 */ ++ volatile unsigned long clkclr; /* 0x0008 */ ++ volatile unsigned long reserved0[1]; ++ volatile unsigned long rsr; /* 0x0010 */ ++ volatile unsigned long rreqr; /* 0x0014 */ ++ volatile unsigned long rrlsr; /* 0x0018 */ ++}; ++ ++/******************************************************************************* ++ * SYS2 Clock Status Register ++ ******************************************************************************/ ++ ++/* Clock Enable for PORT4 */ ++#define SYS2_CLKSR_PORT4 (0x1 << 27) ++#define SYS2_CLKSR_PORT4_VAL(val) (((val) & 0x1) << 27) ++#define SYS2_CLKSR_PORT4_GET(val) (((val) & SYS2_CLKSR_PORT4) >> 27) ++/* Clock Enable for HWSYNC */ ++#define SYS2_CLKSR_HWSYNC (0x1 << 26) ++#define SYS2_CLKSR_HWSYNC_VAL(val) (((val) & ++#define SYS2_CLKSR_HWSYNC_GET(val) (((val) & SYS2_CLKSR_HWSYNC) >> 26) ++ /* Clock Enable for MBS */ ++#define SYS2_CLKSR_MBS (0x1 << 25) ++#define SYS2_CLKSR_MBS_VAL(val) (((val) & 0x1) << 25) ++#define SYS2_CLKSR_MBS_GET(val) (((val) & SYS2_CLKSR_MBS) >> 25) ++ /* Clock Enable for SWINT */ ++#define SYS2_CLKSR_SWINT (0x1 << 24) ++#define SYS2_CLKSR_SWINT_VAL(val) (((val) & 0x1) << 24) ++#define SYS2_CLKSR_SWINT_GET(val) (((val) & SYS2_CLKSR_SWINT) >> 24) ++ /* Clock Enable for HWACC3 */ ++#define SYS2_CLKSR_HWACC3 (0x1 << 19) ++#define SYS2_CLKSR_HWACC3_VAL(val) (((val) & ++#define SYS2_CLKSR_HWACC3_GET(val) (((val) & SYS2_CLKSR_HWACC3) >> 19) ++ /* Clock Enable for HWACC2 */ ++#define SYS2_CLKSR_HWACC2 (0x1 << 18) ++#define SYS2_CLKSR_HWACC2_VAL(val) (((val) & ++#define SYS2_CLKSR_HWACC2_GET(val) (((val) & SYS2_CLKSR_HWACC2) >> 18) ++ /* Clock Enable for HWACC1 */ ++#define SYS2_CLKSR_HWACC1 (0x1 << 17) ++#define SYS2_CLKSR_HWACC1_VAL(val) (((val) & ++#define SYS2_CLKSR_HWACC1_GET(val) (((val) & SYS2_CLKSR_HWACC1) >> 17) ++ /* Clock Enable for HWACC0 */ ++#define SYS2_CLKSR_HWACC0 (0x1 << 16) ++#define SYS2_CLKSR_HWACC0_VAL(val) (((val) & ++#define SYS2_CLKSR_HWACC0_GET(val) (((val) & SYS2_CLKSR_HWACC0) >> 16) ++ /* Clock Enable for SIF7 */ ++#define SYS2_CLKSR_SIF7 (0x1 << 15) ++#define SYS2_CLKSR_SIF7_VAL(val) (((val) & 0x1) << 15) ++#define SYS2_CLKSR_SIF7_GET(val) (((val) & SYS2_CLKSR_SIF7) >> 15) ++ /* Clock Enable for SIF6 */ ++#define SYS2_CLKSR_SIF6 (0x1 << 14) ++#define SYS2_CLKSR_SIF6_VAL(val) (((val) & 0x1) << 14) ++#define SYS2_CLKSR_SIF6_GET(val) (((val) & SYS2_CLKSR_SIF6) >> 14) ++ /* Clock Enable for SIF5 */ ++#define SYS2_CLKSR_SIF5 (0x1 << 13) ++#define SYS2_CLKSR_SIF5_VAL(val) (((val) & 0x1) << 13) ++#define SYS2_CLKSR_SIF5_GET(val) (((val) & SYS2_CLKSR_SIF5) >> 13) ++ /* Clock Enable for SIF4 */ ++#define SYS2_CLKSR_SIF4 (0x1 << 12) ++#define SYS2_CLKSR_SIF4_VAL(val) (((val) & 0x1) << 12) ++#define SYS2_CLKSR_SIF4_GET(val) (((val) & SYS2_CLKSR_SIF4) >> 12) ++ /* Clock Enable for SIF3 */ ++#define SYS2_CLKSR_SIF3 (0x1 << 11) ++#define SYS2_CLKSR_SIF3_VAL(val) (((val) & 0x1) << 11) ++#define SYS2_CLKSR_SIF3_GET(val) (((val) & SYS2_CLKSR_SIF3) >> 11) ++/* Clock Enable for SIF2 */ ++#define SYS2_CLKSR_SIF2 (0x1 << 10) ++#define SYS2_CLKSR_SIF2_VAL(val) (((val) & 0x1) << 10) ++#define SYS2_CLKSR_SIF2_GET(val) (((val) & SYS2_CLKSR_SIF2) >> 10) ++/* Clock Enable for SIF1 */ ++#define SYS2_CLKSR_SIF1 (0x1 << 9) ++#define SYS2_CLKSR_SIF1_VAL(val) (((val) & 0x1) << 9) ++#define SYS2_CLKSR_SIF1_GET(val) (((val) & SYS2_CLKSR_SIF1) >> 9) ++/* Clock Enable for SIF0 */ ++#define SYS2_CLKSR_SIF0 (0x1 << 8) ++#define SYS2_CLKSR_SIF0_VAL(val) (((val) & 0x1) << 8) ++#define SYS2_CLKSR_SIF0_GET(val) (((val) & SYS2_CLKSR_SIF0) >> 8) ++/* Clock Enable for DFEV7 */ ++#define SYS2_CLKSR_DFEV7 (0x1 << 7) ++#define SYS2_CLKSR_DFEV7_VAL(val) (((val) & 0x1) << 7) ++#define SYS2_CLKSR_DFEV7_GET(val) (((val) & SYS2_CLKSR_DFEV7) >> 7) ++/* Clock Enable for DFEV6 */ ++#define SYS2_CLKSR_DFEV6 (0x1 << 6) ++#define SYS2_CLKSR_DFEV6_VAL(val) (((val) & 0x1) << 6) ++#define SYS2_CLKSR_DFEV6_GET(val) (((val) & SYS2_CLKSR_DFEV6) >> 6) ++/* Clock Enable for DFEV5 */ ++#define SYS2_CLKSR_DFEV5 (0x1 << 5) ++#define SYS2_CLKSR_DFEV5_VAL(val) (((val) & 0x1) << 5) ++#define SYS2_CLKSR_DFEV5_GET(val) (((val) & SYS2_CLKSR_DFEV5) >> 5) ++/* Clock Enable for DFEV4 */ ++#define SYS2_CLKSR_DFEV4 (0x1 << 4) ++#define SYS2_CLKSR_DFEV4_VAL(val) (((val) & 0x1) << 4) ++#define SYS2_CLKSR_DFEV4_GET(val) (((val) & SYS2_CLKSR_DFEV4) >> 4) ++/* Clock Enable for DFEV3 */ ++#define SYS2_CLKSR_DFEV3 (0x1 << 3) ++#define SYS2_CLKSR_DFEV3_VAL(val) (((val) & 0x1) << 3) ++#define SYS2_CLKSR_DFEV3_GET(val) (((val) & SYS2_CLKSR_DFEV3) >> 3) ++/* Clock Enable for DFEV2 */ ++#define SYS2_CLKSR_DFEV2 (0x1 << 2) ++#define SYS2_CLKSR_DFEV2_VAL(val) (((val) & 0x1) << 2) ++#define SYS2_CLKSR_DFEV2_GET(val) (((val) & SYS2_CLKSR_DFEV2) >> 2) ++/* Clock Enable for DFEV1 */ ++#define SYS2_CLKSR_DFEV1 (0x1 << 1) ++#define SYS2_CLKSR_DFEV1_VAL(val) (((val) & 0x1) << 1) ++#define SYS2_CLKSR_DFEV1_GET(val) (((val) & SYS2_CLKSR_DFEV1) >> 1) ++/* Clock Enable for DFEV0 */ ++#define SYS2_CLKSR_DFEV0 (0x1) ++#define SYS2_CLKSR_DFEV0_VAL(val) (((val) & 0x1)) ++#define SYS2_CLKSR_DFEV0_GET(val) ((val) & SYS2_CLKSR_DFEV0) ++ ++/******************************************************************************* ++ * SYS2 Clock Enable Register ++ ******************************************************************************/ ++ ++/* Clock Enable Request for PORT4 */ ++#define SYS2_CLKENR_PORT4 (0x1 << 27) ++#define SYS2_CLKENR_PORT4_VAL(val) (((val) & 0x1) << 27) ++#define SYS2_CLKENR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_PORT4) | ((val & 0x1) << 27)) ++/* Clock Enable Request for HWSYNC */ ++#define SYS2_CLKENR_HWSYNC (0x1 << 26) ++#define SYS2_CLKENR_HWSYNC_VAL(val) (((val) & 0x1) << 26) ++#define SYS2_CLKENR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWSYNC) | ((val & 0x1) << 26)) ++/* Clock Enable Request for MBS */ ++#define SYS2_CLKENR_MBS (0x1 << 25) ++#define SYS2_CLKENR_MBS_VAL(val) (((val) & 0x1) << 25) ++#define SYS2_CLKENR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_MBS) | ((val & 0x1) << 25)) ++/* Clock Enable Request for SWINT */ ++#define SYS2_CLKENR_SWINT (0x1 << 24) ++#define SYS2_CLKENR_SWINT_VAL(val) (((val) & 0x1) << 24) ++#define SYS2_CLKENR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SWINT) | ((val & 0x1) << 24)) ++/* Clock Enable Request for HWACC3 */ ++#define SYS2_CLKENR_HWACC3 (0x1 << 19) ++#define SYS2_CLKENR_HWACC3_VAL(val) (((val) & 0x1) << 19) ++#define SYS2_CLKENR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC3) | ((val & 0x1) << 19)) ++/* Clock Enable Request for HWACC2 */ ++#define SYS2_CLKENR_HWACC2 (0x1 << 18) ++#define SYS2_CLKENR_HWACC2_VAL(val) (((val) & 0x1) << 18) ++#define SYS2_CLKENR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC2) | ((val & 0x1) << 18)) ++/* Clock Enable Request for HWACC1 */ ++#define SYS2_CLKENR_HWACC1 (0x1 << 17) ++#define SYS2_CLKENR_HWACC1_VAL(val) (((val) & 0x1) << 17) ++#define SYS2_CLKENR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC1) | ((val & 0x1) << 17)) ++/* Clock Enable Request for HWACC0 */ ++#define SYS2_CLKENR_HWACC0 (0x1 << 16) ++#define SYS2_CLKENR_HWACC0_VAL(val) (((val) & 0x1) << 16) ++#define SYS2_CLKENR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_HWACC0) | ((val & 0x1) << 16)) ++/* Clock Enable Request for SIF7 */ ++#define SYS2_CLKENR_SIF7 (0x1 << 15) ++#define SYS2_CLKENR_SIF7_VAL(val) (((val) & 0x1) << 15) ++#define SYS2_CLKENR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF7) | ((val & 0x1) << 15)) ++/* Clock Enable Request for SIF6 */ ++#define SYS2_CLKENR_SIF6 (0x1 << 14) ++#define SYS2_CLKENR_SIF6_VAL(val) (((val) & 0x1) << 14) ++#define SYS2_CLKENR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF6) | ((val & 0x1) << 14)) ++/* Clock Enable Request for SIF5 */ ++#define SYS2_CLKENR_SIF5 (0x1 << 13) ++#define SYS2_CLKENR_SIF5_VAL(val) (((val) & 0x1) << 13) ++#define SYS2_CLKENR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF5) | ((val & 0x1) << 13)) ++/* Clock Enable Request for SIF4 */ ++#define SYS2_CLKENR_SIF4 (0x1 << 12) ++#define SYS2_CLKENR_SIF4_VAL(val) (((val) & 0x1) << 12) ++#define SYS2_CLKENR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF4) | ((val & 0x1) << 12)) ++/* Clock Enable Request for SIF3 */ ++#define SYS2_CLKENR_SIF3 (0x1 << 11) ++#define SYS2_CLKENR_SIF3_VAL(val) (((val) & 0x1) << 11) ++#define SYS2_CLKENR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF3) | ((val & 0x1) << 11)) ++/* Clock Enable Request for SIF2 */ ++#define SYS2_CLKENR_SIF2 (0x1 << 10) ++#define SYS2_CLKENR_SIF2_VAL(val) (((val) & 0x1) << 10) ++#define SYS2_CLKENR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF2) | ((val & 0x1) << 10)) ++/* Clock Enable Request for SIF1 */ ++#define SYS2_CLKENR_SIF1 (0x1 << 9) ++#define SYS2_CLKENR_SIF1_VAL(val) (((val) & 0x1) << 9) ++#define SYS2_CLKENR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF1) | ((val & 0x1) << 9)) ++/* Clock Enable Request for SIF0 */ ++#define SYS2_CLKENR_SIF0 (0x1 << 8) ++#define SYS2_CLKENR_SIF0_VAL(val) (((val) & 0x1) << 8) ++#define SYS2_CLKENR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_SIF0) | ((val & 0x1) << 8)) ++/* Clock Enable Request for DFEV7 */ ++#define SYS2_CLKENR_DFEV7 (0x1 << 7) ++#define SYS2_CLKENR_DFEV7_VAL(val) (((val) & 0x1) << 7) ++#define SYS2_CLKENR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV7) | ((val & 0x1) << 7)) ++/* Clock Enable Request for DFEV6 */ ++#define SYS2_CLKENR_DFEV6 (0x1 << 6) ++#define SYS2_CLKENR_DFEV6_VAL(val) (((val) & 0x1) << 6) ++#define SYS2_CLKENR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV6) | ((val & 0x1) << 6)) ++/* Clock Enable Request for DFEV5 */ ++#define SYS2_CLKENR_DFEV5 (0x1 << 5) ++#define SYS2_CLKENR_DFEV5_VAL(val) (((val) & 0x1) << 5) ++#define SYS2_CLKENR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV5) | ((val & 0x1) << 5)) ++/* Clock Enable Request for DFEV4 */ ++#define SYS2_CLKENR_DFEV4 (0x1 << 4) ++#define SYS2_CLKENR_DFEV4_VAL(val) (((val) & 0x1) << 4) ++#define SYS2_CLKENR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV4) | ((val & 0x1) << 4)) ++/* Clock Enable Request for DFEV3 */ ++#define SYS2_CLKENR_DFEV3 (0x1 << 3) ++#define SYS2_CLKENR_DFEV3_VAL(val) (((val) & 0x1) << 3) ++#define SYS2_CLKENR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV3) | ((val & 0x1) << 3)) ++/* Clock Enable Request for DFEV2 */ ++#define SYS2_CLKENR_DFEV2 (0x1 << 2) ++#define SYS2_CLKENR_DFEV2_VAL(val) (((val) & 0x1) << 2) ++#define SYS2_CLKENR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV2) | ((val & 0x1) << 2)) ++/* Clock Enable Request for DFEV1 */ ++#define SYS2_CLKENR_DFEV1 (0x1 << 1) ++#define SYS2_CLKENR_DFEV1_VAL(val) (((val) & 0x1) << 1) ++#define SYS2_CLKENR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV1) | ((val & 0x1) << 1)) ++/* Clock Enable Request for DFEV0 */ ++#define SYS2_CLKENR_DFEV0 (0x1) ++#define SYS2_CLKENR_DFEV0_VAL(val) (((val) & 0x1)) ++#define SYS2_CLKENR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKENR_DFEV0) | ((val & 0x1))) ++ ++/******************************************************************************* ++ * SYS2 Clock Clear Register ++ ******************************************************************************/ ++ ++/* Clock Disable Request for PORT4 */ ++#define SYS2_CLKCLR_PORT4 (0x1 << 27) ++#define SYS2_CLKCLR_PORT4_VAL(val) (((val) & 0x1) << 27) ++#define SYS2_CLKCLR_PORT4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_PORT4) | ((val & 0x1) << 27)) ++/* Clock Disable Request for HWSYNC */ ++#define SYS2_CLKCLR_HWSYNC (0x1 << 26) ++#define SYS2_CLKCLR_HWSYNC_VAL(val) (((val) & 0x1) << 26) ++#define SYS2_CLKCLR_HWSYNC_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWSYNC) | ((val & 0x1) << 26)) ++/* Clock Disable Request for MBS */ ++#define SYS2_CLKCLR_MBS (0x1 << 25) ++#define SYS2_CLKCLR_MBS_VAL(val) (((val) & 0x1) << 25) ++#define SYS2_CLKCLR_MBS_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_MBS) | ((val & 0x1) << 25)) ++/* Clock Disable Request for SWINT */ ++#define SYS2_CLKCLR_SWINT (0x1 << 24) ++#define SYS2_CLKCLR_SWINT_VAL(val) (((val) & 0x1) << 24) ++#define SYS2_CLKCLR_SWINT_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SWINT) | ((val & 0x1) << 24)) ++/* Clock Disable Request for HWACC3 */ ++#define SYS2_CLKCLR_HWACC3 (0x1 << 19) ++#define SYS2_CLKCLR_HWACC3_VAL(val) (((val) & 0x1) << 19) ++#define SYS2_CLKCLR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC3) | ((val & 0x1) << 19)) ++/* Clock Disable Request for HWACC2 */ ++#define SYS2_CLKCLR_HWACC2 (0x1 << 18) ++#define SYS2_CLKCLR_HWACC2_VAL(val) (((val) & 0x1) << 18) ++#define SYS2_CLKCLR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC2) | ((val & 0x1) << 18)) ++/* Clock Disable Request for HWACC1 */ ++#define SYS2_CLKCLR_HWACC1 (0x1 << 17) ++#define SYS2_CLKCLR_HWACC1_VAL(val) (((val) & 0x1) << 17) ++#define SYS2_CLKCLR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC1) | ((val & 0x1) << 17)) ++/* Clock Disable Request for HWACC0 */ ++#define SYS2_CLKCLR_HWACC0 (0x1 << 16) ++#define SYS2_CLKCLR_HWACC0_VAL(val) (((val) & 0x1) << 16) ++#define SYS2_CLKCLR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_HWACC0) | ((val & 0x1) << 16)) ++/* Clock Disable Request for SIF7 */ ++#define SYS2_CLKCLR_SIF7 (0x1 << 15) ++#define SYS2_CLKCLR_SIF7_VAL(val) (((val) & 0x1) << 15) ++#define SYS2_CLKCLR_SIF7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF7) | ((val & 0x1) << 15)) ++/* Clock Disable Request for SIF6 */ ++#define SYS2_CLKCLR_SIF6 (0x1 << 14) ++#define SYS2_CLKCLR_SIF6_VAL(val) (((val) & 0x1) << 14) ++#define SYS2_CLKCLR_SIF6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF6) | ((val & 0x1) << 14)) ++/* Clock Disable Request for SIF5 */ ++#define SYS2_CLKCLR_SIF5 (0x1 << 13) ++#define SYS2_CLKCLR_SIF5_VAL(val) (((val) & 0x1) << 13) ++#define SYS2_CLKCLR_SIF5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF5) | ((val & 0x1) << 13)) ++/* Clock Disable Request for SIF4 */ ++#define SYS2_CLKCLR_SIF4 (0x1 << 12) ++#define SYS2_CLKCLR_SIF4_VAL(val) (((val) & 0x1) << 12) ++#define SYS2_CLKCLR_SIF4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF4) | ((val & 0x1) << 12)) ++/* Clock Disable Request for SIF3 */ ++#define SYS2_CLKCLR_SIF3 (0x1 << 11) ++#define SYS2_CLKCLR_SIF3_VAL(val) (((val) & 0x1) << 11) ++#define SYS2_CLKCLR_SIF3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF3) | ((val & 0x1) << 11)) ++/* Clock Disable Request for SIF2 */ ++#define SYS2_CLKCLR_SIF2 (0x1 << 10) ++#define SYS2_CLKCLR_SIF2_VAL(val) (((val) & 0x1) << 10) ++#define SYS2_CLKCLR_SIF2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF2) | ((val & 0x1) << 10)) ++/* Clock Disable Request for SIF1 */ ++#define SYS2_CLKCLR_SIF1 (0x1 << 9) ++#define SYS2_CLKCLR_SIF1_VAL(val) (((val) & 0x1) << 9) ++#define SYS2_CLKCLR_SIF1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF1) | ((val & 0x1) << 9)) ++/* Clock Disable Request for SIF0 */ ++#define SYS2_CLKCLR_SIF0 (0x1 << 8) ++#define SYS2_CLKCLR_SIF0_VAL(val) (((val) & 0x1) << 8) ++#define SYS2_CLKCLR_SIF0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_SIF0) | ((val & 0x1) << 8)) ++/* Clock Disable Request for DFEV7 */ ++#define SYS2_CLKCLR_DFEV7 (0x1 << 7) ++#define SYS2_CLKCLR_DFEV7_VAL(val) (((val) & 0x1) << 7) ++#define SYS2_CLKCLR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV7) | ((val & 0x1) << 7)) ++/* Clock Disable Request for DFEV6 */ ++#define SYS2_CLKCLR_DFEV6 (0x1 << 6) ++#define SYS2_CLKCLR_DFEV6_VAL(val) (((val) & 0x1) << 6) ++#define SYS2_CLKCLR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV6) | ((val & 0x1) << 6)) ++/* Clock Disable Request for DFEV5 */ ++#define SYS2_CLKCLR_DFEV5 (0x1 << 5) ++#define SYS2_CLKCLR_DFEV5_VAL(val) (((val) & 0x1) << 5) ++#define SYS2_CLKCLR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV5) | ((val & 0x1) << 5)) ++/* Clock Disable Request for DFEV4 */ ++#define SYS2_CLKCLR_DFEV4 (0x1 << 4) ++#define SYS2_CLKCLR_DFEV4_VAL(val) (((val) & 0x1) << 4) ++#define SYS2_CLKCLR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV4) | ((val & 0x1) << 4)) ++/* Clock Disable Request for DFEV3 */ ++#define SYS2_CLKCLR_DFEV3 (0x1 << 3) ++#define SYS2_CLKCLR_DFEV3_VAL(val) (((val) & 0x1) << 3) ++#define SYS2_CLKCLR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV3) | ((val & 0x1) << 3)) ++/* Clock Disable Request for DFEV2 */ ++#define SYS2_CLKCLR_DFEV2 (0x1 << 2) ++#define SYS2_CLKCLR_DFEV2_VAL(val) (((val) & 0x1) << 2) ++#define SYS2_CLKCLR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV2) | ((val & 0x1) << 2)) ++/* Clock Disable Request for DFEV1 */ ++#define SYS2_CLKCLR_DFEV1 (0x1 << 1) ++#define SYS2_CLKCLR_DFEV1_VAL(val) (((val) & 0x1) << 1) ++#define SYS2_CLKCLR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV1) | ((val & 0x1) << 1)) ++/* Clock Disable Request for DFEV0 */ ++#define SYS2_CLKCLR_DFEV0 (0x1) ++#define SYS2_CLKCLR_DFEV0_VAL(val) (((val) & 0x1)) ++#define SYS2_CLKCLR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_CLKCLR_DFEV0) | ((val & 0x1))) ++ ++/******************************************************************************* ++ * SYS2 Reset Status Register ++ ******************************************************************************/ ++ ++/* HWACC3 Reset */ ++#define SYS2_RSR_HWACC3 (0x1 << 11) ++#define SYS2_RSR_HWACC3_VAL(val) (((val) & 0x1) << 11) ++#define SYS2_RSR_HWACC3_GET(val) (((val) & SYS2_RSR_HWACC3) >> 11) ++/* HWACC2 Reset */ ++#define SYS2_RSR_HWACC2 (0x1 << 10) ++#define SYS2_RSR_HWACC2_VAL(val) (((val) & 0x1) << 10) ++#define SYS2_RSR_HWACC2_GET(val) (((val) & SYS2_RSR_HWACC2) >> 10) ++/* HWACC1 Reset */ ++#define SYS2_RSR_HWACC1 (0x1 << 9) ++#define SYS2_RSR_HWACC1_VAL(val) (((val) & 0x1) << 9) ++#define SYS2_RSR_HWACC1_GET(val) (((val) & SYS2_RSR_HWACC1) >> 9) ++/* HWACC0 Reset */ ++#define SYS2_RSR_HWACC0 (0x1 << 8) ++#define SYS2_RSR_HWACC0_VAL(val) (((val) & 0x1) << 8) ++#define SYS2_RSR_HWACC0_GET(val) (((val) & SYS2_RSR_HWACC0) >> 8) ++/* DFEV7 Reset */ ++#define SYS2_RSR_DFEV7 (0x1 << 7) ++#define SYS2_RSR_DFEV7_VAL(val) (((val) & 0x1) << 7) ++#define SYS2_RSR_DFEV7_GET(val) (((val) & SYS2_RSR_DFEV7) >> 7) ++/* DFEV6 Reset */ ++#define SYS2_RSR_DFEV6 (0x1 << 6) ++#define SYS2_RSR_DFEV6_VAL(val) (((val) & 0x1) << 6) ++#define SYS2_RSR_DFEV6_GET(val) (((val) & SYS2_RSR_DFEV6) >> 6) ++/* DFEV5 Reset */ ++#define SYS2_RSR_DFEV5 (0x1 << 5) ++#define SYS2_RSR_DFEV5_VAL(val) (((val) & 0x1) << 5) ++#define SYS2_RSR_DFEV5_GET(val) (((val) & SYS2_RSR_DFEV5) >> 5) ++/* DFEV4 Reset */ ++#define SYS2_RSR_DFEV4 (0x1 << 4) ++#define SYS2_RSR_DFEV4_VAL(val) (((val) & 0x1) << 4) ++#define SYS2_RSR_DFEV4_GET(val) (((val) & SYS2_RSR_DFEV4) >> 4) ++/* DFEV3 Reset */ ++#define SYS2_RSR_DFEV3 (0x1 << 3) ++#define SYS2_RSR_DFEV3_VAL(val) (((val) & 0x1) << 3) ++#define SYS2_RSR_DFEV3_GET(val) (((val) & SYS2_RSR_DFEV3) >> 3) ++/* DFEV2 Reset */ ++#define SYS2_RSR_DFEV2 (0x1 << 2) ++#define SYS2_RSR_DFEV2_VAL(val) (((val) & 0x1) << 2) ++#define SYS2_RSR_DFEV2_GET(val) (((val) & SYS2_RSR_DFEV2) >> 2) ++/* DFEV1 Reset */ ++#define SYS2_RSR_DFEV1 (0x1 << 1) ++#define SYS2_RSR_DFEV1_VAL(val) (((val) & 0x1) << 1) ++#define SYS2_RSR_DFEV1_GET(val) (((val) & SYS2_RSR_DFEV1) >> 1) ++/* DFEV0 Reset */ ++#define SYS2_RSR_DFEV0 (0x1) ++#define SYS2_RSR_DFEV0_VAL(val) (((val) & 0x1)) ++#define SYS2_RSR_DFEV0_GET(val) ((val) & SYS2_RSR_DFEV0) ++ ++/****************************************************************************** ++ * SYS2 Reset Request Register ++ ******************************************************************************/ ++ ++/* HWACC3 Reset Request */ ++#define SYS2_RREQR_HWACC3 (0x1 << 11) ++#define SYS2_RREQR_HWACC3_VAL(val) (((val) & 0x1) << 11) ++#define SYS2_RREQR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC3) | ((val & 0x1) << 11)) ++/* HWACC2 Reset Request */ ++#define SYS2_RREQR_HWACC2 (0x1 << 10) ++#define SYS2_RREQR_HWACC2_VAL(val) (((val) & 0x1) << 10) ++#define SYS2_RREQR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC2) | ((val & 0x1) << 10)) ++/* HWACC1 Reset Request */ ++#define SYS2_RREQR_HWACC1 (0x1 << 9) ++#define SYS2_RREQR_HWACC1_VAL(val) (((val) & 0x1) << 9) ++#define SYS2_RREQR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC1) | ((val & 0x1) << 9)) ++/* HWACC0 Reset Request */ ++#define SYS2_RREQR_HWACC0 (0x1 << 8) ++#define SYS2_RREQR_HWACC0_VAL(val) (((val) & 0x1) << 8) ++#define SYS2_RREQR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_HWACC0) | ((val & 0x1) << 8)) ++/* DFEV7 Reset Request */ ++#define SYS2_RREQR_DFEV7 (0x1 << 7) ++#define SYS2_RREQR_DFEV7_VAL(val) (((val) & 0x1) << 7) ++#define SYS2_RREQR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV7) | ((val & 0x1) << 7)) ++/* DFEV6 Reset Request */ ++#define SYS2_RREQR_DFEV6 (0x1 << 6) ++#define SYS2_RREQR_DFEV6_VAL(val) (((val) & 0x1) << 6) ++#define SYS2_RREQR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV6) | ((val & 0x1) << 6)) ++/* DFEV5 Reset Request */ ++#define SYS2_RREQR_DFEV5 (0x1 << 5) ++#define SYS2_RREQR_DFEV5_VAL(val) (((val) & 0x1) << 5) ++#define SYS2_RREQR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV5) | ((val & 0x1) << 5)) ++/* DFEV4 Reset Request */ ++#define SYS2_RREQR_DFEV4 (0x1 << 4) ++#define SYS2_RREQR_DFEV4_VAL(val) (((val) & 0x1) << 4) ++#define SYS2_RREQR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV4) | ((val & 0x1) << 4)) ++/* DFEV3 Reset Request */ ++#define SYS2_RREQR_DFEV3 (0x1 << 3) ++#define SYS2_RREQR_DFEV3_VAL(val) (((val) & 0x1) << 3) ++#define SYS2_RREQR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV3) | ((val & 0x1) << 3)) ++/* DFEV2 Reset Request */ ++#define SYS2_RREQR_DFEV2 (0x1 << 2) ++#define SYS2_RREQR_DFEV2_VAL(val) (((val) & 0x1) << 2) ++#define SYS2_RREQR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV2) | ((val & 0x1) << 2)) ++/* DFEV1 Reset Request */ ++#define SYS2_RREQR_DFEV1 (0x1 << 1) ++#define SYS2_RREQR_DFEV1_VAL(val) (((val) & 0x1) << 1) ++#define SYS2_RREQR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV1) | ((val & 0x1) << 1)) ++/* DFEV0 Reset Request */ ++#define SYS2_RREQR_DFEV0 (0x1) ++#define SYS2_RREQR_DFEV0_VAL(val) (((val) & 0x1)) ++#define SYS2_RREQR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RREQR_DFEV0) | ((val & 0x1))) ++ ++/******************************************************************************* ++ * SYS2 Reset Release Register ++ ******************************************************************************/ ++ ++/* HWACC3 Reset Release */ ++#define SYS2_RRLSR_HWACC3 (0x1 << 11) ++#define SYS2_RRLSR_HWACC3_VAL(val) (((val) & 0x1) << 11) ++#define SYS2_RRLSR_HWACC3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC3) | ((val & 0x1) << 11)) ++/* HWACC2 Reset Release */ ++#define SYS2_RRLSR_HWACC2 (0x1 << 10) ++#define SYS2_RRLSR_HWACC2_VAL(val) (((val) & 0x1) << 10) ++#define SYS2_RRLSR_HWACC2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC2) | ((val & 0x1) << 10)) ++/* HWACC1 Reset Release */ ++#define SYS2_RRLSR_HWACC1 (0x1 << 9) ++#define SYS2_RRLSR_HWACC1_VAL(val) (((val) & 0x1) << 9) ++#define SYS2_RRLSR_HWACC1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC1) | ((val & 0x1) << 9)) ++/* HWACC0 Reset Release */ ++#define SYS2_RRLSR_HWACC0 (0x1 << 8) ++#define SYS2_RRLSR_HWACC0_VAL(val) (((val) & 0x1) << 8) ++#define SYS2_RRLSR_HWACC0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_HWACC0) | ((val & 0x1) << 8)) ++/* DFEV7 Reset Release */ ++#define SYS2_RRLSR_DFEV7 (0x1 << 7) ++#define SYS2_RRLSR_DFEV7_VAL(val) (((val) & 0x1) << 7) ++#define SYS2_RRLSR_DFEV7_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV7) | ((val & 0x1) << 7)) ++/* DFEV6 Reset Release */ ++#define SYS2_RRLSR_DFEV6 (0x1 << 6) ++#define SYS2_RRLSR_DFEV6_VAL(val) (((val) & 0x1) << 6) ++#define SYS2_RRLSR_DFEV6_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV6) | ((val & 0x1) << 6)) ++/* DFEV5 Reset Release */ ++#define SYS2_RRLSR_DFEV5 (0x1 << 5) ++#define SYS2_RRLSR_DFEV5_VAL(val) (((val) & 0x1) << 5) ++#define SYS2_RRLSR_DFEV5_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV5) | ((val & 0x1) << 5)) ++/* DFEV4 Reset Release */ ++#define SYS2_RRLSR_DFEV4 (0x1 << 4) ++#define SYS2_RRLSR_DFEV4_VAL(val) (((val) & 0x1) << 4) ++#define SYS2_RRLSR_DFEV4_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV4) | ((val & 0x1) << 4)) ++/* DFEV3 Reset Release */ ++#define SYS2_RRLSR_DFEV3 (0x1 << 3) ++#define SYS2_RRLSR_DFEV3_VAL(val) (((val) & 0x1) << 3) ++#define SYS2_RRLSR_DFEV3_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV3) | ((val & 0x1) << 3)) ++/* DFEV2 Reset Release */ ++#define SYS2_RRLSR_DFEV2 (0x1 << 2) ++#define SYS2_RRLSR_DFEV2_VAL(val) (((val) & 0x1) << 2) ++#define SYS2_RRLSR_DFEV2_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV2) | ((val & 0x1) << 2)) ++/* DFEV1 Reset Release */ ++#define SYS2_RRLSR_DFEV1 (0x1 << 1) ++#define SYS2_RRLSR_DFEV1_VAL(val) (((val) & 0x1) << 1) ++#define SYS2_RRLSR_DFEV1_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV1) | ((val & 0x1) << 1)) ++/* DFEV0 Reset Release */ ++#define SYS2_RRLSR_DFEV0 (0x1) ++#define SYS2_RRLSR_DFEV0_VAL(val) (((val) & 0x1)) ++#define SYS2_RRLSR_DFEV0_SET (reg,val) (reg) = ((reg & ~SYS2_RRLSR_DFEV0) | ((val & 0x1))) ++ ++#endif /* __SYS2_H */ ++ +Index: linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/include/asm/mach-lantiq/svip/svip_pms.h 2012-07-31 15:46:02.484476159 +0200 +@@ -0,0 +1,23 @@ ++/************************************************************************ ++ * ++ * Copyright (c) 2007 ++ * Infineon Technologies AG ++ * St. Martin Strasse 53; 81669 Muenchen; Germany ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ ************************************************************************/ ++ ++#ifndef __SVIP_PMS_H ++#define __SVIP_PMS_H ++ ++void svip_sys1_clk_enable(u32 mask); ++int svip_sys1_clk_is_enabled(u32 mask); ++ ++void svip_sys2_clk_enable(u32 mask); ++int svip_sys2_clk_is_enabled(u32 mask); ++ ++#endif diff --git a/target/linux/lantiq/patches-3.3/310-svip_board.patch b/target/linux/lantiq/patches-3.3/310-svip_board.patch new file mode 100644 index 0000000000..f817c94ee9 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/310-svip_board.patch @@ -0,0 +1,7636 @@ +Index: linux-3.3.8/arch/mips/lantiq/Kconfig +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/Kconfig 2012-07-31 19:51:33.349105884 +0200 ++++ linux-3.3.8/arch/mips/lantiq/Kconfig 2012-07-31 19:51:34.133105918 +0200 +@@ -20,9 +20,14 @@ + config SOC_FALCON + bool "FALCON" + ++config SOC_SVIP ++ bool "SVIP" ++ select MIPS_CPU_SCACHE ++ + endchoice + + source "arch/mips/lantiq/xway/Kconfig" + source "arch/mips/lantiq/falcon/Kconfig" ++source "arch/mips/lantiq/svip/Kconfig" + + endif +Index: linux-3.3.8/arch/mips/lantiq/svip/Kconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/Kconfig 2012-07-31 19:51:34.133105918 +0200 +@@ -0,0 +1,16 @@ ++if SOC_SVIP ++ ++menu "Mips Machine" ++ ++config LANTIQ_MACH_EASY33016 ++ bool "Easy33016" ++ default y ++ ++config LANTIQ_MACH_EASY336 ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ bool "Easy336" ++ default y ++ ++endmenu ++ ++endif +Index: linux-3.3.8/arch/mips/lantiq/Makefile +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/Makefile 2012-07-31 19:51:34.017105912 +0200 ++++ linux-3.3.8/arch/mips/lantiq/Makefile 2012-07-31 19:51:34.133105918 +0200 +@@ -10,3 +10,4 @@ + + obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ + obj-$(CONFIG_SOC_FALCON) += falcon/ ++obj-$(CONFIG_SOC_SVIP) += svip/ +Index: linux-3.3.8/arch/mips/lantiq/svip/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/Makefile 2012-07-31 19:51:34.133105918 +0200 +@@ -0,0 +1,3 @@ ++obj-y := devices.o prom.o reset.o clk-svip.o gpio.o dma.o switchip_setup.o pms.o mux.o ++obj-$(CONFIG_LANTIQ_MACH_EASY33016) += mach-easy33016.o ++obj-$(CONFIG_LANTIQ_MACH_EASY336) += mach-easy336.o +Index: linux-3.3.8/arch/mips/lantiq/svip/devices.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/devices.c 2012-07-31 19:51:34.137105918 +0200 +@@ -0,0 +1,385 @@ ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/types.h> ++#include <linux/string.h> ++#include <linux/mtd/physmap.h> ++#include <linux/kernel.h> ++#include <linux/reboot.h> ++#include <linux/platform_device.h> ++#include <linux/leds.h> ++#include <linux/etherdevice.h> ++#include <linux/reboot.h> ++#include <linux/time.h> ++#include <linux/io.h> ++#include <linux/gpio.h> ++#include <linux/leds.h> ++#include <linux/spi/spi.h> ++#include <linux/mtd/nand.h> ++ ++#include <asm/bootinfo.h> ++#include <asm/irq.h> ++ ++#include <lantiq.h> ++ ++#include <base_reg.h> ++#include <sys1_reg.h> ++#include <sys2_reg.h> ++#include <ebu_reg.h> ++ ++#include "devices.h" ++ ++#include <lantiq_soc.h> ++#include <svip_mux.h> ++#include <svip_pms.h> ++ ++/* ASC */ ++void __init svip_register_asc(int port) ++{ ++ switch (port) { ++ case 0: ++ ltq_register_asc(0); ++ svip_sys1_clk_enable(SYS1_CLKENR_ASC0); ++ break; ++ case 1: ++ ltq_register_asc(1); ++ svip_sys1_clk_enable(SYS1_CLKENR_ASC1); ++ break; ++ default: ++ break; ++ }; ++} ++ ++/* Ethernet */ ++static unsigned char svip_ethaddr[6] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; ++ ++static struct platform_device ltq_mii = { ++ .name = "ifxmips_mii0", ++ .dev = { ++ .platform_data = svip_ethaddr, ++ }, ++}; ++ ++static int __init svip_set_ethaddr(char *str) ++{ ++ sscanf(str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &svip_ethaddr[0], &svip_ethaddr[1], &svip_ethaddr[2], ++ &svip_ethaddr[3], &svip_ethaddr[4], &svip_ethaddr[5]); ++ return 0; ++} ++__setup("ethaddr=", svip_set_ethaddr); ++ ++void __init svip_register_eth(void) ++{ ++ if (!is_valid_ether_addr(svip_ethaddr)) ++ random_ether_addr(svip_ethaddr); ++ ++ platform_device_register(<q_mii); ++ svip_sys1_clk_enable(SYS1_CLKENR_ETHSW); ++} ++ ++/* Virtual Ethernet */ ++static struct platform_device ltq_ve = { ++ .name = "ifxmips_svip_ve", ++}; ++ ++void __init svip_register_virtual_eth(void) ++{ ++ platform_device_register(<q_ve); ++} ++ ++/* SPI */ ++static void __init ltq_register_ssc(int bus_num, unsigned long base, int irq_rx, ++ int irq_tx, int irq_err, int irq_frm) ++{ ++ struct resource res[] = { ++ { ++ .name = "regs", ++ .start = base, ++ .end = base + 0x20 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .name = "rx", ++ .start = irq_rx, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .name = "tx", ++ .start = irq_tx, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .name = "err", ++ .start = irq_err, ++ .flags = IORESOURCE_IRQ, ++ }, { ++ .name = "frm", ++ .start = irq_frm, ++ .flags = IORESOURCE_IRQ, ++ }, ++ }; ++ ++ platform_device_register_simple("ifx_ssc", bus_num, res, ++ ARRAY_SIZE(res)); ++} ++ ++static struct spi_board_info bdinfo[] __initdata = { ++ { ++ .modalias = "xt16", ++ .mode = SPI_MODE_3, ++ .irq = INT_NUM_IM5_IRL0 + 28, ++ .max_speed_hz = 1000000, ++ .bus_num = 0, ++ .chip_select = 1, ++ }, ++ { ++ .modalias = "xt16", ++ .mode = SPI_MODE_3, ++ .irq = INT_NUM_IM5_IRL0 + 19, ++ .max_speed_hz = 1000000, ++ .bus_num = 0, ++ .chip_select = 2, ++ }, ++ { ++ .modalias = "loop", ++ .mode = SPI_MODE_0 | SPI_LOOP, ++ .irq = -1, ++ .max_speed_hz = 10000000, ++ .bus_num = 0, ++ .chip_select = 3, ++ }, ++}; ++ ++void __init svip_register_spi(void) ++{ ++ ++ ltq_register_ssc(0, LTQ_SSC0_BASE, INT_NUM_IM1_IRL0 + 6, ++ INT_NUM_IM1_IRL0 + 7, INT_NUM_IM1_IRL0 + 8, ++ INT_NUM_IM1_IRL0 + 9); ++ ++ ltq_register_ssc(1, LTQ_SSC1_BASE, INT_NUM_IM1_IRL0 + 10, ++ INT_NUM_IM1_IRL0 + 11, INT_NUM_IM1_IRL0 + 12, ++ INT_NUM_IM1_IRL0 + 13); ++ ++ spi_register_board_info(bdinfo, ARRAY_SIZE(bdinfo)); ++ ++ svip_sys1_clk_enable(SYS1_CLKENR_SSC0 | SYS1_CLKENR_SSC1); ++} ++ ++void __init svip_register_spi_flash(struct spi_board_info *bdinfo) ++{ ++ spi_register_board_info(bdinfo, 1); ++} ++ ++/* GPIO */ ++static struct platform_device ltq_gpio = { ++ .name = "ifxmips_gpio", ++}; ++ ++static struct platform_device ltq_gpiodev = { ++ .name = "GPIODEV", ++}; ++ ++void __init svip_register_gpio(void) ++{ ++ platform_device_register(<q_gpio); ++ platform_device_register(<q_gpiodev); ++} ++ ++/* MUX */ ++static struct ltq_mux_settings ltq_mux_settings; ++ ++static struct platform_device ltq_mux = { ++ .name = "ltq_mux", ++ .dev = { ++ .platform_data = <q_mux_settings, ++ } ++}; ++ ++void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], ++ const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], ++ const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], ++ const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], ++ const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]) ++{ ++ ltq_mux_settings.mux_p0 = mux_p0; ++ ltq_mux_settings.mux_p1 = mux_p1; ++ ltq_mux_settings.mux_p2 = mux_p2; ++ ltq_mux_settings.mux_p3 = mux_p3; ++ ltq_mux_settings.mux_p4 = mux_p4; ++ ++ if (mux_p0) ++ svip_sys1_clk_enable(SYS1_CLKENR_PORT0); ++ ++ if (mux_p1) ++ svip_sys1_clk_enable(SYS1_CLKENR_PORT1); ++ ++ if (mux_p2) ++ svip_sys1_clk_enable(SYS1_CLKENR_PORT2); ++ ++ if (mux_p3) ++ svip_sys1_clk_enable(SYS1_CLKENR_PORT3); ++ ++ if (mux_p4) ++ svip_sys2_clk_enable(SYS2_CLKENR_PORT4); ++ ++ platform_device_register(<q_mux); ++} ++ ++/* NAND */ ++#define NAND_ADDR_REGION_BASE (LTQ_EBU_SEG1_BASE) ++#define NAND_CLE_BIT (1 << 3) ++#define NAND_ALE_BIT (1 << 2) ++ ++static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; ++ ++static int svip_nand_probe(struct platform_device *pdev) ++{ ++ ebu_w32(LTQ_EBU_ADDR_SEL_0_BASE_VAL(CPHYSADDR(NAND_ADDR_REGION_BASE) ++ >> 12) ++ | LTQ_EBU_ADDR_SEL_0_MASK_VAL(15) ++ | LTQ_EBU_ADDR_SEL_0_MRME_VAL(0) ++ | LTQ_EBU_ADDR_SEL_0_REGEN_VAL(1), ++ addr_sel_0); ++ ++ ebu_w32(LTQ_EBU_CON_0_WRDIS_VAL(0) ++ | LTQ_EBU_CON_0_ADSWP_VAL(1) ++ | LTQ_EBU_CON_0_AGEN_VAL(0x00) ++ | LTQ_EBU_CON_0_SETUP_VAL(1) ++ | LTQ_EBU_CON_0_WAIT_VAL(0x00) ++ | LTQ_EBU_CON_0_WINV_VAL(0) ++ | LTQ_EBU_CON_0_PW_VAL(0x00) ++ | LTQ_EBU_CON_0_ALEC_VAL(0) ++ | LTQ_EBU_CON_0_BCGEN_VAL(0x01) ++ | LTQ_EBU_CON_0_WAITWRC_VAL(1) ++ | LTQ_EBU_CON_0_WAITRDC_VAL(1) ++ | LTQ_EBU_CON_0_HOLDC_VAL(1) ++ | LTQ_EBU_CON_0_RECOVC_VAL(0) ++ | LTQ_EBU_CON_0_CMULT_VAL(0x01), ++ con_0); ++ ++ /* ++ * ECC disabled ++ * CLE, ALE and CS are pulse, all other signal are latches based ++ * CLE and ALE are active high, PRE, WP, SE and CS/CE are active low ++ * OUT_CS_S is disabled ++ * NAND mode is disabled ++ */ ++ ebu_w32(LTQ_EBU_NAND_CON_ECC_ON_VAL(0) ++ | LTQ_EBU_NAND_CON_LAT_EN_VAL(0x38) ++ | LTQ_EBU_NAND_CON_OUT_CS_S_VAL(0) ++ | LTQ_EBU_NAND_CON_IN_CS_S_VAL(0) ++ | LTQ_EBU_NAND_CON_PRE_P_VAL(1) ++ | LTQ_EBU_NAND_CON_WP_P_VAL(1) ++ | LTQ_EBU_NAND_CON_SE_P_VAL(1) ++ | LTQ_EBU_NAND_CON_CS_P_VAL(1) ++ | LTQ_EBU_NAND_CON_CLE_P_VAL(0) ++ | LTQ_EBU_NAND_CON_ALE_P_VAL(0) ++ | LTQ_EBU_NAND_CON_CSMUX_E_VAL(0) ++ | LTQ_EBU_NAND_CON_NANDMODE_VAL(0), ++ nand_con); ++ ++ return 0; ++} ++ ++static void svip_nand_hwcontrol(struct mtd_info *mtd, int cmd, ++ unsigned int ctrl) ++{ ++ struct nand_chip *this = mtd->priv; ++ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ unsigned long adr; ++ /* Coming here means to change either the enable state or ++ * the address for controlling ALE or CLE */ ++ ++ /* NAND_NCE: Select the chip by setting nCE to low. ++ * This is done in CON register */ ++ if (ctrl & NAND_NCE) ++ ebu_w32_mask(0, LTQ_EBU_NAND_CON_NANDMODE_VAL(1), ++ nand_con); ++ else ++ ebu_w32_mask(LTQ_EBU_NAND_CON_NANDMODE_VAL(1), ++ 0, nand_con); ++ ++ /* The addressing of CLE or ALE is done via different addresses. ++ We are now changing the address depending on the given action ++ SVIPs NAND_CLE_BIT = (1 << 3), NAND_CLE = 0x02 ++ NAND_ALE_BIT = (1 << 2) = NAND_ALE (0x04) */ ++ adr = (unsigned long)this->IO_ADDR_W; ++ adr &= ~(NAND_CLE_BIT | NAND_ALE_BIT); ++ adr |= (ctrl & NAND_CLE) << 2 | (ctrl & NAND_ALE); ++ this->IO_ADDR_W = (void __iomem *)adr; ++ } ++ ++ if (cmd != NAND_CMD_NONE) ++ writeb(cmd, this->IO_ADDR_W); ++} ++ ++static int svip_nand_ready(struct mtd_info *mtd) ++{ ++ return (ebu_r32(nand_wait) & 0x01) == 0x01; ++} ++ ++static inline void svip_nand_wait(void) ++{ ++ static const int nops = 150; ++ int i; ++ ++ for (i = 0; i < nops; i++) ++ asm("nop"); ++} ++ ++static void svip_nand_write_buf(struct mtd_info *mtd, ++ const u_char *buf, int len) ++{ ++ int i; ++ struct nand_chip *this = mtd->priv; ++ ++ for (i = 0; i < len; i++) { ++ writeb(buf[i], this->IO_ADDR_W); ++ svip_nand_wait(); ++ } ++} ++ ++static void svip_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) ++{ ++ int i; ++ struct nand_chip *this = mtd->priv; ++ ++ for (i = 0; i < len; i++) { ++ buf[i] = readb(this->IO_ADDR_R); ++ svip_nand_wait(); ++ } ++} ++ ++static const char *part_probes[] = { "cmdlinepart", NULL }; ++ ++static struct platform_nand_data svip_flash_nand_data = { ++ .chip = { ++ .nr_chips = 1, ++ .part_probe_types = part_probes, ++ }, ++ .ctrl = { ++ .probe = svip_nand_probe, ++ .cmd_ctrl = svip_nand_hwcontrol, ++ .dev_ready = svip_nand_ready, ++ .write_buf = svip_nand_write_buf, ++ .read_buf = svip_nand_read_buf, ++ } ++}; ++ ++static struct resource svip_nand_resources[] = { ++ MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX), ++}; ++ ++static struct platform_device svip_flash_nand = { ++ .name = "gen_nand", ++ .id = -1, ++ .num_resources = ARRAY_SIZE(svip_nand_resources), ++ .resource = svip_nand_resources, ++ .dev = { ++ .platform_data = &svip_flash_nand_data, ++ }, ++}; ++ ++void __init svip_register_nand(void) ++{ ++ platform_device_register(&svip_flash_nand); ++} +Index: linux-3.3.8/arch/mips/lantiq/svip/clk-svip.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/clk-svip.c 2012-07-31 19:51:34.137105918 +0200 +@@ -0,0 +1,100 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/io.h> ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/time.h> ++ ++#include <asm/irq.h> ++#include <asm/div64.h> ++ ++#include <lantiq_soc.h> ++#include <base_reg.h> ++#include <sys0_reg.h> ++#include <sys1_reg.h> ++#include <status_reg.h> ++ ++static struct svip_reg_status *const status = ++(struct svip_reg_status *)LTQ_STATUS_BASE; ++static struct svip_reg_sys0 *const sys0 = (struct svip_reg_sys0 *)LTQ_SYS0_BASE; ++static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; ++ ++unsigned int ltq_svip_io_region_clock(void) ++{ ++ return 200000000; /* 200 MHz */ ++} ++EXPORT_SYMBOL(ltq_svip_io_region_clock); ++ ++unsigned int ltq_svip_cpu_hz(void) ++{ ++ /* Magic BootROM speed location... */ ++ if ((*(u32 *)0x9fc07ff0) == 1) ++ return *(u32 *)0x9fc07ff4; ++ ++ if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { ++ /* xT16 */ ++ return 393216000; ++ } else { ++ switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { ++ case 3: ++ return 475000000; ++ case 2: ++ return 450000000; ++ case 1: ++ return 425000000; ++ default: ++ return 400000000; ++ } ++ } ++} ++EXPORT_SYMBOL(ltq_svip_cpu_hz); ++ ++unsigned int ltq_svip_fpi_hz(void) ++{ ++ u32 fbs0_div[2] = {4, 8}; ++ u32 div; ++ ++ div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); ++ return ltq_svip_cpu_hz()/fbs0_div[div]; ++} ++EXPORT_SYMBOL(ltq_svip_fpi_hz); ++ ++unsigned int ltq_get_ppl_hz(void) ++{ ++ /* Magic BootROM speed location... */ ++ if ((*(u32 *)0x9fc07ff0) == 1) ++ return *(u32 *)0x9fc07ff4; ++ ++ if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) { ++ /* xT16 */ ++ return 393216000; ++ } else { ++ switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) { ++ case 3: ++ return 475000000; ++ case 2: ++ return 450000000; ++ case 1: ++ return 425000000; ++ default: ++ return 400000000; ++ } ++ } ++} ++ ++unsigned int ltq_get_fbs0_hz(void) ++{ ++ u32 fbs0_div[2] = {4, 8}; ++ u32 div; ++ ++ div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr)); ++ return ltq_get_ppl_hz()/fbs0_div[div]; ++} ++EXPORT_SYMBOL(ltq_get_fbs0_hz); +Index: linux-3.3.8/arch/mips/lantiq/svip/gpio.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/gpio.c 2012-07-31 19:51:34.137105918 +0200 +@@ -0,0 +1,553 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/slab.h> ++#include <linux/gpio.h> ++#include <linux/ioport.h> ++#include <linux/io.h> ++#include <linux/types.h> ++#include <linux/errno.h> ++#include <linux/proc_fs.h> ++#include <linux/init.h> ++#include <linux/ioctl.h> ++#include <linux/timer.h> ++#include <linux/interrupt.h> ++#include <linux/kobject.h> ++#include <linux/workqueue.h> ++#include <linux/skbuff.h> ++#include <linux/netlink.h> ++#include <linux/platform_device.h> ++#include <net/sock.h> ++#include <linux/uaccess.h> ++#include <linux/version.h> ++#include <linux/semaphore.h> ++ ++#include <lantiq_soc.h> ++#include <svip_mux.h> ++#include <base_reg.h> ++#include <port_reg.h> ++ ++#define DRV_NAME "ifxmips_gpio" ++ ++int gpio_to_irq(unsigned int gpio) ++{ ++ return -EINVAL; ++} ++EXPORT_SYMBOL(gpio_to_irq); ++ ++int irq_to_gpio(unsigned int gpio) ++{ ++ return -EINVAL; ++} ++EXPORT_SYMBOL(irq_to_gpio); ++ ++struct ltq_port_base { ++ struct svip_reg_port *base; ++ u32 pins; ++}; ++ ++/* Base addresses for ports */ ++static const struct ltq_port_base ltq_port_base[] = { ++ { (struct svip_reg_port *)LTQ_PORT_P0_BASE, 20 }, ++ { (struct svip_reg_port *)LTQ_PORT_P1_BASE, 20 }, ++ { (struct svip_reg_port *)LTQ_PORT_P2_BASE, 19 }, ++ { (struct svip_reg_port *)LTQ_PORT_P3_BASE, 20 }, ++ { (struct svip_reg_port *)LTQ_PORT_P4_BASE, 24 } ++}; ++ ++#define MAX_PORTS ARRAY_SIZE(ltq_port_base) ++#define PINS_PER_PORT(port) (ltq_port_base[port].pins) ++ ++static inline ++void ltq_port_set_exintcr0(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->exintcr0) | (1 << pin), ++ ltq_port_base[port].base->exintcr0); ++} ++ ++static inline ++void ltq_port_clear_exintcr0(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->exintcr0) & ~(1 << pin), ++ ltq_port_base[port].base->exintcr0); ++} ++ ++static inline ++void ltq_port_set_exintcr1(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->exintcr1) | (1 << pin), ++ ltq_port_base[port].base->exintcr1); ++} ++ ++static inline ++void ltq_port_clear_exintcr1(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->exintcr1) & ~(1 << pin), ++ ltq_port_base[port].base->exintcr1); ++} ++ ++static inline ++void ltq_port_set_irncfg(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->irncfg) | (1 << pin), ++ ltq_port_base[port].base->irncfg); ++} ++ ++static inline ++void ltq_port_clear_irncfg(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->irncfg) & ~(1 << pin), ++ ltq_port_base[port].base->irncfg); ++} ++ ++static inline ++void ltq_port_set_irnen(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(1 << pin, ltq_port_base[port].base->irnenset); ++} ++ ++static inline ++void ltq_port_clear_irnen(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(1 << pin, ltq_port_base[port].base->irnenclr); ++} ++ ++static inline ++void ltq_port_set_dir_out(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->dir) | (1 << pin), ++ ltq_port_base[port].base->dir); ++} ++ ++static inline ++void ltq_port_set_dir_in(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->dir) & ~(1 << pin), ++ ltq_port_base[port].base->dir); ++} ++ ++static inline ++void ltq_port_set_output(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->out) | (1 << pin), ++ ltq_port_base[port].base->out); ++} ++ ++static inline ++void ltq_port_clear_output(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->out) & ~(1 << pin), ++ ltq_port_base[port].base->out); ++} ++ ++static inline ++int ltq_port_get_input(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return -EINVAL; ++ ++ return (port_r32(ltq_port_base[port].base->in) & (1 << pin)) == 0; ++} ++ ++static inline ++void ltq_port_set_puen(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->puen) | (1 << pin), ++ ltq_port_base[port].base->puen); ++} ++ ++static inline ++void ltq_port_clear_puen(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->puen) & ~(1 << pin), ++ ltq_port_base[port].base->puen); ++} ++ ++static inline ++void ltq_port_set_altsel0(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->altsel0) | (1 << pin), ++ ltq_port_base[port].base->altsel0); ++} ++ ++static inline ++void ltq_port_clear_altsel0(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->altsel0) & ~(1 << pin), ++ ltq_port_base[port].base->altsel0); ++} ++ ++static inline ++void ltq_port_set_altsel1(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->altsel1) | (1 << pin), ++ ltq_port_base[port].base->altsel1); ++} ++ ++static inline ++void ltq_port_clear_altsel1(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return; ++ ++ port_w32(port_r32(ltq_port_base[port].base->altsel1) & ~(1 << pin), ++ ltq_port_base[port].base->altsel1); ++} ++ ++void ltq_gpio_configure(int port, int pin, bool dirin, bool puen, ++ bool altsel0, bool altsel1) ++{ ++ if (dirin) ++ ltq_port_set_dir_in(port, pin); ++ else ++ ltq_port_set_dir_out(port, pin); ++ ++ if (puen) ++ ltq_port_set_puen(port, pin); ++ else ++ ltq_port_clear_puen(port, pin); ++ ++ if (altsel0) ++ ltq_port_set_altsel0(port, pin); ++ else ++ ltq_port_clear_altsel0(port, pin); ++ ++ if (altsel1) ++ ltq_port_set_altsel1(port, pin); ++ else ++ ltq_port_clear_altsel1(port, pin); ++} ++ ++int ltq_port_get_dir(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return -EINVAL; ++ ++ return (port_r32(ltq_port_base[port].base->dir) & (1 << pin)) != 0; ++} ++ ++int ltq_port_get_puden(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return -EINVAL; ++ ++ return (port_r32(ltq_port_base[port].base->puen) & (1 << pin)) != 0; ++} ++ ++int ltq_port_get_altsel0(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return -EINVAL; ++ ++ return (port_r32(ltq_port_base[port].base->altsel0) & (1 << pin)) != 0; ++} ++ ++int ltq_port_get_altsel1(unsigned int port, unsigned int pin) ++{ ++ if (port >= MAX_PORTS || pin >= PINS_PER_PORT(port)) ++ return -EINVAL; ++ ++ return (port_r32(ltq_port_base[port].base->altsel1) & (1 << pin)) != 0; ++} ++ ++struct ltq_gpio_port { ++ struct gpio_chip gpio_chip; ++ unsigned int irq_base; ++ unsigned int chained_irq; ++}; ++ ++static struct ltq_gpio_port ltq_gpio_port[MAX_PORTS]; ++ ++static int gpio_exported; ++static int __init gpio_export_setup(char *str) ++{ ++ get_option(&str, &gpio_exported); ++ return 1; ++} ++__setup("gpio_exported=", gpio_export_setup); ++ ++static inline unsigned int offset2port(unsigned int offset) ++{ ++ unsigned int i; ++ unsigned int prev = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { ++ if (offset >= prev && ++ offset < prev + ltq_port_base[i].pins) ++ return i; ++ ++ prev = ltq_port_base[i].pins; ++ } ++ ++ return 0; ++} ++ ++static inline unsigned int offset2pin(unsigned int offset) ++{ ++ unsigned int i; ++ unsigned int prev = 0; ++ ++ for (i = 0; i < ARRAY_SIZE(ltq_port_base); i++) { ++ if (offset >= prev && ++ offset < prev + ltq_port_base[i].pins) ++ return offset - prev; ++ ++ prev = ltq_port_base[i].pins; ++ } ++ ++ return 0; ++} ++ ++static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) ++{ ++ ltq_port_set_dir_in(offset2port(offset), offset2pin(offset)); ++ return 0; ++} ++ ++static int ltq_gpio_direction_output(struct gpio_chip *chip, ++ unsigned int offset, int value) ++{ ++ ltq_port_set_dir_out(offset2port(offset), offset2pin(offset)); ++ return 0; ++} ++ ++static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset) ++{ ++ return ltq_port_get_input(offset2port(offset), offset2pin(offset)); ++} ++ ++static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) ++{ ++ if (value) ++ ltq_port_set_output(offset2port(offset), offset2pin(offset)); ++ else ++ ltq_port_clear_output(offset2port(offset), offset2pin(offset)); ++} ++ ++static int svip_gpio_request(struct gpio_chip *chip, unsigned offset) ++{ ++ return 0; ++} ++ ++static void ltq_gpio_free(struct gpio_chip *chip, unsigned offset) ++{ ++} ++ ++static int ltq_gpio_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ struct ltq_gpio_port *gpio_port; ++ ++ if (pdev->id >= MAX_PORTS) ++ return -ENODEV; ++ ++ gpio_port = <q_gpio_port[pdev->id]; ++ gpio_port->gpio_chip.label = "ltq-gpio"; ++ ++ gpio_port->gpio_chip.direction_input = ltq_gpio_direction_input; ++ gpio_port->gpio_chip.direction_output = ltq_gpio_direction_output; ++ gpio_port->gpio_chip.get = ltq_gpio_get; ++ gpio_port->gpio_chip.set = ltq_gpio_set; ++ gpio_port->gpio_chip.request = svip_gpio_request; ++ gpio_port->gpio_chip.free = ltq_gpio_free; ++ gpio_port->gpio_chip.base = 100 * pdev->id; ++ gpio_port->gpio_chip.ngpio = 32; ++ gpio_port->gpio_chip.dev = &pdev->dev; ++ gpio_port->gpio_chip.exported = gpio_exported; ++ ++ ret = gpiochip_add(&gpio_port->gpio_chip); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", ++ pdev->id, ret); ++ goto err; ++ } ++ platform_set_drvdata(pdev, gpio_port); ++ ++ return 0; ++ ++err: ++ return ret; ++} ++ ++static int ltq_gpio_remove(struct platform_device *pdev) ++{ ++ struct ltq_gpio_port *gpio_port = platform_get_drvdata(pdev); ++ int ret; ++ ++ ret = gpiochip_remove(&gpio_port->gpio_chip); ++ ++ return ret; ++} ++ ++static struct platform_driver ltq_gpio_driver = { ++ .probe = ltq_gpio_probe, ++ .remove = __devexit_p(ltq_gpio_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int __init ltq_gpio_init(void) ++{ ++ int ret = platform_driver_register(<q_gpio_driver); ++ if (ret) ++ printk(KERN_INFO DRV_NAME ++ ": Error registering platform driver!"); ++ return ret; ++} ++ ++postcore_initcall(ltq_gpio_init); ++ ++/** ++ * Convert interrupt number to corresponding port/pin pair ++ * Returns the port/pin pair serving the selected external interrupt; ++ * needed since mapping not linear. ++ * ++ * \param exint External interrupt number ++ * \param port Pointer for resulting port ++ * \param pin Pointer for resutling pin ++ * \return -EINVAL Invalid exint ++ * \return 0 port/pin updated ++ * \ingroup API ++ */ ++static int ltq_exint2port(u32 exint, int *port, int *pin) ++{ ++ if ((exint >= 0) && (exint <= 10)) { ++ *port = 0; ++ *pin = exint + 7; ++ } else if ((exint >= 11) && (exint <= 14)) { ++ *port = 1; ++ *pin = 18 - (exint - 11) ; ++ } else if (exint == 15) { ++ *port = 1; ++ *pin = 19; ++ } else if (exint == 16) { ++ *port = 0; ++ *pin = 19; ++ } else { ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++/** ++ * Enable external interrupt. ++ * This function enables an external interrupt and sets the given mode. ++ * valid values for mode are: ++ * - 0 = Interrupt generation disabled ++ * - 1 = Interrupt on rising edge ++ * - 2 = Interrupt on falling edge ++ * - 3 = Interrupt on rising and falling edge ++ * - 5 = Interrupt on high level detection ++ * - 6 = Interrupt on low level detection ++ * ++ * \param exint - Number of external interrupt ++ * \param mode - Trigger mode ++ * \return 0 on success ++ * \ingroup API ++ */ ++int ifx_enable_external_int(u32 exint, u32 mode) ++{ ++ int port; ++ int pin; ++ ++ if ((mode < 0) || (mode > 6)) ++ return -EINVAL; ++ ++ if (ltq_exint2port(exint, &port, &pin)) ++ return -EINVAL; ++ ++ ltq_port_clear_exintcr0(port, pin); ++ ltq_port_clear_exintcr1(port, pin); ++ ltq_port_clear_irncfg(port, pin); ++ ++ if (mode & 0x1) ++ ltq_port_set_exintcr0(port, pin); ++ if (mode & 0x2) ++ ltq_port_set_exintcr1(port, pin); ++ if (mode & 0x4) ++ ltq_port_set_irncfg(port, pin); ++ ++ ltq_port_set_irnen(port, pin); ++ return 0; ++} ++EXPORT_SYMBOL(ifx_enable_external_int); ++ ++/** ++ * Disable external interrupt. ++ * This function disables an external interrupt and sets mode to 0x00. ++ * ++ * \param exint - Number of external interrupt ++ * \return 0 on success ++ * \ingroup API ++ */ ++int ifx_disable_external_int(u32 exint) ++{ ++ int port; ++ int pin; ++ ++ if (ltq_exint2port(exint, &port, &pin)) ++ return -EINVAL; ++ ++ ltq_port_clear_irnen(port, pin); ++ return 0; ++} ++EXPORT_SYMBOL(ifx_disable_external_int); +Index: linux-3.3.8/arch/mips/lantiq/svip/prom.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/prom.c 2012-07-31 19:51:34.137105918 +0200 +@@ -0,0 +1,73 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/clk.h> ++#include <linux/time.h> ++#include <asm/bootinfo.h> ++ ++#include <lantiq_soc.h> ++ ++#include "../prom.h" ++#include "../clk.h" ++#include "../machtypes.h" ++ ++#include <base_reg.h> ++#include <ebu_reg.h> ++ ++#define SOC_SVIP "SVIP" ++ ++#define PART_SHIFT 12 ++#define PART_MASK 0x0FFFF000 ++#define REV_SHIFT 28 ++#define REV_MASK 0xF0000000 ++ ++static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; ++ ++void __init ltq_soc_init(void) ++{ ++ clkdev_add_static(ltq_svip_cpu_hz(), ltq_svip_fpi_hz(), ++ ltq_svip_io_region_clock()); ++} ++ ++void __init ++ltq_soc_setup(void) ++{ ++ if (mips_machtype == LANTIQ_MACH_EASY33016 || ++ mips_machtype == LANTIQ_MACH_EASY336) { ++ ebu_w32(0x120000f1, addr_sel_2); ++ ebu_w32(LTQ_EBU_CON_0_ADSWP | ++ LTQ_EBU_CON_0_SETUP | ++ LTQ_EBU_CON_0_BCGEN_VAL(0x02) | ++ LTQ_EBU_CON_0_WAITWRC_VAL(7) | ++ LTQ_EBU_CON_0_WAITRDC_VAL(3) | ++ LTQ_EBU_CON_0_HOLDC_VAL(3) | ++ LTQ_EBU_CON_0_RECOVC_VAL(3) | ++ LTQ_EBU_CON_0_CMULT_VAL(3), con_2); ++ } ++} ++ ++void __init ++ltq_soc_detect(struct ltq_soc_info *i) ++{ ++ i->partnum = (ltq_r32(LTQ_STATUS_CHIPID) & PART_MASK) >> PART_SHIFT; ++ i->rev = (ltq_r32(LTQ_STATUS_CHIPID) & REV_MASK) >> REV_SHIFT; ++ sprintf(i->rev_type, "1.%d", i->rev); ++ switch (i->partnum) { ++ case SOC_ID_SVIP: ++ i->name = SOC_SVIP; ++ i->type = SOC_TYPE_SVIP; ++ break; ++ ++ default: ++ printk(KERN_ERR "unknown partnum : 0x%08X\n", i->partnum); ++ while (1); ++ break; ++ } ++} +Index: linux-3.3.8/arch/mips/lantiq/svip/reset.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/reset.c 2012-07-31 19:51:34.137105918 +0200 +@@ -0,0 +1,95 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/ioport.h> ++#include <linux/pm.h> ++#include <linux/module.h> ++#include <asm/reboot.h> ++ ++#include <lantiq_soc.h> ++#include "../machtypes.h" ++#include <base_reg.h> ++#include <sys1_reg.h> ++#include <boot_reg.h> ++#include <ebu_reg.h> ++ ++static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; ++static struct svip_reg_ebu *const ebu = (struct svip_reg_ebu *)LTQ_EBU_BASE; ++ ++#define CPLD_CMDREG3 ((volatile unsigned char*)(KSEG1 + 0x120000f3)) ++extern void switchip_reset(void); ++ ++static void ltq_machine_restart(char *command) ++{ ++ printk(KERN_NOTICE "System restart\n"); ++ local_irq_disable(); ++ ++ if (mips_machtype == LANTIQ_MACH_EASY33016 || ++ mips_machtype == LANTIQ_MACH_EASY336) { ++ /* We just use the CPLD function to reset the entire system as a ++ workaround for the switch reset problem */ ++ local_irq_disable(); ++ ebu_w32(0x120000f1, addr_sel_2); ++ ebu_w32(0x404027ff, con_2); ++ ++ if (mips_machtype == LANTIQ_MACH_EASY336) ++ /* set bit 0 to reset SVIP */ ++ *CPLD_CMDREG3 = (1<<0); ++ else ++ /* set bit 7 to reset SVIP, set bit 3 to reset xT */ ++ *CPLD_CMDREG3 = (1<<7) | (1<<3); ++ } else { ++ *LTQ_BOOT_RVEC(0) = 0; ++ /* reset all except PER, SUBSYS and CPU0 */ ++ sys1_w32(0x00043F3E, rreqr); ++ /* release WDT0 reset */ ++ sys1_w32(0x00000100, rrlsr); ++ /* restore reset value for clock enables */ ++ sys1_w32(~0x0c000040, clkclr); ++ /* reset SUBSYS (incl. DDR2) and CPU0 */ ++ sys1_w32(0x00030001, rbtr); ++ } ++ ++ for (;;) ++ ; ++} ++ ++static void ltq_machine_halt(void) ++{ ++ printk(KERN_NOTICE "System halted.\n"); ++ local_irq_disable(); ++ for (;;) ++ ; ++} ++ ++static void ltq_machine_power_off(void) ++{ ++ printk(KERN_NOTICE "Please turn off the power now.\n"); ++ local_irq_disable(); ++ for (;;) ++ ; ++} ++ ++/* This function is used by the watchdog driver */ ++int ltq_reset_cause(void) ++{ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(ltq_reset_cause); ++ ++static int __init mips_reboot_setup(void) ++{ ++ _machine_restart = ltq_machine_restart; ++ _machine_halt = ltq_machine_halt; ++ pm_power_off = ltq_machine_power_off; ++ return 0; ++} ++ ++arch_initcall(mips_reboot_setup); +Index: linux-3.3.8/arch/mips/lantiq/machtypes.h +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/machtypes.h 2012-07-31 19:51:33.989105912 +0200 ++++ linux-3.3.8/arch/mips/lantiq/machtypes.h 2012-07-31 19:51:34.137105918 +0200 +@@ -16,6 +16,12 @@ + LTQ_MACH_EASY50712, /* Danube evaluation board */ + LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ + ++ /* SVIP */ ++ LANTIQ_MACH_EASY33016, /* SVIP Easy33016 */ ++ LANTIQ_MACH_EASY336, /* SVIP Easy336, NOR Flash */ ++ LANTIQ_MACH_EASY336SF, /* SVIP Easy336, Serial Flash */ ++ LANTIQ_MACH_EASY336NAND, /* SVIP Easy336, NAND Flash */ ++ + /* FALCON */ + LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ + LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ +Index: linux-3.3.8/arch/mips/lantiq/svip/mach-easy33016.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/mach-easy33016.c 2012-07-31 19:51:34.137105918 +0200 +@@ -0,0 +1,73 @@ ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/leds.h> ++#include <linux/gpio.h> ++#include <linux/gpio_buttons.h> ++#include <linux/mtd/mtd.h> ++#include <linux/mtd/partitions.h> ++#include <linux/input.h> ++#include <linux/interrupt.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/flash.h> ++#include "../machtypes.h" ++ ++#include <sys1_reg.h> ++#include <sys2_reg.h> ++#include <svip_pms.h> ++ ++#include "devices.h" ++ ++static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { ++ LTQ_MUX_P0_0_SSC0_MTSR, ++ LTQ_MUX_P0_1_SSC0_MRST, ++ LTQ_MUX_P0_2_SSC0_SCLK, ++ LTQ_MUX_P0_3_SSC1_MTSR, ++ LTQ_MUX_P0_4_SSC1_MRST, ++ LTQ_MUX_P0_5_SSC1_SCLK, ++ LTQ_MUX_P0_6_SSC0_CS0, ++ LTQ_MUX_P0_7_SSC0_CS1, ++ LTQ_MUX_P0_8_SSC0_CS2, ++ LTQ_MUX_P0_9, ++ LTQ_MUX_P0_10, ++ LTQ_MUX_P0_11_EXINT4, ++ LTQ_MUX_P0_12, ++ LTQ_MUX_P0_13, ++ LTQ_MUX_P0_14_ASC0_TXD, ++ LTQ_MUX_P0_15_ASC0_RXD, ++ LTQ_MUX_P0_16_EXINT9, ++ LTQ_MUX_P0_17_EXINT10, ++ LTQ_MUX_P0_18_EJ_BRKIN, ++ LTQ_MUX_P0_19_EXINT16 ++}; ++ ++static void __init easy33016_init(void) ++{ ++ svip_sys1_clk_enable(SYS1_CLKENR_L2C | ++ SYS1_CLKENR_DDR2 | ++ SYS1_CLKENR_SMI2 | ++ SYS1_CLKENR_SMI1 | ++ SYS1_CLKENR_SMI0 | ++ SYS1_CLKENR_FMI0 | ++ SYS1_CLKENR_DMA | ++ SYS1_CLKENR_SSC0 | ++ SYS1_CLKENR_SSC1 | ++ SYS1_CLKENR_EBU); ++ ++ svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | ++ SYS2_CLKENR_MBS | ++ SYS2_CLKENR_SWINT); ++ ++ svip_register_mux(mux_p0, NULL, NULL, NULL, NULL); ++ svip_register_asc(0); ++ svip_register_eth(); ++ svip_register_virtual_eth(); ++ ltq_register_wdt(); ++ svip_register_gpio(); ++ svip_register_spi(); ++ svip_register_nand(); ++} ++ ++MIPS_MACHINE(LANTIQ_MACH_EASY33016, ++ "EASY33016", ++ "EASY33016", ++ easy33016_init); +Index: linux-3.3.8/arch/mips/lantiq/svip/mach-easy336.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/mach-easy336.c 2012-07-31 19:51:34.141105918 +0200 +@@ -0,0 +1,221 @@ ++#include <linux/init.h> ++#include <linux/platform_device.h> ++#include <linux/leds.h> ++#include <linux/gpio.h> ++#include <linux/gpio_buttons.h> ++#include <linux/mtd/mtd.h> ++#include <linux/mtd/partitions.h> ++#include <linux/input.h> ++#include <linux/interrupt.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/flash.h> ++#include "../machtypes.h" ++ ++#include <sys1_reg.h> ++#include <sys2_reg.h> ++#include <svip_pms.h> ++ ++#include "devices.h" ++ ++static struct mtd_partition easy336_sflash_partitions[] = { ++ { ++ .name = "SPI flash", ++ .size = MTDPART_SIZ_FULL, ++ .offset = 0, ++ }, ++}; ++ ++static struct flash_platform_data easy336_sflash_data = { ++ .name = "m25p32", ++ .parts = (void *)&easy336_sflash_partitions, ++ .nr_parts = ARRAY_SIZE(easy336_sflash_partitions), ++ .type = "m25p32", ++}; ++ ++static struct spi_board_info bdinfo[] __initdata = { ++ { ++ .modalias = "m25p80", ++ .platform_data = &easy336_sflash_data, ++ .mode = SPI_MODE_0, ++ .irq = -1, ++ .max_speed_hz = 25000000, ++ .bus_num = 0, ++ .chip_select = 0, ++ } ++}; ++ ++static struct mtd_partition easy336_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0x0, ++ .size = 0x40000, ++ }, ++ { ++ .name = "uboot_env", ++ .offset = 0x40000, ++ .size = 0x20000, ++ }, ++ { ++ .name = "linux", ++ .offset = 0x60000, ++ .size = 0x1a0000, ++ }, ++ { ++ .name = "rootfs", ++ .offset = 0x200000, ++ .size = 0x500000, ++ }, ++}; ++ ++static struct physmap_flash_data easy336_flash_data = { ++ .nr_parts = ARRAY_SIZE(easy336_partitions), ++ .parts = easy336_partitions, ++}; ++ ++static const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS] = { ++ LTQ_MUX_P0_0_SSC0_MTSR, ++ LTQ_MUX_P0_1_SSC0_MRST, ++ LTQ_MUX_P0_2_SSC0_SCLK, ++ LTQ_MUX_P0_3_SSC1_MTSR, ++ LTQ_MUX_P0_4_SSC1_MRST, ++ LTQ_MUX_P0_5_SSC1_SCLK, ++ LTQ_MUX_P0_6_SSC0_CS0, ++ LTQ_MUX_P0_7_SSC0_CS1, ++ LTQ_MUX_P0_8_SSC0_CS2, ++ LTQ_MUX_P0_9_SSC0_CS3, ++ LTQ_MUX_P0_10_SSC0_CS4, ++ LTQ_MUX_P0_11_SSC0_CS5, ++ LTQ_MUX_P0_12_EXINT5, ++ LTQ_MUX_P0_13_EXINT6, ++ LTQ_MUX_P0_14_ASC0_TXD, ++ LTQ_MUX_P0_15_ASC0_RXD, ++ LTQ_MUX_P0_16_EXINT9, ++ LTQ_MUX_P0_17_EXINT10, ++ LTQ_MUX_P0_18_EJ_BRKIN, ++ LTQ_MUX_P0_19_EXINT16 ++}; ++ ++static const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS] = { ++ LTQ_MUX_P2_0_EBU_A0, ++ LTQ_MUX_P2_1_EBU_A1, ++ LTQ_MUX_P2_2_EBU_A2, ++ LTQ_MUX_P2_3_EBU_A3, ++ LTQ_MUX_P2_4_EBU_A4, ++ LTQ_MUX_P2_5_EBU_A5, ++ LTQ_MUX_P2_6_EBU_A6, ++ LTQ_MUX_P2_7_EBU_A7, ++ LTQ_MUX_P2_8_EBU_A8, ++ LTQ_MUX_P2_9_EBU_A9, ++ LTQ_MUX_P2_10_EBU_A10, ++ LTQ_MUX_P2_11_EBU_A11, ++ LTQ_MUX_P2_12_EBU_RD, ++ LTQ_MUX_P2_13_EBU_WR, ++ LTQ_MUX_P2_14_EBU_ALE, ++ LTQ_MUX_P2_15_EBU_WAIT, ++ LTQ_MUX_P2_16_EBU_RDBY, ++ LTQ_MUX_P2_17_EBU_BC0, ++ LTQ_MUX_P2_18_EBU_BC1 ++}; ++ ++static const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS] = { ++ LTQ_MUX_P3_0_EBU_AD0, ++ LTQ_MUX_P3_1_EBU_AD1, ++ LTQ_MUX_P3_2_EBU_AD2, ++ LTQ_MUX_P3_3_EBU_AD3, ++ LTQ_MUX_P3_4_EBU_AD4, ++ LTQ_MUX_P3_5_EBU_AD5, ++ LTQ_MUX_P3_6_EBU_AD6, ++ LTQ_MUX_P3_7_EBU_AD7, ++ LTQ_MUX_P3_8_EBU_AD8, ++ LTQ_MUX_P3_9_EBU_AD9, ++ LTQ_MUX_P3_10_EBU_AD10, ++ LTQ_MUX_P3_11_EBU_AD11, ++ LTQ_MUX_P3_12_EBU_AD12, ++ LTQ_MUX_P3_13_EBU_AD13, ++ LTQ_MUX_P3_14_EBU_AD14, ++ LTQ_MUX_P3_15_EBU_AD15, ++ LTQ_MUX_P3_16_EBU_CS0, ++ LTQ_MUX_P3_17_EBU_CS1, ++ LTQ_MUX_P3_18_EBU_CS2, ++ LTQ_MUX_P3_19_EBU_CS3 ++}; ++ ++static void __init easy336_init_common(void) ++{ ++ svip_sys1_clk_enable(SYS1_CLKENR_L2C | ++ SYS1_CLKENR_DDR2 | ++ SYS1_CLKENR_SMI2 | ++ SYS1_CLKENR_SMI1 | ++ SYS1_CLKENR_SMI0 | ++ SYS1_CLKENR_FMI0 | ++ SYS1_CLKENR_DMA | ++ SYS1_CLKENR_GPTC | ++ SYS1_CLKENR_EBU); ++ ++ svip_sys2_clk_enable(SYS2_CLKENR_HWSYNC | ++ SYS2_CLKENR_MBS | ++ SYS2_CLKENR_SWINT | ++ SYS2_CLKENR_HWACC3 | ++ SYS2_CLKENR_HWACC2 | ++ SYS2_CLKENR_HWACC1 | ++ SYS2_CLKENR_HWACC0 | ++ SYS2_CLKENR_SIF7 | ++ SYS2_CLKENR_SIF6 | ++ SYS2_CLKENR_SIF5 | ++ SYS2_CLKENR_SIF4 | ++ SYS2_CLKENR_SIF3 | ++ SYS2_CLKENR_SIF2 | ++ SYS2_CLKENR_SIF1 | ++ SYS2_CLKENR_SIF0 | ++ SYS2_CLKENR_DFEV7 | ++ SYS2_CLKENR_DFEV6 | ++ SYS2_CLKENR_DFEV5 | ++ SYS2_CLKENR_DFEV4 | ++ SYS2_CLKENR_DFEV3 | ++ SYS2_CLKENR_DFEV2 | ++ SYS2_CLKENR_DFEV1 | ++ SYS2_CLKENR_DFEV0); ++ ++ svip_register_mux(mux_p0, NULL, mux_p2, mux_p3, NULL); ++ svip_register_asc(0); ++ svip_register_eth(); ++ svip_register_virtual_eth(); ++ /* ltq_register_wdt(); - conflicts with lq_switch */ ++ svip_register_gpio(); ++ svip_register_spi(); ++ ltq_register_tapi(); ++} ++ ++static void __init easy336_init(void) ++{ ++ easy336_init_common(); ++ ltq_register_nor(&easy336_flash_data); ++} ++ ++static void __init easy336sf_init(void) ++{ ++ easy336_init_common(); ++ svip_register_spi_flash(bdinfo); ++} ++ ++static void __init easy336nand_init(void) ++{ ++ easy336_init_common(); ++ svip_register_nand(); ++} ++ ++MIPS_MACHINE(LANTIQ_MACH_EASY336, ++ "EASY336", ++ "EASY336", ++ easy336_init); ++ ++MIPS_MACHINE(LANTIQ_MACH_EASY336SF, ++ "EASY336SF", ++ "EASY336 (Serial Flash)", ++ easy336sf_init); ++ ++MIPS_MACHINE(LANTIQ_MACH_EASY336NAND, ++ "EASY336NAND", ++ "EASY336 (NAND Flash)", ++ easy336nand_init); ++ +Index: linux-3.3.8/drivers/net/ethernet/svip_virtual_eth.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/drivers/net/ethernet/svip_virtual_eth.c 2012-07-31 19:51:34.141105918 +0200 +@@ -0,0 +1,346 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2007 ++ Infineon Technologies AG ++ Am Campeon 1-12; 81726 Munich, Germany ++ ++ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, ++ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS ++ SOFTWARE IS FREE OF CHARGE. ++ ++ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS ++ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING ++ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE ++ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD ++ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL ++ PROPERTY INFRINGEMENT. ++ ++ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT ++ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM ++ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ DEALINGS IN THE SOFTWARE. ++ ++ **************************************************************************** ++Module : svip_virtual_eth.c ++ ++Description : This file contains network driver implementation for a ++Virtual Ethernet interface. The Virtual Ethernet interface ++is part of Infineon's VINETIC-SVIP Linux BSP. ++ *******************************************************************************/ ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/netdevice.h> ++#include <linux/platform_device.h> ++#include <linux/etherdevice.h> ++#include <linux/init.h> ++ ++#define SVIP_VETH_VER_STR "3.0" ++#define SVIP_VETH_INFO_STR \ ++ "@(#)SVIP virtual ethernet interface, version " SVIP_VETH_VER_STR ++ ++/****************************************************************************** ++ * Local define/macro definitions ++ ******************************************************************************/ ++struct svip_ve_priv ++{ ++ struct net_device_stats stats; ++}; ++ ++/****************************************************************************** ++ * Global function declarations ++ ******************************************************************************/ ++int svip_ve_rx(struct sk_buff *skb); ++ ++/****************************************************************************** ++ * Local variable declarations ++ ******************************************************************************/ ++static struct net_device *svip_ve_dev; ++static int watchdog_timeout = 10*HZ; ++static int (*svip_ve_mps_xmit)(struct sk_buff *skb) = NULL; ++ ++ ++/****************************************************************************** ++ * Global function declarations ++ ******************************************************************************/ ++ ++/** ++ * Called by MPS driver to register a transmit routine called for each outgoing ++ * VoFW0 message. ++ * ++ * \param mps_xmit pointer to transmit routine ++ * ++ * \return none ++ * ++ * \ingroup Internal ++ */ ++void register_mps_xmit_routine(int (*mps_xmit)(struct sk_buff *skb)) ++{ ++ svip_ve_mps_xmit = mps_xmit; ++} ++EXPORT_SYMBOL(register_mps_xmit_routine); ++ ++/** ++ * Returns a pointer to the routine used to deliver an incoming packet/message ++ * from the MPS mailbox to the networking layer. This routine is called by MPS ++ * driver during initialisation time. ++ * ++ * \param skb pointer to incoming socket buffer ++ * ++ * \return svip_ve_rx pointer to incoming messages delivering routine ++ * ++ * \ingroup Internal ++ */ ++int (*register_mps_recv_routine(void)) (struct sk_buff *skb) ++{ ++ return svip_ve_rx; ++} ++ ++/** ++ * Used to deliver outgoing packets to VoFW0 module through the MPS driver. ++ * Upon loading/initialisation the MPS driver is registering a transmitting ++ * routine, which is called here to deliver the packet to the VoFW0 module. ++ * ++ * \param skb pointer to skb containing outgoing data ++ * \param dev pointer to this networking device's data ++ * ++ * \return 0 on success ++ * \return non-zero on error ++ * ++ * \ingroup Internal ++ */ ++static int svip_ve_xmit(struct sk_buff *skb, struct net_device *dev) ++{ ++ int err; ++ struct svip_ve_priv *priv = netdev_priv(dev); ++ struct net_device_stats *stats = &priv->stats; ++ ++ stats->tx_packets++; ++ stats->tx_bytes += skb->len; ++ ++ if (svip_ve_mps_xmit) ++ { ++ err = svip_ve_mps_xmit(skb); ++ if (err) ++ stats->tx_errors++; ++ dev->trans_start = jiffies; ++ return err; ++ } ++ else ++ printk(KERN_ERR "%s: MPS driver not registered, outgoing packet not delivered\n", dev->name); ++ ++ dev_kfree_skb(skb); ++ ++ return -1; ++} ++ ++/** ++ * Called by MPS driver upon receipt of a new message from VoFW0 module in ++ * the data inbox. The packet is pushed up the IP module for further processing. ++ * ++ * \param skb pointer to skb containing the incoming message ++ * ++ * \return 0 on success ++ * \return non-zero on error ++ * ++ * \ingroup Internal ++ */ ++int svip_ve_rx(struct sk_buff *skb) ++{ ++ int err; ++ struct svip_ve_priv *priv = netdev_priv(svip_ve_dev); ++ struct net_device_stats *stats = &priv->stats; ++ ++ skb->dev = svip_ve_dev; ++ skb->protocol = eth_type_trans(skb, svip_ve_dev); ++ ++ stats->rx_packets++; ++ stats->rx_bytes += skb->len; ++ ++ err = netif_rx(skb); ++ switch (err) ++ { ++ case NET_RX_SUCCESS: ++ return 0; ++ break; ++ case NET_RX_DROP: ++ default: ++ stats->rx_dropped++; ++ break; ++ } ++ ++ return 1; ++} ++EXPORT_SYMBOL(svip_ve_rx); ++ ++/** ++ * Returns a pointer to the device's networking statistics data ++ * ++ * \param dev pointer to this networking device's data ++ * ++ * \return stats pointer to this network device's statistics data ++ * ++ * \ingroup Internal ++ */ ++static struct net_device_stats *svip_ve_get_stats(struct net_device *dev) ++{ ++ struct svip_ve_priv *priv = netdev_priv(dev); ++ ++ return &priv->stats; ++} ++ ++static void svip_ve_tx_timeout(struct net_device *dev) ++{ ++ struct svip_ve_priv *priv = netdev_priv(dev); ++ ++ priv->stats.tx_errors++; ++ netif_wake_queue(dev); ++} ++ ++/** ++ * Device open routine. Called e.g. upon setting of an IP address using, ++ * 'ifconfig veth0 YYY.YYY.YYY.YYY netmask ZZZ.ZZZ.ZZZ.ZZZ' or ++ * 'ifconfig veth0 up' ++ * ++ * \param dev pointer to this network device's data ++ * ++ * \return 0 on success ++ * \return non-zero on error ++ * ++ * \ingroup Internal ++ */ ++int svip_ve_open(struct net_device *dev) ++{ ++ netif_start_queue(dev); ++ return 0; ++} ++ ++/** ++ * Device close routine. Called e.g. upon calling ++ * 'ifconfig veth0 down' ++ * ++ * \param dev pointer to this network device's data ++ * ++ * \return 0 on success ++ * \return non-zero on error ++ * ++ * \ingroup Internal ++ */ ++ ++int svip_ve_release(struct net_device *dev) ++{ ++ netif_stop_queue(dev); ++ return 0; ++} ++ ++static int svip_ve_dev_init(struct net_device *dev); ++ ++static const struct net_device_ops svip_virtual_eth_netdev_ops = { ++ .ndo_init = svip_ve_dev_init, ++ .ndo_open = svip_ve_open, ++ .ndo_stop = svip_ve_release, ++ .ndo_start_xmit = svip_ve_xmit, ++ .ndo_get_stats = svip_ve_get_stats, ++ .ndo_tx_timeout = svip_ve_tx_timeout, ++}; ++ ++ ++/** ++ * Device initialisation routine which registers device interface routines. ++ * It is called upon execution of 'register_netdev' routine. ++ * ++ * \param dev pointer to this network device's data ++ * ++ * \return 0 on success ++ * \return non-zero on error ++ * ++ * \ingroup Internal ++ */ ++static int svip_ve_dev_init(struct net_device *dev) ++{ ++ ether_setup(dev); /* assign some of the fields */ ++ ++ dev->watchdog_timeo = watchdog_timeout; ++ memset(netdev_priv(dev), 0, sizeof(struct svip_ve_priv)); ++ dev->flags |= IFF_NOARP|IFF_PROMISC; ++ dev->flags &= ~IFF_MULTICAST; ++ ++ /* dedicated MAC address to veth0, 00:03:19:00:15:80 */ ++ dev->dev_addr[0] = 0x00; ++ dev->dev_addr[1] = 0x03; ++ dev->dev_addr[2] = 0x19; ++ dev->dev_addr[3] = 0x00; ++ dev->dev_addr[4] = 0x15; ++ dev->dev_addr[5] = 0x80; ++ ++ return 0; ++} ++ ++static int svip_ve_probe(struct platform_device *dev) ++{ ++ int result = 0; ++ ++ svip_ve_dev = alloc_etherdev(sizeof(struct svip_ve_priv)); ++ svip_ve_dev->netdev_ops = &svip_virtual_eth_netdev_ops; ++ ++ strcpy(svip_ve_dev->name, "veth%d"); ++ ++ result = register_netdev(svip_ve_dev); ++ if (result) ++ { ++ printk(KERN_INFO "error %i registering device \"%s\"\n", result, svip_ve_dev->name); ++ goto out; ++ } ++ ++ printk (KERN_INFO "%s, (c) 2009, Lantiq Deutschland GmbH\n", &SVIP_VETH_INFO_STR[4]); ++ ++out: ++ return result; ++} ++ ++static int svip_ve_remove(struct platform_device *dev) ++{ ++ unregister_netdev(svip_ve_dev); ++ free_netdev(svip_ve_dev); ++ ++ printk(KERN_INFO "%s removed\n", svip_ve_dev->name); ++ return 0; ++} ++ ++static struct platform_driver svip_ve_driver = { ++ .probe = svip_ve_probe, ++ .remove = svip_ve_remove, ++ .driver = { ++ .name = "ifxmips_svip_ve", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++/** ++ * Module/driver entry routine ++ */ ++static int __init svip_ve_init_module(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&svip_ve_driver); ++ if (ret) ++ printk(KERN_INFO "SVIP: error(%d) registering virtual Ethernet driver!\n", ret); ++ return ret; ++} ++ ++/** ++ * Module exit routine (never called for statically linked driver) ++ */ ++static void __exit svip_ve_cleanup_module(void) ++{ ++ platform_driver_unregister(&svip_ve_driver); ++} ++ ++module_init(svip_ve_init_module); ++module_exit(svip_ve_cleanup_module); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("virtual ethernet driver for LANTIQ SVIP system"); ++ ++EXPORT_SYMBOL(register_mps_recv_routine); +Index: linux-3.3.8/arch/mips/kernel/cevt-r4k.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/kernel/cevt-r4k.c 2012-06-01 09:16:13.000000000 +0200 ++++ linux-3.3.8/arch/mips/kernel/cevt-r4k.c 2012-07-31 19:51:34.141105918 +0200 +@@ -171,8 +171,10 @@ + if (!cpu_has_counter || !mips_hpt_frequency) + return -ENXIO; + ++#ifndef CONFIG_SOC_SVIP + if (!c0_compare_int_usable()) + return -ENXIO; ++#endif + + /* + * With vectored interrupts things are getting platform specific. +Index: linux-3.3.8/arch/mips/lantiq/clk.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/clk.c 2012-07-31 19:51:33.457105889 +0200 ++++ linux-3.3.8/arch/mips/lantiq/clk.c 2012-07-31 19:51:34.141105918 +0200 +@@ -149,7 +149,13 @@ + + clk = clk_get_cpu(); + mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); ++#ifdef CONFIG_SOC_SVIP ++ write_c0_count(0); ++ write_c0_compare(mips_hpt_frequency / HZ); ++ enable_irq(MIPS_CPU_TIMER_IRQ); ++#else + write_c0_compare(read_c0_count()); ++#endif + pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); + clk_put(clk); + } +Index: linux-3.3.8/arch/mips/lantiq/irq.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/irq.c 2012-07-31 19:51:33.897105907 +0200 ++++ linux-3.3.8/arch/mips/lantiq/irq.c 2012-07-31 19:51:34.141105918 +0200 +@@ -17,6 +17,10 @@ + + #include <lantiq_soc.h> + #include <irq.h> ++#ifdef CONFIG_SOC_SVIP ++#include <ebu_reg.h> ++#include <base_reg.h> ++#endif + + /* register definitions */ + #define LTQ_ICU_IM0_ISR 0x0000 +@@ -175,7 +179,6 @@ + int irq_nr = d->irq - INT_NUM_IRQ0; + unsigned int im_nr; + +- irq_nr -= INT_NUM_IRQ0; + im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + +@@ -188,7 +191,6 @@ + int irq_nr = d->irq - INT_NUM_IRQ0; + unsigned int im_nr; + +- irq_nr -= INT_NUM_IRQ0; + im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + +@@ -200,7 +202,6 @@ + int irq_nr = d->irq - INT_NUM_IRQ0; + unsigned int im_nr; + +- irq_nr -= INT_NUM_IRQ0; + im_nr = (irq_nr / INT_NUM_IM_OFFSET); + irq_nr %= INT_NUM_IM_OFFSET; + +@@ -281,10 +282,12 @@ + irq = __fls(irq); + do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); + ++#ifndef CONFIG_SOC_SVIP + /* if this is a EBU irq, we need to ack it or get a deadlock */ + if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, + LTQ_EBU_PCC_ISTAT); ++#endif + } + + #define DEFINE_HWx_IRQDISPATCH(x) \ +@@ -298,10 +301,14 @@ + DEFINE_HWx_IRQDISPATCH(3) + DEFINE_HWx_IRQDISPATCH(4) + ++#if MIPS_CPU_TIMER_IRQ == 7 + static void ltq_hw5_irqdispatch(void) + { + do_IRQ(MIPS_CPU_TIMER_IRQ); + } ++#else ++DEFINE_HWx_IRQDISPATCH(5) ++#endif + + #ifdef CONFIG_MIPS_MT_SMP + void __init arch_init_ipiirq(int irq, struct irqaction *action) +@@ -349,11 +356,11 @@ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + unsigned int i; + +- if (pending & CAUSEF_IP7) { ++ if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) { + do_IRQ(MIPS_CPU_TIMER_IRQ); + goto out; + } else { +- for (i = 0; i < 5; i++) { ++ for (i = 0; i < IM_NUM; i++) { + if (pending & (CAUSEF_IP2 << i)) { + ltq_hw_irqdispatch(i); + goto out; +@@ -389,15 +396,6 @@ + panic("Failed to remap icu memory\n"); + } + +- if (request_mem_region(ltq_icu_resource.start, +- resource_size(<q_icu_resource), "icu") < 0) +- panic("Failed to request icu memory"); +- +- ltq_icu_membase = ioremap_nocache(ltq_icu_resource.start, +- resource_size(<q_icu_resource)); +- if (!ltq_icu_membase) +- panic("Failed to remap icu memory"); +- + if (LTQ_EIU_BASE_ADDR) { + if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) + panic("Failed to insert eiu memory\n"); +@@ -413,7 +411,7 @@ + } + + /* make sure all irqs are turned off by default */ +- for (i = 0; i < IM_NUM; i++) ++ for (i = 0; i < IM_NUM; i++) { + ltq_icu_w32(0, LTQ_ICU_IM0_IER, i); + /* clear all possibly pending interrupts */ + ltq_icu_w32(~0, LTQ_ICU_IM0_ISR, i); +@@ -421,8 +419,8 @@ + + mips_cpu_irq_init(); + +- for (i = 2; i <= 6; i++) +- setup_irq(i, &cascade); ++ for (i = 0; i < IM_NUM; i++) ++ setup_irq(i + 2, &cascade); + + if (cpu_has_vint) { + pr_info("Setting up vectored interrupts\n"); +@@ -435,7 +433,7 @@ + } + + for (i = INT_NUM_IRQ0; +- i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) ++ i <= (INT_NUM_IRQ0 + (IM_NUM * INT_NUM_IM_OFFSET)); i++) + if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || + (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR) + irq_set_chip_and_handler(i, <q_eiu_type, +@@ -473,5 +471,9 @@ + + unsigned int __cpuinit get_c0_compare_int(void) + { ++#ifdef CONFIG_SOC_SVIP ++ return MIPS_CPU_TIMER_IRQ; ++#else + return CP0_LEGACY_COMPARE_IRQ; ++#endif + } +Index: linux-3.3.8/arch/mips/lantiq/svip/devices.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/devices.h 2012-07-31 19:51:34.141105918 +0200 +@@ -0,0 +1,23 @@ ++#ifndef _SVIP_DEVICES_H__ ++#define _SVIP_DEVICES_H__ ++ ++#include <linux/mtd/physmap.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/flash.h> ++#include <svip_mux.h> ++#include "../devices.h" ++ ++extern void __init svip_register_asc(int port); ++extern void __init svip_register_eth(void); ++extern void __init svip_register_virtual_eth(void); ++extern void __init svip_register_spi(void); ++extern void __init svip_register_spi_flash(struct spi_board_info *bdinfo); ++extern void __init svip_register_gpio(void); ++extern void __init svip_register_mux(const struct ltq_mux_pin mux_p0[LTQ_MUX_P0_PINS], ++ const struct ltq_mux_pin mux_p1[LTQ_MUX_P1_PINS], ++ const struct ltq_mux_pin mux_p2[LTQ_MUX_P2_PINS], ++ const struct ltq_mux_pin mux_p3[LTQ_MUX_P3_PINS], ++ const struct ltq_mux_pin mux_p4[LTQ_MUX_P4_PINS]); ++extern void __init svip_register_nand(void); ++ ++#endif +Index: linux-3.3.8/arch/mips/mm/c-r4k.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/mm/c-r4k.c 2012-07-31 19:51:33.433105887 +0200 ++++ linux-3.3.8/arch/mips/mm/c-r4k.c 2012-07-31 19:51:34.145105918 +0200 +@@ -1252,6 +1252,9 @@ + way_string[c->scache.ways], c->scache.linesz); + } + #else ++#ifdef CONFIG_SOC_SVIP ++ return; ++#endif + if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) + panic("Dunno how to handle MIPS32 / MIPS64 second level cache"); + #endif +Index: linux-3.3.8/arch/mips/lantiq/svip/dma.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/dma.c 2012-07-31 20:45:23.245243957 +0200 +@@ -0,0 +1,1206 @@ ++/* ++ ** Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com> ++ ** ++ ** This program is free software; you can redistribute it and/or modify ++ ** it under the terms of the GNU General Public License as published by ++ ** the Free Software Foundation; either version 2 of the License, or ++ ** (at your option) any later version. ++ ** ++ ** This program is distributed in the hope that it will be useful, ++ ** but WITHOUT ANY WARRANTY; without even the implied warranty of ++ ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ ** GNU General Public License for more details. ++ ** ++ ** You should have received a copy of the GNU General Public License ++ ** along with this program; if not, write to the Free Software ++ ** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++/* ++ * Description: ++ * Driver for SVIP DMA ++ * Author: Wu Qi Ming[Qi-Ming.Wu@infineon.com] ++ * Created: 26-September-2005 ++ */ ++ ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/sched.h> ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include <linux/string.h> ++#include <linux/timer.h> ++#include <linux/fs.h> ++#include <linux/errno.h> ++#include <linux/proc_fs.h> ++#include <linux/stat.h> ++#include <linux/mm.h> ++#include <linux/tty.h> ++#include <linux/selection.h> ++#include <linux/kmod.h> ++#include <linux/vmalloc.h> ++#include <linux/interrupt.h> ++#include <linux/delay.h> ++#include <linux/errno.h> ++#include <linux/uaccess.h> ++#include <linux/io.h> ++#include <linux/semaphore.h> ++ ++#include <base_reg.h> ++#include <mps_reg.h> ++#include <dma_reg.h> ++#include <svip_dma.h> ++#include <lantiq_soc.h> ++#include <irq.h> ++#include <sys1_reg.h> ++ ++static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; ++static struct svip_reg_dma *const dma = (struct svip_reg_dma *)LTQ_DMA_BASE; ++static struct svip_reg_mbs *const mbs = (struct svip_reg_mbs *)LTQ_MBS_BASE; ++ ++#define DRV_NAME "ltq_dma" ++extern void ltq_mask_and_ack_irq(struct irq_data *data); ++extern void ltq_enable_irq(struct irq_data *data); ++ ++static inline void mask_and_ack_irq(unsigned int irq_nr) ++{ ++ static int i = 0; ++ struct irq_data data; ++ data.irq = irq_nr; ++ if ((i < 2) && (irq_nr == 137)) { ++ printk("eth delay hack\n"); ++ i++; ++ } ++ ltq_mask_and_ack_irq(&data); ++} ++ ++static inline void svip_enable_irq(unsigned int irq_nr) ++{ ++ struct irq_data data; ++ data.irq = irq_nr; ++ ltq_enable_irq(&data); ++} ++ ++#define DMA_EMSG(fmt, args...) \ ++ printk(KERN_ERR "%s: " fmt, __func__, ## args) ++ ++static inline void mbs_grab(void) ++{ ++ while (mbs_r32(mbsr0) != 0); ++} ++ ++static inline void mbs_release(void) ++{ ++ mbs_w32(0, mbsr0); ++ asm("sync"); ++} ++ ++/* max ports connecting to dma */ ++#define LTQ_MAX_DMA_DEVICE_NUM ARRAY_SIZE(dma_devices) ++/* max dma channels */ ++#define LTQ_MAX_DMA_CHANNEL_NUM ARRAY_SIZE(dma_chan) ++ ++/* bytes per descriptor */ ++#define DMA_DESCR_SIZE 8 ++ ++#define DMA_DESCR_CH_SIZE (DMA_DESCR_NUM * DMA_DESCR_SIZE) ++#define DMA_DESCR_TOTAL_SIZE (LTQ_MAX_DMA_CHANNEL_NUM * DMA_DESCR_CH_SIZE) ++#define DMA_DESCR_MEM_PAGES ((DMA_DESCR_TOTAL_SIZE / PAGE_SIZE) + \ ++ (((DMA_DESCR_TOTAL_SIZE % PAGE_SIZE) > 0))) ++ ++/* budget for interrupt handling */ ++#define DMA_INT_BUDGET 100 ++/* set the correct counter value here! */ ++#define DMA_POLL_COUNTER 32 ++ ++struct proc_dir_entry *g_dma_dir; ++ ++/* device_name | max_rx_chan_num | max_tx_chan_num | drop_enable */ ++struct dma_device_info dma_devices[] = { ++ { "SW", 4, 4, 0 }, ++ { "DEU", 1, 1, 0 }, ++ { "SSC0", 1, 1, 0 }, ++ { "SSC1", 1, 1, 0 }, ++ { "MCTRL", 1, 1, 0 }, ++ { "PCM0", 1, 1, 0 }, ++ { "PCM1", 1, 1, 0 }, ++ { "PCM2", 1, 1, 0 }, ++ { "PCM3", 1, 1, 0 } ++}; ++ ++/* *dma_dev | dir | pri | irq | rel_chan_no */ ++struct dma_channel_info dma_chan[] = { ++ { &dma_devices[0], DIR_RX, 0, INT_NUM_IM4_IRL0 + 0, 0 }, ++ { &dma_devices[0], DIR_TX, 0, INT_NUM_IM4_IRL0 + 1, 0 }, ++ { &dma_devices[0], DIR_RX, 1, INT_NUM_IM4_IRL0 + 2, 1 }, ++ { &dma_devices[0], DIR_TX, 1, INT_NUM_IM4_IRL0 + 3, 1 }, ++ { &dma_devices[0], DIR_RX, 2, INT_NUM_IM4_IRL0 + 4, 2 }, ++ { &dma_devices[0], DIR_TX, 2, INT_NUM_IM4_IRL0 + 5, 2 }, ++ { &dma_devices[0], DIR_RX, 3, INT_NUM_IM4_IRL0 + 6, 3 }, ++ { &dma_devices[0], DIR_TX, 3, INT_NUM_IM4_IRL0 + 7, 3 }, ++ { &dma_devices[1], DIR_RX, 0, INT_NUM_IM4_IRL0 + 8, 0 }, ++ { &dma_devices[1], DIR_TX, 0, INT_NUM_IM4_IRL0 + 9, 0 }, ++ { &dma_devices[2], DIR_RX, 0, INT_NUM_IM4_IRL0 + 10, 0 }, ++ { &dma_devices[2], DIR_TX, 0, INT_NUM_IM4_IRL0 + 11, 0 }, ++ { &dma_devices[3], DIR_RX, 0, INT_NUM_IM4_IRL0 + 12, 0 }, ++ { &dma_devices[3], DIR_TX, 0, INT_NUM_IM4_IRL0 + 13, 0 }, ++ { &dma_devices[4], DIR_RX, 0, INT_NUM_IM4_IRL0 + 14, 0 }, ++ { &dma_devices[4], DIR_TX, 0, INT_NUM_IM4_IRL0 + 15, 0 }, ++ { &dma_devices[5], DIR_RX, 0, INT_NUM_IM4_IRL0 + 16, 0 }, ++ { &dma_devices[5], DIR_TX, 0, INT_NUM_IM4_IRL0 + 17, 0 }, ++ { &dma_devices[6], DIR_RX, 1, INT_NUM_IM3_IRL0 + 18, 0 }, ++ { &dma_devices[6], DIR_TX, 1, INT_NUM_IM3_IRL0 + 19, 0 }, ++ { &dma_devices[7], DIR_RX, 2, INT_NUM_IM4_IRL0 + 20, 0 }, ++ { &dma_devices[7], DIR_TX, 2, INT_NUM_IM4_IRL0 + 21, 0 }, ++ { &dma_devices[8], DIR_RX, 3, INT_NUM_IM4_IRL0 + 22, 0 }, ++ { &dma_devices[8], DIR_TX, 3, INT_NUM_IM4_IRL0 + 23, 0 } ++}; ++ ++u64 *g_desc_list[DMA_DESCR_MEM_PAGES]; ++ ++volatile u32 g_dma_int_status = 0; ++ ++/* 0 - not in process, 1 - in process */ ++volatile int g_dma_in_process; ++ ++int ltq_dma_init(void); ++void do_dma_tasklet(unsigned long); ++DECLARE_TASKLET(dma_tasklet, do_dma_tasklet, 0); ++irqreturn_t dma_interrupt(int irq, void *dev_id); ++ ++u8 *common_buffer_alloc(int len, int *byte_offset, void **opt) ++{ ++ u8 *buffer = kmalloc(len * sizeof(u8), GFP_KERNEL); ++ *byte_offset = 0; ++ return buffer; ++} ++ ++void common_buffer_free(u8 *dataptr, void *opt) ++{ ++ kfree(dataptr); ++} ++ ++void enable_ch_irq(struct dma_channel_info *ch) ++{ ++ int chan_no = (int)(ch - dma_chan); ++ unsigned long flag; ++ u32 val; ++ ++ if (ch->dir == DIR_RX) ++ val = DMA_CIE_DESCPT | DMA_CIE_DUR; ++ else ++ val = DMA_CIE_DESCPT; ++ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ dma_w32(val, cie); ++ dma_w32_mask(0, 1 << chan_no, irnen); ++ mbs_release(); ++ local_irq_restore(flag); ++ ++ svip_enable_irq(ch->irq); ++} ++ ++void disable_ch_irq(struct dma_channel_info *ch) ++{ ++ unsigned long flag; ++ int chan_no = (int)(ch - dma_chan); ++ ++ local_irq_save(flag); ++ g_dma_int_status &= ~(1 << chan_no); ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ dma_w32(0, cie); ++ mbs_release(); ++ dma_w32_mask(1 << chan_no, 0, irnen); ++ local_irq_restore(flag); ++ ++ mask_and_ack_irq(ch->irq); ++} ++ ++int open_chan(struct dma_channel_info *ch) ++{ ++ unsigned long flag; ++ int j; ++ int chan_no = (int)(ch - dma_chan); ++ u8 *buffer; ++ int byte_offset; ++ struct rx_desc *rx_desc_p; ++ struct tx_desc *tx_desc_p; ++ ++ if (ch->control == LTQ_DMA_CH_ON) ++ return -1; ++ ++ if (ch->dir == DIR_RX) { ++ for (j = 0; j < ch->desc_len; j++) { ++ rx_desc_p = (struct rx_desc *)ch->desc_base+j; ++ buffer = ch->dma_dev->buffer_alloc(ch->packet_size, ++ &byte_offset, ++ (void *)&ch->opt[j]); ++ if (!buffer) ++ return -ENOBUFS; ++ ++ rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buffer); ++ rx_desc_p->status.word = 0; ++ rx_desc_p->status.field.byte_offset = byte_offset; ++ rx_desc_p->status.field.data_length = ch->packet_size; ++ rx_desc_p->status.field.own = DMA_OWN; ++ } ++ } else { ++ for (j = 0; j < ch->desc_len; j++) { ++ tx_desc_p = (struct tx_desc *)ch->desc_base + j; ++ tx_desc_p->data_pointer = 0; ++ tx_desc_p->status.word = 0; ++ } ++ } ++ ch->xfer_cnt = 0; ++ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ dma_w32(ch->desc_len, cdlen); ++ dma_w32(0x7e, cis); ++ dma_w32(DMA_CCTRL_TXWGT_VAL(ch->tx_weight) ++ | DMA_CCTRL_CLASS_VAL(ch->pri) ++ | (ch->dir == DIR_RX ? DMA_CCTRL_ON_OFF : 0), cctrl); ++ mbs_release(); ++ ch->control = LTQ_DMA_CH_ON; ++ local_irq_restore(flag); ++ ++ if (request_irq(ch->irq, dma_interrupt, ++ IRQF_DISABLED, "dma-core", (void *)ch) != 0) { ++ printk(KERN_ERR "error, cannot get dma_irq!\n"); ++ return -EFAULT; ++ } ++ ++ enable_ch_irq(ch); ++ return 0; ++} ++ ++int close_chan(struct dma_channel_info *ch) ++{ ++ unsigned long flag; ++ int j; ++ int chan_no = (int)(ch - dma_chan); ++ struct rx_desc *desc_p; ++ ++ if (ch->control == LTQ_DMA_CH_OFF) ++ return -1; ++ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ dma_w32_mask(DMA_CCTRL_ON_OFF, 0, cctrl); ++ mbs_release(); ++ disable_ch_irq(ch); ++ free_irq(ch->irq, (void *)ch); ++ ch->control = LTQ_DMA_CH_OFF; ++ local_irq_restore(flag); ++ ++ /* free descriptors in use */ ++ for (j = 0; j < ch->desc_len; j++) { ++ desc_p = (struct rx_desc *)ch->desc_base+j; ++ if ((desc_p->status.field.own == CPU_OWN && ++ desc_p->status.field.c) || ++ (desc_p->status.field.own == DMA_OWN)) { ++ if (desc_p->data_pointer) { ++ ch->dma_dev->buffer_free((u8 *)__va(desc_p->data_pointer), ++ (void *)ch->opt[j]); ++ desc_p->data_pointer = (u32)NULL; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++int reset_chan(struct dma_channel_info *ch) ++{ ++ unsigned long flag; ++ int val; ++ int chan_no = (int)(ch - dma_chan); ++ ++ close_chan(ch); ++ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ dma_w32_mask(0, DMA_CCTRL_RST, cctrl); ++ mbs_release(); ++ local_irq_restore(flag); ++ ++ do { ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ val = dma_r32(cctrl); ++ mbs_release(); ++ local_irq_restore(flag); ++ } while (val & DMA_CCTRL_RST); ++ ++ return 0; ++} ++ ++static inline void rx_chan_intr_handler(int chan_no) ++{ ++ struct dma_device_info *dma_dev = (struct dma_device_info *) ++ dma_chan[chan_no].dma_dev; ++ struct dma_channel_info *ch = &dma_chan[chan_no]; ++ struct rx_desc *rx_desc_p; ++ unsigned long flag; ++ u32 val; ++ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ val = dma_r32(cis); ++ dma_w32(DMA_CIS_DESCPT, cis); ++ mbs_release(); ++ ++ /* handle command complete interrupt */ ++ rx_desc_p = (struct rx_desc *)ch->desc_base + ch->curr_desc; ++ if ((rx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == ++ DMA_DESC_CPT_SET) { ++ local_irq_restore(flag); ++ /* Every thing is correct, then we inform the upper layer */ ++ dma_dev->current_rx_chan = ch->rel_chan_no; ++ if (dma_dev->intr_handler) ++ dma_dev->intr_handler(dma_dev, RCV_INT); ++ ch->weight--; ++ } else { ++ g_dma_int_status &= ~(1 << chan_no); ++ local_irq_restore(flag); ++ svip_enable_irq(dma_chan[chan_no].irq); ++ } ++} ++ ++static inline void tx_chan_intr_handler(int chan_no) ++{ ++ struct dma_device_info *dma_dev = (struct dma_device_info *) ++ dma_chan[chan_no].dma_dev; ++ struct dma_channel_info *ch = &dma_chan[chan_no]; ++ struct tx_desc *tx_desc_p; ++ unsigned long flag; ++ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ dma_w32(DMA_CIS_DESCPT, cis); ++ mbs_release(); ++ ++ tx_desc_p = (struct tx_desc *)ch->desc_base+ch->prev_desc; ++ if ((tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) == ++ DMA_DESC_CPT_SET) { ++ local_irq_restore(flag); ++ ++ dma_dev->buffer_free((u8 *)__va(tx_desc_p->data_pointer), ++ ch->opt[ch->prev_desc]); ++ memset(tx_desc_p, 0, sizeof(struct tx_desc)); ++ dma_dev->current_tx_chan = ch->rel_chan_no; ++ if (dma_dev->intr_handler) ++ dma_dev->intr_handler(dma_dev, TRANSMIT_CPT_INT); ++ ch->weight--; ++ ++ ch->prev_desc = (ch->prev_desc + 1) % (ch->desc_len); ++ } else { ++ g_dma_int_status &= ~(1 << chan_no); ++ local_irq_restore(flag); ++ svip_enable_irq(dma_chan[chan_no].irq); ++ } ++} ++ ++void do_dma_tasklet(unsigned long unused) ++{ ++ int i; ++ int chan_no = 0; ++ int budget = DMA_INT_BUDGET; ++ int weight = 0; ++ unsigned long flag; ++ ++ while (g_dma_int_status) { ++ if (budget-- < 0) { ++ tasklet_schedule(&dma_tasklet); ++ return; ++ } ++ chan_no = -1; ++ weight = 0; ++ /* WFQ algorithm to select the channel */ ++ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { ++ if (g_dma_int_status & (1 << i) && ++ dma_chan[i].weight > 0) { ++ if (dma_chan[i].weight > weight) { ++ chan_no = i; ++ weight = dma_chan[chan_no].weight; ++ } ++ } ++ } ++ if (chan_no >= 0) { ++ if (dma_chan[chan_no].dir == DIR_RX) ++ rx_chan_intr_handler(chan_no); ++ else ++ tx_chan_intr_handler(chan_no); ++ } else { ++ /* reset all the channels */ ++ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) ++ dma_chan[i].weight = dma_chan[i].default_weight; ++ } ++ } ++ ++ local_irq_save(flag); ++ g_dma_in_process = 0; ++ if (g_dma_int_status) { ++ g_dma_in_process = 1; ++ tasklet_schedule(&dma_tasklet); ++ } ++ local_irq_restore(flag); ++} ++ ++irqreturn_t dma_interrupt(int irq, void *dev_id) ++{ ++ struct dma_channel_info *ch; ++ int chan_no = 0; ++ ++ ch = (struct dma_channel_info *)dev_id; ++ chan_no = (int)(ch - dma_chan); ++ ++ if ((unsigned)chan_no >= LTQ_MAX_DMA_CHANNEL_NUM) { ++ printk(KERN_ERR "error: dma_interrupt irq=%d chan_no=%d\n", ++ irq, chan_no); ++ } ++ ++ g_dma_int_status |= 1 << chan_no; ++ dma_w32(1 << chan_no, irncr); ++ mask_and_ack_irq(irq); ++ ++ if (!g_dma_in_process) { ++ g_dma_in_process = 1; ++ tasklet_schedule(&dma_tasklet); ++ } ++ ++ return IRQ_RETVAL(1); ++} ++ ++struct dma_device_info *dma_device_reserve(char *dev_name) ++{ ++ int i; ++ ++ ltq_dma_init(); ++ for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { ++ if (strcmp(dev_name, dma_devices[i].device_name) == 0) { ++ if (dma_devices[i].reserved) ++ return NULL; ++ dma_devices[i].reserved = 1; ++ break; ++ } ++ } ++ ++ if (i == LTQ_MAX_DMA_DEVICE_NUM) ++ return NULL; ++ ++ return &dma_devices[i]; ++} ++EXPORT_SYMBOL(dma_device_reserve); ++ ++int dma_device_release(struct dma_device_info *dma_dev) ++{ ++ dma_dev->reserved = 0; ++ ++ return 0; ++} ++EXPORT_SYMBOL(dma_device_release); ++ ++int dma_device_register(struct dma_device_info *dma_dev) ++{ ++ int port_no = (int)(dma_dev - dma_devices); ++ int txbl, rxbl; ++ unsigned long flag; ++ ++ switch (dma_dev->tx_burst_len) { ++ case 8: ++ txbl = 3; ++ break; ++ case 4: ++ txbl = 2; ++ break; ++ default: ++ txbl = 1; ++ break; ++ } ++ ++ switch (dma_dev->rx_burst_len) { ++ case 8: ++ rxbl = 3; ++ break; ++ case 4: ++ rxbl = 2; ++ break; ++ default: ++ rxbl = 1; ++ } ++ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(port_no, ps); ++ dma_w32(DMA_PCTRL_TXWGT_VAL(dma_dev->tx_weight) ++ | DMA_PCTRL_TXENDI_VAL(dma_dev->tx_endianness_mode) ++ | DMA_PCTRL_RXENDI_VAL(dma_dev->rx_endianness_mode) ++ | DMA_PCTRL_PDEN_VAL(dma_dev->drop_enable) ++ | DMA_PCTRL_TXBL_VAL(txbl) ++ | DMA_PCTRL_RXBL_VAL(rxbl), pctrl); ++ mbs_release(); ++ local_irq_restore(flag); ++ ++ return 0; ++} ++EXPORT_SYMBOL(dma_device_register); ++ ++int dma_device_unregister(struct dma_device_info *dma_dev) ++{ ++ int i; ++ int port_no = (int)(dma_dev - dma_devices); ++ unsigned long flag; ++ ++ /* flush memcopy module; has no effect for other ports */ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(port_no, ps); ++ dma_w32_mask(0, DMA_PCTRL_GPC, pctrl); ++ mbs_release(); ++ local_irq_restore(flag); ++ ++ for (i = 0; i < dma_dev->max_tx_chan_num; i++) ++ reset_chan(dma_dev->tx_chan[i]); ++ ++ for (i = 0; i < dma_dev->max_rx_chan_num; i++) ++ reset_chan(dma_dev->rx_chan[i]); ++ ++ return 0; ++} ++EXPORT_SYMBOL(dma_device_unregister); ++ ++/** ++ * Read Packet from DMA Rx channel. ++ * The function gets the data from the current rx descriptor assigned ++ * to the passed DMA device and passes it back to the caller. ++ * The function is called in the context of DMA interrupt. ++ * In detail the following actions are done: ++ * - get current receive descriptor ++ * - allocate memory via allocation callback function ++ * - pass data from descriptor to allocated memory ++ * - update channel weight ++ * - release descriptor ++ * - update current descriptor position ++ * ++ * \param *dma_dev - pointer to DMA device structure ++ * \param **dataptr - pointer to received data ++ * \param **opt ++ * \return packet length - length of received data ++ * \ingroup Internal ++ */ ++int dma_device_read(struct dma_device_info *dma_dev, u8 **dataptr, void **opt) ++{ ++ u8 *buf; ++ int len; ++ int byte_offset = 0; ++ void *p = NULL; ++ ++ struct dma_channel_info *ch = ++ dma_dev->rx_chan[dma_dev->current_rx_chan]; ++ ++ struct rx_desc *rx_desc_p; ++ ++ /* get the rx data first */ ++ rx_desc_p = (struct rx_desc *)ch->desc_base+ch->curr_desc; ++ buf = (u8 *)__va(rx_desc_p->data_pointer); ++ *(u32 *)dataptr = (u32)buf; ++ len = rx_desc_p->status.field.data_length; ++#ifndef CONFIG_MIPS_UNCACHED ++ dma_cache_inv((unsigned long)buf, len); ++#endif ++ if (opt) ++ *(int *)opt = (int)ch->opt[ch->curr_desc]; ++ ++ /* replace with a new allocated buffer */ ++ buf = dma_dev->buffer_alloc(ch->packet_size, &byte_offset, &p); ++ if (buf) { ++ ch->opt[ch->curr_desc] = p; ++ ++ wmb(); ++ rx_desc_p->data_pointer = (u32)CPHYSADDR((u32)buf); ++ rx_desc_p->status.word = (DMA_OWN << 31) \ ++ |(byte_offset << 23) \ ++ | ch->packet_size; ++ ++ wmb(); ++ } else { ++ *(u32 *)dataptr = 0; ++ if (opt) ++ *(int *)opt = 0; ++ } ++ ++ ch->xfer_cnt++; ++ /* increase the curr_desc pointer */ ++ ch->curr_desc++; ++ if (ch->curr_desc == ch->desc_len) ++ ch->curr_desc = 0; ++ /* return the length of the received packet */ ++ return len; ++} ++EXPORT_SYMBOL(dma_device_read); ++ ++/** ++ * Write Packet through DMA Tx channel to peripheral. ++ * ++ * \param *dma_dev - pointer to DMA device structure ++ * \param *dataptr - pointer to data to be sent ++ * \param len - amount of data bytes to be sent ++ * \param *opt ++ * \return len - length of transmitted data ++ * \ingroup Internal ++ */ ++int dma_device_write(struct dma_device_info *dma_dev, u8 *dataptr, int len, ++ void *opt) ++{ ++ unsigned long flag; ++ u32 byte_offset; ++ struct dma_channel_info *ch; ++ int chan_no; ++ struct tx_desc *tx_desc_p; ++ local_irq_save(flag); ++ ++ ch = dma_dev->tx_chan[dma_dev->current_tx_chan]; ++ chan_no = (int)(ch - dma_chan); ++ ++ if (ch->control == LTQ_DMA_CH_OFF) { ++ local_irq_restore(flag); ++ printk(KERN_ERR "%s: dma channel %d not enabled!\n", ++ __func__, chan_no); ++ return 0; ++ } ++ ++ tx_desc_p = (struct tx_desc *)ch->desc_base+ch->curr_desc; ++ /* Check whether this descriptor is available */ ++ if (tx_desc_p->status.word & (DMA_DESC_OWN_DMA | DMA_DESC_CPT_SET)) { ++ /* if not , the tell the upper layer device */ ++ dma_dev->intr_handler(dma_dev, TX_BUF_FULL_INT); ++ local_irq_restore(flag); ++ return 0; ++ } ++ ch->opt[ch->curr_desc] = opt; ++ /* byte offset----to adjust the starting address of the data buffer, ++ * should be multiple of the burst length.*/ ++ byte_offset = ((u32)CPHYSADDR((u32)dataptr)) % ++ (dma_dev->tx_burst_len * 4); ++#ifndef CONFIG_MIPS_UNCACHED ++ dma_cache_wback((unsigned long)dataptr, len); ++ wmb(); ++#endif ++ tx_desc_p->data_pointer = (u32)CPHYSADDR((u32)dataptr) - byte_offset; ++ wmb(); ++ tx_desc_p->status.word = (DMA_OWN << 31) ++ | DMA_DESC_SOP_SET ++ | DMA_DESC_EOP_SET ++ | (byte_offset << 23) ++ | len; ++ wmb(); ++ ++ if (ch->xfer_cnt == 0) { ++ mbs_grab(); ++ dma_w32(chan_no, cs); ++ dma_w32_mask(0, DMA_CCTRL_ON_OFF, cctrl); ++ mbs_release(); ++ } ++ ++ ch->xfer_cnt++; ++ ch->curr_desc++; ++ if (ch->curr_desc == ch->desc_len) ++ ch->curr_desc = 0; ++ ++ local_irq_restore(flag); ++ return len; ++} ++EXPORT_SYMBOL(dma_device_write); ++ ++/** ++ * Display descriptor list via proc file ++ * ++ * \param chan_no - logical channel number ++ * \ingroup Internal ++ */ ++int desc_list_proc_read(char *buf, char **start, off_t offset, ++ int count, int *eof, void *data) ++{ ++ int len = 0; ++ int i; ++ static int chan_no; ++ u32 *p; ++ ++ if ((chan_no == 0) && (offset > count)) { ++ *eof = 1; ++ return 0; ++ } ++ ++ if (chan_no != 0) { ++ *start = buf; ++ } else { ++ buf = buf + offset; ++ *start = buf; ++ } ++ ++ p = (u32 *)dma_chan[chan_no].desc_base; ++ ++ if (dma_chan[chan_no].dir == DIR_RX) ++ len += sprintf(buf + len, ++ "channel %d %s Rx descriptor list:\n", ++ chan_no, dma_chan[chan_no].dma_dev->device_name); ++ else ++ len += sprintf(buf + len, ++ "channel %d %s Tx descriptor list:\n", ++ chan_no, dma_chan[chan_no].dma_dev->device_name); ++ len += sprintf(buf + len, ++ " no address data pointer command bits " ++ "(Own, Complete, SoP, EoP, Offset) \n"); ++ len += sprintf(buf + len, ++ "----------------------------------------------" ++ "-----------------------------------\n"); ++ for (i = 0; i < dma_chan[chan_no].desc_len; i++) { ++ len += sprintf(buf + len, "%3d ", i); ++ len += sprintf(buf + len, "0x%08x ", (u32)(p + (i * 2))); ++ len += sprintf(buf + len, "%08x ", *(p + (i * 2 + 1))); ++ len += sprintf(buf + len, "%08x ", *(p + (i * 2))); ++ ++ if (*(p + (i * 2)) & 0x80000000) ++ len += sprintf(buf + len, "D "); ++ else ++ len += sprintf(buf + len, "C "); ++ if (*(p + (i * 2)) & 0x40000000) ++ len += sprintf(buf + len, "C "); ++ else ++ len += sprintf(buf + len, "c "); ++ if (*(p + (i * 2)) & 0x20000000) ++ len += sprintf(buf + len, "S "); ++ else ++ len += sprintf(buf + len, "s "); ++ if (*(p + (i * 2)) & 0x10000000) ++ len += sprintf(buf + len, "E "); ++ else ++ len += sprintf(buf + len, "e "); ++ ++ /* byte offset is different for rx and tx descriptors*/ ++ if (dma_chan[chan_no].dir == DIR_RX) { ++ len += sprintf(buf + len, "%01x ", ++ (*(p + (i * 2)) & 0x01800000) >> 23); ++ } else { ++ len += sprintf(buf + len, "%02x ", ++ (*(p + (i * 2)) & 0x0F800000) >> 23); ++ } ++ ++ if (dma_chan[chan_no].curr_desc == i) ++ len += sprintf(buf + len, "<- CURR"); ++ ++ if (dma_chan[chan_no].prev_desc == i) ++ len += sprintf(buf + len, "<- PREV"); ++ ++ len += sprintf(buf + len, "\n"); ++ ++ } ++ ++ len += sprintf(buf + len, "\n"); ++ chan_no++; ++ if (chan_no > LTQ_MAX_DMA_CHANNEL_NUM - 1) ++ chan_no = 0; ++ ++ *eof = 1; ++ return len; ++} ++ ++/** ++ * Displays the weight of all DMA channels via proc file ++ * ++ * ++ * ++ * \param *buf ++ * \param **start ++ * \param offset ++ * \param count ++ * \param *eof ++ * \param *data ++ * \return len - amount of bytes written to file ++ */ ++int channel_weight_proc_read(char *buf, char **start, off_t offset, ++ int count, int *eof, void *data) ++{ ++ int i; ++ int len = 0; ++ len += sprintf(buf + len, "Qos dma channel weight list\n"); ++ len += sprintf(buf + len, "channel_num default_weight " ++ "current_weight device Tx/Rx\n"); ++ len += sprintf(buf + len, "---------------------------" ++ "---------------------------------\n"); ++ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { ++ struct dma_channel_info *ch = &dma_chan[i]; ++ ++ if (ch->dir == DIR_RX) { ++ len += sprintf(buf + len, ++ " %2d %08x " ++ "%08x %10s Rx\n", ++ i, ch->default_weight, ch->weight, ++ ch->dma_dev->device_name); ++ } else { ++ len += sprintf(buf + len, ++ " %2d %08x " ++ "%08x %10s Tx\n", ++ i, ch->default_weight, ch->weight, ++ ch->dma_dev->device_name); ++ } ++ } ++ ++ return len; ++} ++ ++/** ++ * Provides DMA Register Content to proc file ++ * This function reads the content of general DMA Registers, DMA Channel ++ * Registers and DMA Port Registers and performs a structures output to the ++ * DMA proc file ++ * ++ * \param *buf ++ * \param **start ++ * \param offset ++ * \param count ++ * \param *eof ++ * \param *data ++ * \return len - amount of bytes written to file ++ */ ++int dma_register_proc_read(char *buf, char **start, off_t offset, ++ int count, int *eof, void *data) ++{ ++ int len = 0; ++ int i; ++ int limit = count; ++ unsigned long flags; ++ static int blockcount; ++ static int channel_no; ++ ++ if ((blockcount == 0) && (offset > count)) { ++ *eof = 1; ++ return 0; ++ } ++ ++ switch (blockcount) { ++ case 0: ++ len += sprintf(buf + len, "\nGeneral DMA Registers\n"); ++ len += sprintf(buf + len, "-------------------------" ++ "----------------\n"); ++ len += sprintf(buf + len, "CLC= %08x\n", dma_r32(clc)); ++ len += sprintf(buf + len, "ID= %08x\n", dma_r32(id)); ++ len += sprintf(buf + len, "DMA_CPOLL= %08x\n", dma_r32(cpoll)); ++ len += sprintf(buf + len, "DMA_CS= %08x\n", dma_r32(cs)); ++ len += sprintf(buf + len, "DMA_PS= %08x\n", dma_r32(ps)); ++ len += sprintf(buf + len, "DMA_IRNEN= %08x\n", dma_r32(irnen)); ++ len += sprintf(buf + len, "DMA_IRNCR= %08x\n", dma_r32(irncr)); ++ len += sprintf(buf + len, "DMA_IRNICR= %08x\n", ++ dma_r32(irnicr)); ++ len += sprintf(buf + len, "\nDMA Channel Registers\n"); ++ blockcount = 1; ++ return len; ++ break; ++ case 1: ++ /* If we had an overflow start at beginning of buffer ++ * otherwise use offset */ ++ if (channel_no != 0) { ++ *start = buf; ++ } else { ++ buf = buf + offset; ++ *start = buf; ++ } ++ ++ local_irq_save(flags); ++ for (i = channel_no; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { ++ struct dma_channel_info *ch = &dma_chan[i]; ++ ++ if (len + 300 > limit) { ++ local_irq_restore(flags); ++ channel_no = i; ++ blockcount = 1; ++ return len; ++ } ++ len += sprintf(buf + len, "----------------------" ++ "-------------------\n"); ++ if (ch->dir == DIR_RX) { ++ len += sprintf(buf + len, ++ "Channel %d - Device %s Rx\n", ++ i, ch->dma_dev->device_name); ++ } else { ++ len += sprintf(buf + len, ++ "Channel %d - Device %s Tx\n", ++ i, ch->dma_dev->device_name); ++ } ++ dma_w32(i, cs); ++ len += sprintf(buf + len, "DMA_CCTRL= %08x\n", ++ dma_r32(cctrl)); ++ len += sprintf(buf + len, "DMA_CDBA= %08x\n", ++ dma_r32(cdba)); ++ len += sprintf(buf + len, "DMA_CIE= %08x\n", ++ dma_r32(cie)); ++ len += sprintf(buf + len, "DMA_CIS= %08x\n", ++ dma_r32(cis)); ++ len += sprintf(buf + len, "DMA_CDLEN= %08x\n", ++ dma_r32(cdlen)); ++ } ++ local_irq_restore(flags); ++ blockcount = 2; ++ channel_no = 0; ++ return len; ++ break; ++ case 2: ++ *start = buf; ++ /* ++ * display port dependent registers ++ */ ++ len += sprintf(buf + len, "\nDMA Port Registers\n"); ++ len += sprintf(buf + len, ++ "-----------------------------------------\n"); ++ local_irq_save(flags); ++ for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { ++ dma_w32(i, ps); ++ len += sprintf(buf + len, ++ "Port %d DMA_PCTRL= %08x\n", ++ i, dma_r32(pctrl)); ++ } ++ local_irq_restore(flags); ++ blockcount = 0; ++ *eof = 1; ++ return len; ++ break; ++ } ++ ++ blockcount = 0; ++ *eof = 1; ++ return 0; ++} ++ ++/** ++ * Open Method of DMA Device Driver ++ * This function increments the device driver's use counter. ++ * ++ * ++ * \param ++ * \return ++ */ ++static int dma_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++/** ++ * Release Method of DMA Device driver. ++ * This function decrements the device driver's use counter. ++ * ++ * ++ * \param ++ * \return ++ */ ++static int dma_release(struct inode *inode, struct file *file) ++{ ++ /* release the resources */ ++ return 0; ++} ++ ++/** ++ * Ioctl Interface to DMA Module ++ * ++ * \param None ++ * \return 0 - initialization successful ++ * <0 - failed initialization ++ */ ++static long dma_ioctl(struct file *file, ++ unsigned int cmd, unsigned long arg) ++{ ++ int result = 0; ++ /* TODO: add some user controled functions here */ ++ return result; ++} ++ ++const static struct file_operations dma_fops = { ++ .owner = THIS_MODULE, ++ .open = dma_open, ++ .release = dma_release, ++ .unlocked_ioctl = dma_ioctl, ++}; ++ ++void map_dma_chan(struct dma_channel_info *map) ++{ ++ int i; ++ ++ /* assign default values for channel settings */ ++ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { ++ dma_chan[i].byte_offset = 0; ++ dma_chan[i].open = &open_chan; ++ dma_chan[i].close = &close_chan; ++ dma_chan[i].reset = &reset_chan; ++ dma_chan[i].enable_irq = enable_ch_irq; ++ dma_chan[i].disable_irq = disable_ch_irq; ++ dma_chan[i].tx_weight = 1; ++ dma_chan[i].control = 0; ++ dma_chan[i].default_weight = LTQ_DMA_CH_DEFAULT_WEIGHT; ++ dma_chan[i].weight = dma_chan[i].default_weight; ++ dma_chan[i].curr_desc = 0; ++ dma_chan[i].prev_desc = 0; ++ } ++ ++ /* assign default values for port settings */ ++ for (i = 0; i < LTQ_MAX_DMA_DEVICE_NUM; i++) { ++ /*set default tx channel number to be one*/ ++ dma_devices[i].num_tx_chan = 1; ++ /*set default rx channel number to be one*/ ++ dma_devices[i].num_rx_chan = 1; ++ dma_devices[i].buffer_alloc = common_buffer_alloc; ++ dma_devices[i].buffer_free = common_buffer_free; ++ dma_devices[i].intr_handler = NULL; ++ dma_devices[i].tx_burst_len = 4; ++ dma_devices[i].rx_burst_len = 4; ++#ifdef CONFIG_CPU_LITTLE_ENDIAN ++ dma_devices[i].tx_endianness_mode = 0; ++ dma_devices[i].rx_endianness_mode = 0; ++#else ++ dma_devices[i].tx_endianness_mode = 3; ++ dma_devices[i].rx_endianness_mode = 3; ++#endif ++ } ++} ++ ++void dma_chip_init(void) ++{ ++ int i; ++ ++ sys1_w32(SYS1_CLKENR_DMA, clkenr); ++ wmb(); ++ /* reset DMA */ ++ dma_w32(DMA_CTRL_RST, ctrl); ++ wmb(); ++ /* disable all the interrupts first */ ++ dma_w32(0, irnen); ++ ++ /* enable polling for all channels */ ++ dma_w32(DMA_CPOLL_EN | DMA_CPOLL_CNT_VAL(DMA_POLL_COUNTER), cpoll); ++ ++ /****************************************************/ ++ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) ++ disable_ch_irq(&dma_chan[i]); ++} ++ ++int ltq_dma_init(void) ++{ ++ int result = 0; ++ int i; ++ unsigned long flag; ++ static int dma_initialized; ++ ++ if (dma_initialized == 1) ++ return 0; ++ dma_initialized = 1; ++ ++ result = register_chrdev(DMA_MAJOR, "dma-core", &dma_fops); ++ if (result) { ++ DMA_EMSG("cannot register device dma-core!\n"); ++ return result; ++ } ++ ++ dma_chip_init(); ++ map_dma_chan(dma_chan); ++ ++ /* allocate DMA memory for buffer descriptors */ ++ for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) { ++ g_desc_list[i] = (u64 *)__get_free_page(GFP_DMA); ++ if (g_desc_list[i] == NULL) { ++ DMA_EMSG("no memory for desriptor\n"); ++ return -ENOMEM; ++ } ++ g_desc_list[i] = (u64 *)KSEG1ADDR(g_desc_list[i]); ++ memset(g_desc_list[i], 0, PAGE_SIZE); ++ } ++ ++ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) { ++ int page_index, ch_per_page; ++ /* cross-link relative channels of a port to ++ * corresponding absolute channels */ ++ if (dma_chan[i].dir == DIR_RX) { ++ ((struct dma_device_info *)(dma_chan[i].dma_dev))-> ++ rx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; ++ } else { ++ ((struct dma_device_info *)(dma_chan[i].dma_dev))-> ++ tx_chan[dma_chan[i].rel_chan_no] = &dma_chan[i]; ++ } ++ dma_chan[i].abs_chan_no = i; ++ ++ page_index = i * DMA_DESCR_CH_SIZE / PAGE_SIZE; ++ ch_per_page = PAGE_SIZE / DMA_DESCR_CH_SIZE + ++ ((PAGE_SIZE % DMA_DESCR_CH_SIZE) > 0); ++ dma_chan[i].desc_base = ++ (u32)g_desc_list[page_index] + ++ (i - page_index*ch_per_page) * DMA_DESCR_NUM*8; ++ dma_chan[i].curr_desc = 0; ++ dma_chan[i].desc_len = DMA_DESCR_NUM; ++ ++ local_irq_save(flag); ++ mbs_grab(); ++ dma_w32(i, cs); ++ dma_w32((u32)CPHYSADDR(dma_chan[i].desc_base), cdba); ++ mbs_release(); ++ local_irq_restore(flag); ++ } ++ ++ g_dma_dir = proc_mkdir("driver/" DRV_NAME, NULL); ++ ++ create_proc_read_entry("dma_register", ++ 0, ++ g_dma_dir, ++ dma_register_proc_read, ++ NULL); ++ ++ create_proc_read_entry("g_desc_list", ++ 0, ++ g_dma_dir, ++ desc_list_proc_read, ++ NULL); ++ ++ create_proc_read_entry("channel_weight", ++ 0, ++ g_dma_dir, ++ channel_weight_proc_read, ++ NULL); ++ ++ printk(KERN_NOTICE "SVIP DMA engine initialized\n"); ++ ++ return 0; ++} ++ ++/** ++ * Cleanup DMA device ++ * This function releases all resources used by the DMA device driver on ++ * module removal. ++ * ++ * ++ * \param None ++ * \return Nothing ++ */ ++void dma_cleanup(void) ++{ ++ int i; ++ unregister_chrdev(DMA_MAJOR, "dma-core"); ++ ++ for (i = 0; i < DMA_DESCR_MEM_PAGES; i++) ++ free_page(KSEG0ADDR((unsigned long)g_desc_list[i])); ++ remove_proc_entry("channel_weight", g_dma_dir); ++ remove_proc_entry("g_desc_list", g_dma_dir); ++ remove_proc_entry("dma_register", g_dma_dir); ++ remove_proc_entry("driver/" DRV_NAME, NULL); ++ /* release the resources */ ++ for (i = 0; i < LTQ_MAX_DMA_CHANNEL_NUM; i++) ++ free_irq(dma_chan[i].irq, (void *)&dma_chan[i]); ++} ++ ++arch_initcall(ltq_dma_init); ++ ++MODULE_LICENSE("GPL"); +Index: linux-3.3.8/drivers/net/ethernet/svip_eth.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/drivers/net/ethernet/svip_eth.c 2012-07-31 20:14:58.881165968 +0200 +@@ -0,0 +1,636 @@ ++/************************************************************************ ++ * ++ * Copyright (c) 2005 ++ * Infineon Technologies AG ++ * St. Martin Strasse 53; 81669 Muenchen; Germany ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ ************************************************************************/ ++ ++#include <linux/kernel.h> ++#include <linux/slab.h> ++#include <linux/errno.h> ++#include <linux/types.h> ++#include <linux/interrupt.h> ++#include <linux/uaccess.h> ++#include <linux/in.h> ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/ip.h> ++#include <linux/tcp.h> ++#include <linux/skbuff.h> ++#include <linux/mm.h> ++#include <linux/platform_device.h> ++#include <linux/ethtool.h> ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/delay.h> ++#include <asm/checksum.h> ++ ++#if 1 /** TODO: MOVE TO APPROPRIATE PLACE */ ++ ++#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600 ++#define REV_MII_MODE 2 ++ ++#endif ++ ++#define DRV_NAME "ifxmips_mii0" ++ ++#include <lantiq_soc.h> ++#include <svip_dma.h> ++ ++#ifdef CONFIG_DEBUG_MINI_BOOT ++#define IKOS_MINI_BOOT ++#endif ++ ++/* debugging */ ++#undef INCAIP2_SW_DUMP ++ ++#define INCAIP2_SW_EMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) ++ ++#define INCAIP2_SW_CHIP_NO 1 ++#define INCAIP2_SW_CHIP_ID 0 ++#define INCAIP2_SW_DEVICE_NO 1 ++ ++#ifdef INCAIP2_SW_DEBUG_MSG ++#define INCAIP2_SW_DMSG(fmt,args...) printk("%s: " fmt, __FUNCTION__ , ##args) ++#else ++#define INCAIP2_SW_DMSG(fmt,args...) ++#endif ++ ++/************************** Module Parameters *****************************/ ++static char *mode = "bridge"; ++module_param(mode, charp, 0000); ++MODULE_PARM_DESC(mode, "<description>"); ++ ++#ifdef HAVE_TX_TIMEOUT ++static int timeout = 10*HZ; ++module_param(timeout, int, 0); ++MODULE_PARM_DESC(timeout, "Transmission watchdog timeout in seconds>"); ++#endif ++ ++#ifdef IKOS_MINI_BOOT ++#ifdef CONFIG_INCAIP2 ++extern s32 incaip2_sw_to_mbx(struct sk_buff* skb); ++#endif ++extern s32 svip_sw_to_mbx(struct sk_buff* skb); ++#endif ++ ++struct svip_mii_priv { ++ struct net_device_stats stats; ++ struct dma_device_info *dma_device; ++ struct sk_buff *skb; ++}; ++ ++static struct net_device *svip_mii0_dev; ++static unsigned char mac_addr[MAX_ADDR_LEN]; ++static unsigned char my_ethaddr[MAX_ADDR_LEN]; ++ ++/** ++ * Initialize MAC address. ++ * This function copies the ethernet address from kernel command line. ++ * ++ * \param line Pointer to parameter ++ * \return 0 OK ++ * \ingroup Internal ++ */ ++static int __init svip_eth_ethaddr_setup(char *line) ++{ ++ char *ep; ++ int i; ++ ++ memset(my_ethaddr, 0, MAX_ADDR_LEN); ++ /* there should really be routines to do this stuff */ ++ for (i = 0; i < 6; i++) ++ { ++ my_ethaddr[i] = line ? simple_strtoul(line, &ep, 16) : 0; ++ if (line) ++ line = (*ep) ? ep+1 : ep; ++ } ++ INCAIP2_SW_DMSG("mac address %2x-%2x-%2x-%2x-%2x-%2x \n" ++ ,my_ethaddr[0] ++ ,my_ethaddr[1] ++ ,my_ethaddr[2] ++ ,my_ethaddr[3] ++ ,my_ethaddr[4] ++ ,my_ethaddr[5]); ++ return 0; ++} ++__setup("ethaddr=", svip_eth_ethaddr_setup); ++ ++ ++/** ++ * Open RX DMA channels. ++ * This function opens all DMA rx channels. ++ * ++ * \param dma_dev pointer to DMA device information ++ * \ingroup Internal ++ */ ++static void svip_eth_open_rx_dma(struct dma_device_info *dma_dev) ++{ ++ int i; ++ ++ for(i=0; i<dma_dev->num_rx_chan; i++) ++ { ++ dma_dev->rx_chan[i]->open(dma_dev->rx_chan[i]); ++ } ++} ++ ++ ++/** ++ * Open TX DMA channels. ++ * This function opens all DMA tx channels. ++ * ++ * \param dev pointer to net device structure that comprises ++ * DMA device information pointed to by it's priv field. ++ * \ingroup Internal ++ */ ++static void svip_eth_open_tx_dma(struct dma_device_info *dma_dev) ++{ ++ int i; ++ ++ for (i=0; i<dma_dev->num_tx_chan; i++) ++ { ++ dma_dev->tx_chan[i]->open(dma_dev->tx_chan[i]); ++ } ++} ++ ++ ++#ifdef CONFIG_NET_HW_FLOWCONTROL ++/** ++ * Enable receiving DMA. ++ * This function enables the receiving DMA channel. ++ * ++ * \param dev pointer to net device structure that comprises ++ * DMA device information pointed to by it's priv field. ++ * \ingroup Internal ++ */ ++void svip_eth_xon(struct net_device *dev) ++{ ++ struct switch_priv *sw_dev = (struct switch_priv *)dev->priv; ++ struct dma_device_info* dma_dev = ++ (struct dma_device_info *)sw_dev->dma_device; ++ unsigned long flag; ++ ++ local_irq_save(flag); ++ ++ INCAIP2_SW_DMSG("wakeup\n"); ++ svip_eth_open_rx_dma(dma_dev); ++ ++ local_irq_restore(flag); ++} ++#endif /* CONFIG_NET_HW_FLOWCONTROL */ ++ ++ ++/** ++ * Open network device. ++ * This functions opens the network device and starts the interface queue. ++ * ++ * \param dev Device structure for Ethernet device ++ * \return 0 OK, device opened ++ * \return -1 Error, registering DMA device ++ * \ingroup API ++ */ ++int svip_mii_open(struct net_device *dev) ++{ ++ struct svip_mii_priv *priv = netdev_priv(dev); ++ struct dma_device_info *dma_dev = priv->dma_device; ++ ++ svip_eth_open_rx_dma(dma_dev); ++ svip_eth_open_tx_dma(dma_dev); ++ ++ netif_start_queue(dev); ++ return 0; ++} ++ ++ ++/** ++ * Close network device. ++ * This functions closes the network device, which will also stop the interface ++ * queue. ++ * ++ * \param dev Device structure for Ethernet device ++ * \return 0 OK, device closed (cannot fail) ++ * \ingroup API ++ */ ++int svip_mii_release(struct net_device *dev) ++{ ++ struct svip_mii_priv *priv = netdev_priv(dev); ++ struct dma_device_info *dma_dev = priv->dma_device; ++ int i; ++ ++ for (i = 0; i < dma_dev->max_rx_chan_num; i++) ++ dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]); ++ netif_stop_queue(dev); ++ return 0; ++} ++ ++ ++/** ++ * Read data from DMA device. ++ * This function reads data from the DMA device. The function is called by ++ * the switch/DMA pseudo interrupt handler dma_intr_handler on occurence of ++ * a DMA receive interrupt. ++ * ++ * \param dev Pointer to network device structure ++ * \param dma_dev Pointer to dma device structure ++ * \return OK In case of successful data reception from dma ++ * -EIO Incorrect opt pointer provided by device ++ * \ingroup Internal ++ */ ++int svip_mii_hw_receive(struct net_device *dev, struct dma_device_info *dma_dev) ++{ ++ struct svip_mii_priv *priv = netdev_priv(dev); ++ unsigned char *buf = NULL; ++ struct sk_buff *skb = NULL; ++ int len = 0; ++ ++ len = dma_device_read(dma_dev, &buf, (void **)&skb); ++ ++ if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE) { ++ printk(KERN_INFO DRV_NAME ": packet too large %d\n", len); ++ goto mii_hw_receive_err_exit; ++ } ++ ++ if (skb == NULL) { ++ printk(KERN_INFO DRV_NAME ": cannot restore pointer\n"); ++ goto mii_hw_receive_err_exit; ++ } ++ ++ if (len > (skb->end - skb->tail)) { ++ printk(KERN_INFO DRV_NAME ": BUG, len:%d end:%p tail:%p\n", ++ len, skb->end, skb->tail); ++ goto mii_hw_receive_err_exit; ++ } ++ ++ skb_put(skb, len); ++ skb->dev = dev; ++ skb->protocol = eth_type_trans(skb, dev); ++ netif_rx(skb); ++ ++ priv->stats.rx_packets++; ++ priv->stats.rx_bytes += len; ++ return 0; ++ ++mii_hw_receive_err_exit: ++ if (len == 0) { ++ if (skb) ++ dev_kfree_skb_any(skb); ++ priv->stats.rx_errors++; ++ priv->stats.rx_dropped++; ++ return -EIO; ++ } else { ++ return len; ++ } ++} ++ ++ ++/** ++ * Write data to Ethernet switch. ++ * This function writes the data comprised in skb structure via DMA to the ++ * Ethernet Switch. It is installed as the switch driver's hard_start_xmit ++ * method. ++ * ++ * \param skb Pointer to socket buffer structure that contains the data ++ * to be sent ++ * \param dev Pointer to network device structure which is used for ++ * data transmission ++ * \return 1 Transmission error ++ * \return 0 OK, successful data transmission ++ * \ingroup API ++ */ ++static int svip_mii_hw_tx(char *buf, int len, struct net_device *dev) ++{ ++ int ret = 0; ++ struct svip_mii_priv *priv = netdev_priv(dev); ++ struct dma_device_info *dma_dev = priv->dma_device; ++ ret = dma_device_write(dma_dev, buf, len, priv->skb); ++ return ret; ++} ++ ++static int svip_mii_tx(struct sk_buff *skb, struct net_device *dev) ++{ ++ int len; ++ char *data; ++ struct svip_mii_priv *priv = netdev_priv(dev); ++ struct dma_device_info *dma_dev = priv->dma_device; ++ ++ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; ++ data = skb->data; ++ priv->skb = skb; ++ dev->trans_start = jiffies; ++ /* TODO: we got more than 1 dma channel, ++ so we should do something intelligent here to select one */ ++ dma_dev->current_tx_chan = 0; ++ ++ wmb(); ++ ++ if (svip_mii_hw_tx(data, len, dev) != len) { ++ dev_kfree_skb_any(skb); ++ priv->stats.tx_errors++; ++ priv->stats.tx_dropped++; ++ } else { ++ priv->stats.tx_packets++; ++ priv->stats.tx_bytes += len; ++ } ++ ++ return 0; ++} ++ ++ ++/** ++ * Transmission timeout callback. ++ * This functions is called when a trasmission timeout occurs. It will wake up ++ * the interface queue again. ++ * ++ * \param dev Device structure for Ethernet device ++ * \ingroup API ++ */ ++void svip_mii_tx_timeout(struct net_device *dev) ++{ ++ int i; ++ struct svip_mii_priv *priv = netdev_priv(dev); ++ ++ priv->stats.tx_errors++; ++ for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) ++ priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]); ++ netif_wake_queue(dev); ++ return; ++} ++ ++ ++/** ++ * Get device statistics. ++ * This functions returns the device statistics, stored in the device structure. ++ * ++ * \param dev Device structure for Ethernet device ++ * \return stats Pointer to statistics structure ++ * \ingroup API ++ */ ++static struct net_device_stats *svip_get_stats(struct net_device *dev) ++{ ++ struct svip_mii_priv *priv = netdev_priv(dev); ++ return &priv->stats; ++} ++ ++ ++/** ++ * Pseudo Interrupt handler for DMA. ++ * This function processes DMA interrupts notified to the switch device driver. ++ * The function is installed at the DMA core as interrupt handler for the ++ * switch dma device. ++ * It handles the following DMA interrupts: ++ * passes received data to the upper layer in case of rx interrupt, ++ * In case of a dma receive interrupt the received data is passed to the upper layer. ++ * In case of a transmit buffer full interrupt the transmit queue is stopped. ++ * In case of a transmission complete interrupt the transmit queue is restarted. ++ * ++ * \param dma_dev pointer to dma device structure ++ * \param status type of interrupt being notified (RCV_INT: dma receive ++ * interrupt, TX_BUF_FULL_INT: transmit buffer full interrupt, ++ * TRANSMIT_CPT_INT: transmission complete interrupt) ++ * \return OK In case of successful data reception from dma ++ * \ingroup Internal ++ */ ++int dma_intr_handler(struct dma_device_info *dma_dev, int status) ++{ ++ int i; ++ ++ switch (status) { ++ case RCV_INT: ++ svip_mii_hw_receive(svip_mii0_dev, dma_dev); ++ break; ++ ++ case TX_BUF_FULL_INT: ++ printk(KERN_INFO DRV_NAME ": tx buffer full\n"); ++ netif_stop_queue(svip_mii0_dev); ++ for (i = 0; i < dma_dev->max_tx_chan_num; i++) { ++ if ((dma_dev->tx_chan[i])->control == LTQ_DMA_CH_ON) ++ dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]); ++ } ++ break; ++ ++ case TRANSMIT_CPT_INT: ++ ++#if 0 ++ for (i = 0; i < dma_dev->max_tx_chan_num; i++) ++#if 0 ++ dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]); ++#else ++ dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i], (char *)__FUNCTION__); ++#endif ++ netif_wake_queue(svip_mii0_dev); ++#endif ++ break; ++ } ++ ++ return 0; ++} ++ ++ ++/** ++ * Allocates buffer sufficient for Ethernet Frame. ++ * This function is installed as DMA callback function to be called on DMA ++ * receive interrupt. ++ * ++ * \param len Unused ++ * \param *byte_offset Pointer to byte offset ++ * \param **opt pointer to skb structure ++ * \return NULL In case of buffer allocation fails ++ * buffer Pointer to allocated memory ++ * \ingroup Internal ++ */ ++unsigned char *svip_etop_dma_buffer_alloc(int len, int *byte_offset, void **opt) ++{ ++ unsigned char *buffer = NULL; ++ struct sk_buff *skb = NULL; ++ ++ skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE); ++ if (skb == NULL) ++ return NULL; ++ ++ buffer = (unsigned char *)(skb->data); ++ skb_reserve(skb, 2); ++ *(int *)opt = (int)skb; ++ *byte_offset = 2; ++ ++ return buffer; ++} ++ ++ ++/** ++ * Free DMA buffer. ++ * This function frees a buffer, which can be either a data buffer or an ++ * skb structure. ++ * ++ * \param *dataptr Pointer to data buffer ++ * \param *opt Pointer to skb structure ++ * \return 0 OK ++ * \ingroup Internal ++ */ ++void svip_etop_dma_buffer_free(unsigned char *dataptr, void *opt) ++{ ++ struct sk_buff *skb = NULL; ++ ++ if (opt == NULL) { ++ kfree(dataptr); ++ } else { ++ skb = (struct sk_buff *)opt; ++ dev_kfree_skb_any(skb); ++ } ++} ++ ++static int svip_mii_dev_init(struct net_device *dev); ++ ++static const struct net_device_ops svip_eth_netdev_ops = { ++ .ndo_init = svip_mii_dev_init, ++ .ndo_open = svip_mii_open, ++ .ndo_stop = svip_mii_release, ++ .ndo_start_xmit = svip_mii_tx, ++ .ndo_get_stats = svip_get_stats, ++ .ndo_tx_timeout = svip_mii_tx_timeout, ++}; ++ ++//#include <linux/device.h> ++ ++/** ++ * Initialize switch driver. ++ * This functions initializes the switch driver structures and registers the ++ * Ethernet device. ++ * ++ * \param dev Device structure for Ethernet device ++ * \return 0 OK ++ * \return ENOMEM No memory for structures available ++ * \return -1 Error during DMA init or Ethernet address configuration. ++ * \ingroup API ++ */ ++static int svip_mii_dev_init(struct net_device *dev) ++{ ++ int i; ++ struct svip_mii_priv *priv = netdev_priv(dev); ++ ++ ++ ether_setup(dev); ++ printk(KERN_INFO DRV_NAME ": %s is up\n", dev->name); ++ dev->watchdog_timeo = 10 * HZ; ++ memset(priv, 0, sizeof(*priv)); ++ priv->dma_device = dma_device_reserve("SW"); ++ if (!priv->dma_device) { ++ BUG(); ++ return -ENODEV; ++ } ++ priv->dma_device->buffer_alloc = svip_etop_dma_buffer_alloc; ++ priv->dma_device->buffer_free = svip_etop_dma_buffer_free; ++ priv->dma_device->intr_handler = dma_intr_handler; ++ ++ for (i = 0; i < priv->dma_device->max_rx_chan_num; i++) ++ priv->dma_device->rx_chan[i]->packet_size = ++ ETHERNET_PACKET_DMA_BUFFER_SIZE; ++ ++ for (i = 0; i < priv->dma_device->max_tx_chan_num; i++) { ++ priv->dma_device->tx_chan[i]->tx_weight=DEFAULT_SW_CHANNEL_WEIGHT; ++ priv->dma_device->tx_chan[i]->packet_size = ++ ETHERNET_PACKET_DMA_BUFFER_SIZE; ++ } ++ ++ dma_device_register(priv->dma_device); ++ ++ printk(KERN_INFO DRV_NAME ": using mac="); ++ ++ for (i = 0; i < 6; i++) { ++ dev->dev_addr[i] = mac_addr[i]; ++ printk("%02X%c", dev->dev_addr[i], (i == 5) ? ('\n') : (':')); ++ } ++ ++ return 0; ++} ++ ++static void svip_mii_chip_init(int mode) ++{ ++} ++ ++static int svip_mii_probe(struct platform_device *dev) ++{ ++ int result = 0; ++ unsigned char *mac = (unsigned char *)dev->dev.platform_data; ++ svip_mii0_dev = alloc_etherdev(sizeof(struct svip_mii_priv)); ++ svip_mii0_dev->netdev_ops = &svip_eth_netdev_ops; ++ memcpy(mac_addr, mac, 6); ++ strcpy(svip_mii0_dev->name, "eth%d"); ++ svip_mii_chip_init(REV_MII_MODE); ++ result = register_netdev(svip_mii0_dev); ++ if (result) { ++ printk(KERN_INFO DRV_NAME ++ ": error %i registering device \"%s\"\n", ++ result, svip_mii0_dev->name); ++ goto out; ++ } ++ printk(KERN_INFO DRV_NAME ": driver loaded!\n"); ++ ++out: ++ return result; ++} ++ ++static int svip_mii_remove(struct platform_device *dev) ++{ ++ struct svip_mii_priv *priv = netdev_priv(svip_mii0_dev); ++ ++ printk(KERN_INFO DRV_NAME ": cleanup\n"); ++ ++ dma_device_unregister(priv->dma_device); ++ dma_device_release(priv->dma_device); ++ kfree(priv->dma_device); ++ unregister_netdev(svip_mii0_dev); ++ free_netdev(svip_mii0_dev); ++ return 0; ++} ++ ++ ++static struct platform_driver svip_mii_driver = { ++ .probe = svip_mii_probe, ++ .remove = svip_mii_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++ ++/** ++ * Initialize switch driver as module. ++ * This functions initializes the switch driver structures and registers the ++ * Ethernet device for module usage. ++ * ++ * \return 0 OK ++ * \return ENODEV An error occured during initialization ++ * \ingroup API ++ */ ++int __init svip_mii_init(void) ++{ ++ int ret = platform_driver_register(&svip_mii_driver); ++ if (ret) ++ printk(KERN_INFO DRV_NAME ++ ": Error registering platfom driver!\n"); ++ return ret; ++} ++ ++ ++/** ++ * Remove driver module. ++ * This functions removes the driver and unregisters all devices. ++ * ++ * \ingroup API ++ */ ++static void __exit svip_mii_cleanup(void) ++{ ++ platform_driver_unregister(&svip_mii_driver); ++} ++ ++module_init(svip_mii_init); ++module_exit(svip_mii_cleanup); ++ ++MODULE_LICENSE("GPL"); +Index: linux-3.3.8/arch/mips/lantiq/svip/mux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/mux.c 2012-07-31 19:51:34.149105918 +0200 +@@ -0,0 +1,187 @@ ++/************************************************************************ ++ * ++ * Copyright (c) 2007 ++ * Infineon Technologies AG ++ * St. Martin Strasse 53; 81669 Muenchen; Germany ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ ************************************************************************/ ++ ++#include <linux/module.h> ++#include <linux/types.h> ++#include <linux/kernel.h> ++#include <linux/proc_fs.h> ++#include <linux/init.h> ++#include <asm/addrspace.h> ++#include <linux/platform_device.h> ++ ++#include <lantiq_soc.h> ++#include <svip_mux.h> ++#include <sys1_reg.h> ++#include <sys2_reg.h> ++#include <svip_pms.h> ++ ++#define DRV_NAME "ltq_mux" ++ ++static void ltq_mux_port_init(const int port, ++ const struct ltq_mux_pin *pins, ++ const int pin_max) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < pin_max; i++) ++ ltq_gpio_configure(port, ++ i, ++ pins[i].dirin, ++ pins[i].puen, ++ pins[i].altsel0, ++ pins[i].altsel1); ++} ++ ++static int ltq_mux_probe(struct platform_device *pdev) ++{ ++ struct ltq_mux_settings *mux_settings = dev_get_platdata(&pdev->dev); ++ ++ if (mux_settings->mux_p0) ++ ltq_mux_port_init(0, ++ mux_settings->mux_p0, ++ LTQ_MUX_P0_PINS); ++ ++ if (mux_settings->mux_p1) ++ ltq_mux_port_init(1, ++ mux_settings->mux_p1, ++ LTQ_MUX_P1_PINS); ++ ++ if (mux_settings->mux_p2) ++ ltq_mux_port_init(2, ++ mux_settings->mux_p2, ++ LTQ_MUX_P2_PINS); ++ ++ if (mux_settings->mux_p3) ++ ltq_mux_port_init(3, ++ mux_settings->mux_p3, ++ LTQ_MUX_P3_PINS); ++ ++ if (mux_settings->mux_p4) ++ ltq_mux_port_init(4, ++ mux_settings->mux_p4, ++ LTQ_MUX_P4_PINS); ++ ++ return 0; ++} ++ ++int ltq_mux_read_procmem(char *buf, char **start, off_t offset, ++ int count, int *eof, void *data) ++{ ++ int len = 0; ++ int t = 0, i = 0; ++ u32 port_clk[5] = { ++ SYS1_CLKENR_PORT0, ++ SYS1_CLKENR_PORT1, ++ SYS1_CLKENR_PORT2, ++ SYS1_CLKENR_PORT3, ++ SYS2_CLKENR_PORT4, ++ }; ++ ++#define PROC_PRINT(fmt, args...) \ ++ do { \ ++ int c_len = 0; \ ++ c_len = snprintf(buf + len, count - len, fmt, ## args); \ ++ if (c_len <= 0) \ ++ goto out; \ ++ if (c_len >= (count - len)) { \ ++ len += (count - len); \ ++ goto out; \ ++ } \ ++ len += c_len; \ ++ if (offset > 0) { \ ++ if (len > offset) { \ ++ len -= offset; \ ++ memmove(buf, buf + offset, len); \ ++ offset = 0; \ ++ } else { \ ++ offset -= len; \ ++ len = 0; \ ++ } \ ++ } \ ++ } while (0) ++ ++ PROC_PRINT("\nVINETIC-SVIP Multiplex Settings\n"); ++ PROC_PRINT(" 3 2 1 0\n"); ++ PROC_PRINT(" 10987654321098765432109876543210\n"); ++ PROC_PRINT(" --------------------------------\n"); ++ ++ for (i = 0; i < ARRAY_SIZE(port_clk); i++) { ++ if (i < 4) { ++ if (!svip_sys1_clk_is_enabled(port_clk[i])) ++ continue; ++ } else { ++ if (!svip_sys2_clk_is_enabled(port_clk[i])) ++ continue; ++ } ++ ++ PROC_PRINT("P%d.%-10s", i, "DIR:"); ++ ++ for (t = 31; t != -1; t--) ++ PROC_PRINT("%d", ltq_port_get_dir(i, t) == 1 ? 1 : 0); ++ PROC_PRINT("\n"); ++ ++ PROC_PRINT("P%d.%-10s", i, "PUEN:"); ++ for (t = 31; t != -1; t--) ++ PROC_PRINT("%d", ltq_port_get_puden(i, t) == 1 ? 1 : 0); ++ PROC_PRINT("\n"); ++ ++ PROC_PRINT("P%d.%-10s", i, "ALTSEL0:"); ++ for (t = 31; t != -1; t--) ++ PROC_PRINT("%d", ++ ltq_port_get_altsel0(i, t) == 1 ? 1 : 0); ++ PROC_PRINT("\n"); ++ ++ PROC_PRINT("P%d.%-10s", i, "ALTSEL1:"); ++ for (t = 31; t != -1; t--) ++ PROC_PRINT("%d", ++ ltq_port_get_altsel1(i, t) == 1 ? 1 : 0); ++ PROC_PRINT("\n\n"); ++ } ++ ++out: ++ if (len < 0) { ++ len = 0; ++ *eof = 1; ++ } else if (len < count) { ++ *eof = 1; ++ } else { ++ len = count; ++ } ++ ++ *start = buf; ++ ++ return len; ++} ++ ++static struct platform_driver ltq_mux_driver = { ++ .probe = ltq_mux_probe, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int __init ltq_mux_init(void) ++{ ++ int ret = platform_driver_register(<q_mux_driver); ++ if (ret) { ++ printk(KERN_INFO DRV_NAME ++ ": Error registering platform driver!"); ++ return ret; ++ } ++ ++ return create_proc_read_entry("driver/ltq_mux", 0, NULL, ++ ltq_mux_read_procmem, NULL) == NULL; ++} ++ ++module_init(ltq_mux_init); +Index: linux-3.3.8/arch/mips/lantiq/svip/pms.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/pms.c 2012-07-31 19:51:34.149105918 +0200 +@@ -0,0 +1,101 @@ ++/************************************************************************ ++ * ++ * Copyright (c) 2007 ++ * Infineon Technologies AG ++ * St. Martin Strasse 53; 81669 Muenchen; Germany ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ ************************************************************************/ ++ ++#include <linux/module.h> ++#include <linux/types.h> ++#include <linux/kernel.h> ++#include <linux/proc_fs.h> ++#include <linux/init.h> ++#include <asm/addrspace.h> ++ ++#include <base_reg.h> ++#include <sys1_reg.h> ++#include <sys2_reg.h> ++#include <lantiq_soc.h> ++ ++static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; ++static struct svip_reg_sys2 *const sys2 = (struct svip_reg_sys2 *)LTQ_SYS2_BASE; ++ ++void svip_sys1_clk_enable(u32 mask) ++{ ++ sys1_w32(sys1_r32(clksr) | mask, clkenr); ++ asm("sync;"); ++} ++EXPORT_SYMBOL(svip_sys1_clk_enable); ++ ++int svip_sys1_clk_is_enabled(u32 mask) ++{ ++ return (sys1_r32(clksr) & mask) != 0; ++} ++EXPORT_SYMBOL(svip_sys1_clk_is_enabled); ++ ++void svip_sys2_clk_enable(u32 mask) ++{ ++ sys2_w32(sys2_r32(clksr) | mask, clkenr); ++ asm("sync;"); ++} ++EXPORT_SYMBOL(svip_sys2_clk_enable); ++ ++int svip_sys2_clk_is_enabled(u32 mask) ++{ ++ return (sys2_r32(clksr) & mask) != 0; ++} ++EXPORT_SYMBOL(svip_sys2_clk_is_enabled); ++ ++int ltq_pms_read_procmem(char *buf, char **start, off_t offset, ++ int count, int *eof, void *data) ++{ ++ long len = 0; ++ int t = 0; ++ u32 bit = 0; ++ u32 reg_tmp, bits_tmp; ++ ++ len = sprintf(buf, "\nSVIP PMS Settings\n"); ++ len = len + sprintf(buf + len, ++ " 3 2 1 0\n"); ++ len = len + sprintf(buf + len, ++ " 210987654321098765432109876543210\n"); ++ len = len + sprintf(buf + len, ++ "---------------------------------------------\n"); ++ len = len + sprintf(buf + len, ++ "SYS1_CLKSR: "); ++ reg_tmp = sys1_r32(clksr); ++ bit = 0x80000000; ++ for (t = 31; t != -1; t--) { ++ bits_tmp = (reg_tmp & bit) >> t; ++ len = len + sprintf(buf + len, "%d", bits_tmp); ++ bit = bit >> 1; ++ } ++ len = len + sprintf(buf + len, "\n\n"); ++ len = len + sprintf(buf + len, "SYS2_CLKSR: "); ++ reg_tmp = sys2_r32(clksr); ++ bit = 0x80000000; ++ for (t = 31; t != -1; t--) { ++ bits_tmp = (reg_tmp & bit) >> t; ++ len = len + sprintf(buf + len, "%d", bits_tmp); ++ bit = bit >> 1; ++ } ++ len = len + sprintf(buf + len, "\n\n"); ++ ++ *eof = 1; ++ ++ return len; ++} ++ ++int __init ltq_pms_init_proc(void) ++{ ++ return create_proc_read_entry("driver/ltq_pms", 0, NULL, ++ ltq_pms_read_procmem, NULL) == NULL; ++} ++ ++module_init(ltq_pms_init_proc); +Index: linux-3.3.8/drivers/spi/spi_svip.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/drivers/spi/spi_svip.c 2012-07-31 19:51:34.149105918 +0200 +@@ -0,0 +1,955 @@ ++/************************************************************************ ++ * ++ * Copyright (c) 2008 ++ * Infineon Technologies AG ++ * St. Martin Strasse 53; 81669 Muenchen; Germany ++ * ++ * Inspired by Atmel AT32/AT91 SPI Controller driver ++ * Copyright (c) 2006 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ ************************************************************************/ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/delay.h> ++#include <linux/interrupt.h> ++#include <linux/slab.h> ++#include <linux/platform_device.h> ++#include <linux/spi/spi.h> ++ ++#include <asm/io.h> ++ ++#include <status_reg.h> ++#include <base_reg.h> ++#include <ssc_reg.h> ++#include <sys0_reg.h> ++#include <sys1_reg.h> ++ ++#define SFRAME_SIZE 512 /* bytes */ ++#define FIFO_HEADROOM 2 /* words */ ++ ++#define SVIP_SSC_RFIFO_WORDS 8 ++ ++enum svip_ssc_dir { ++ SSC_RXTX, ++ SSC_RX, ++ SSC_TX, ++ SSC_UNDEF ++}; ++ ++/* ++ * The core SPI transfer engine just talks to a register bank to set up ++ * DMA transfers; transfer queue progress is driven by IRQs. The clock ++ * framework provides the base clock, subdivided for each spi_device. ++ */ ++struct svip_ssc_device { ++ struct svip_reg_ssc *regs; ++ enum svip_ssc_dir bus_dir; ++ struct spi_device *stay; ++ ++ u8 stopping; ++ struct list_head queue; ++ struct spi_transfer *current_transfer; ++ int remaining_bytes; ++ int rx_bytes; ++ int tx_bytes; ++ ++ char intname[4][16]; ++ ++ spinlock_t lock; ++}; ++ ++static int svip_ssc_setup(struct spi_device *spi); ++ ++extern unsigned int ltq_get_fbs0_hz(void); ++ ++static void cs_activate(struct svip_ssc_device *ssc_dev, struct spi_device *spi) ++{ ++ ssc_dev->regs->whbgpostat = 0x0001 << spi->chip_select; /* activate the chip select */ ++} ++ ++static void cs_deactivate(struct svip_ssc_device *ssc_dev, struct spi_device *spi) ++{ ++ ssc_dev->regs->whbgpostat = 0x0100 << spi->chip_select; /* deactivate the chip select */ ++} ++ ++/* ++ * "Normally" returns Byte Valid = 4. ++ * If the unaligned remainder of the packet is 3 bytes, these have to be ++ * transferred as a combination of a 16-bit and a 8-bit FPI transfer. For ++ * 2 or 1 remaining bytes a single 16-bit or 8-bit transfer will do. ++ */ ++static int inline _estimate_bv(int byte_pos, int bytelen) ++{ ++ int remainder = bytelen % 4; ++ ++ if (byte_pos < (bytelen - remainder)) ++ return 4; ++ ++ if (remainder == 3) ++ { ++ if (byte_pos == (bytelen - remainder)) ++ return 2; ++ else ++ return 1; ++ } ++ return remainder; ++} ++ ++/* ++ * Submit next transfer. ++ * lock is held, spi irq is blocked ++ */ ++static void svip_ssc_next_xfer(struct spi_master *master, ++ struct spi_message *msg) ++{ ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ struct spi_transfer *xfer; ++ unsigned char *buf_ptr; ++ ++ xfer = ssc_dev->current_transfer; ++ if (!xfer || ssc_dev->remaining_bytes == 0) { ++ if (xfer) ++ xfer = list_entry(xfer->transfer_list.next, ++ struct spi_transfer, transfer_list); ++ else ++ xfer = list_entry(msg->transfers.next, ++ struct spi_transfer, transfer_list); ++ ssc_dev->remaining_bytes = xfer->len; ++ ssc_dev->rx_bytes = 0; ++ ssc_dev->tx_bytes = 0; ++ ssc_dev->current_transfer = xfer; ++ ssc_dev->regs->sfcon = 0; /* reset Serial Framing */ ++ ++ /* enable and flush RX/TX FIFO */ ++ ssc_dev->regs->rxfcon = ++ SSC_RXFCON_RXFITL_VAL(SVIP_SSC_RFIFO_WORDS-FIFO_HEADROOM) | ++ SSC_RXFCON_RXFLU | /* Receive FIFO Flush */ ++ SSC_RXFCON_RXFEN; /* Receive FIFO Enable */ ++ ++ ssc_dev->regs->txfcon = ++ SSC_TXFCON_TXFITL_VAL(FIFO_HEADROOM) | ++ SSC_TXFCON_TXFLU | /* Transmit FIFO Flush */ ++ SSC_TXFCON_TXFEN; /* Transmit FIFO Enable */ ++ ++ asm("sync"); ++ ++ /* select mode RXTX, RX or TX */ ++ if (xfer->rx_buf && xfer->tx_buf) /* RX and TX */ ++ { ++ if (ssc_dev->bus_dir != SSC_RXTX) ++ { ++ ssc_dev->regs->mcon &= ~(SSC_MCON_RXOFF | SSC_MCON_TXOFF); ++ ssc_dev->bus_dir = SSC_RXTX; ++ ssc_dev->regs->irnen = SSC_IRNEN_T | SSC_IRNEN_F | SSC_IRNEN_E; ++ } ++ ssc_dev->regs->sfcon = ++ SSC_SFCON_PLEN_VAL(0) | ++ SSC_SFCON_DLEN_VAL(((xfer->len-1)%SFRAME_SIZE)*8+7) | ++ SSC_SFCON_STOP | ++ SSC_SFCON_ICLK_VAL(2) | ++ SSC_SFCON_IDAT_VAL(2) | ++ SSC_SFCON_IAEN | ++ SSC_SFCON_SFEN; ++ ++ } ++ else if (xfer->rx_buf) /* RX only */ ++ { ++ if (ssc_dev->bus_dir != SSC_RX) ++ { ++ ssc_dev->regs->mcon = ++ (ssc_dev->regs->mcon | SSC_MCON_TXOFF) & ~SSC_MCON_RXOFF; ++ ++ ssc_dev->bus_dir = SSC_RX; ++ ++ ssc_dev->regs->irnen = SSC_IRNEN_R | SSC_IRNEN_E; ++ } ++ /* Initiate clock generation for Rx-Only Transfer. In case of RX-only transfer, ++ * rx_bytes represents the number of already requested bytes. ++ */ ++ ssc_dev->rx_bytes = min(xfer->len, (unsigned)(SVIP_SSC_RFIFO_WORDS*4)); ++ ssc_dev->regs->rxreq = ssc_dev->rx_bytes; ++ } ++ else /* TX only */ ++ { ++ if (ssc_dev->bus_dir != SSC_TX) ++ { ++ ssc_dev->regs->mcon = ++ (ssc_dev->regs->mcon | SSC_MCON_RXOFF) & ~SSC_MCON_TXOFF; ++ ++ ssc_dev->bus_dir = SSC_TX; ++ ++ ssc_dev->regs->irnen = ++ SSC_IRNEN_T | SSC_IRNEN_F | SSC_IRNEN_E; ++ } ++ ssc_dev->regs->sfcon = ++ SSC_SFCON_PLEN_VAL(0) | ++ SSC_SFCON_DLEN_VAL(((xfer->len-1)%SFRAME_SIZE)*8+7) | ++ SSC_SFCON_STOP | ++ SSC_SFCON_ICLK_VAL(2) | ++ SSC_SFCON_IDAT_VAL(2) | ++ SSC_SFCON_IAEN | ++ SSC_SFCON_SFEN; ++ } ++ } ++ ++ if (xfer->tx_buf) ++ { ++ int outstanding; ++ int i; ++ int fstat = ssc_dev->regs->fstat; ++ int txffl = SSC_FSTAT_TXFFL_GET(fstat); ++ int rxffl = SSC_FSTAT_RXFFL_GET(fstat); ++ ++ outstanding = txffl; ++ ++ if (xfer->rx_buf) ++ { ++ outstanding += rxffl; ++ if (SSC_STATE_BSY_GET(ssc_dev->regs->state)) ++ outstanding++; ++ ++ while (rxffl) /* is 0 in TX-Only mode */ ++ { ++ unsigned int rb; ++ int rxbv = _estimate_bv(ssc_dev->rx_bytes, xfer->len); ++ rb = ssc_dev->regs->rb; ++ for (i=0; i<rxbv; i++) ++ { ++ ((unsigned char*)xfer->rx_buf)[ssc_dev->rx_bytes] = ++ (rb >> ((rxbv-i-1)*8)) & 0xFF; ++ ++ ssc_dev->rx_bytes++; ++ } ++ rxffl--; ++ outstanding--; ++ } ++ ssc_dev->remaining_bytes = xfer->len - ssc_dev->rx_bytes; ++ } ++ ++ /* for last Tx cycle set TxFifo threshold to 0 */ ++ if ((xfer->len - ssc_dev->tx_bytes) <= ++ (4*(SVIP_SSC_RFIFO_WORDS-1-outstanding))) ++ { ++ ssc_dev->regs->txfcon = SSC_TXFCON_TXFITL_VAL(0) | ++ SSC_TXFCON_TXFEN; ++ } ++ ++ while ((ssc_dev->tx_bytes < xfer->len) && ++ (outstanding < (SVIP_SSC_RFIFO_WORDS-1))) ++ { ++ unsigned int tb = 0; ++ int txbv = _estimate_bv(ssc_dev->tx_bytes, xfer->len); ++ ++ for (i=0; i<txbv; i++) ++ { ++ tb |= ((unsigned char*)xfer->tx_buf)[ssc_dev->tx_bytes] << ++ ((txbv-i-1)*8); ++ ++ ssc_dev->tx_bytes++; ++ } ++ switch(txbv) ++ { ++#ifdef __BIG_ENDIAN ++ case 1: ++ *((unsigned char *)(&(ssc_dev->regs->tb))+3) = tb & 0xFF; ++ break; ++ case 2: ++ *((unsigned short *)(&(ssc_dev->regs->tb))+1) = tb & 0xFFFF; ++ break; ++#else /* __LITTLE_ENDIAN */ ++ case 1: ++ *((unsigned char *)(&(ssc_dev->regs->tb))) = tb & 0xFF; ++ break; ++ case 2: ++ *((unsigned short *)(&(ssc_dev->regs->tb))) = tb & 0xFFFF; ++ break; ++#endif ++ default: ++ ssc_dev->regs->tb = tb; ++ } ++ outstanding++; ++ } ++ } ++ else /* xfer->tx_buf == NULL -> RX only! */ ++ { ++ int j; ++ int rxffl = SSC_FSTAT_RXFFL_GET(ssc_dev->regs->fstat); ++ int rxbv = 0; ++ unsigned int rbuf; ++ ++ buf_ptr = (unsigned char*)xfer->rx_buf + ++ (xfer->len - ssc_dev->remaining_bytes); ++ ++ for (j = 0; j < rxffl; j++) ++ { ++ rxbv = SSC_STATE_RXBV_GET(ssc_dev->regs->state); ++ rbuf = ssc_dev->regs->rb; ++ ++ if (rxbv == 4) ++ { ++ *((unsigned int*)buf_ptr+j) = ntohl(rbuf); ++ } ++ else ++ { ++ int b; ++#ifdef __BIG_ENDIAN ++ for (b = 0; b < rxbv; b++) ++ { ++ buf_ptr[4*j+b] = ((unsigned char*)(&rbuf))[4-rxbv+b]; ++ } ++#else /* __LITTLE_ENDIAN */ ++ for (b = 0; b < rxbv; b++) ++ { ++ buf_ptr[4*j+b] = ((unsigned char*)(&rbuf))[rxbv-1-b]; ++ } ++#endif ++ } ++ ssc_dev->remaining_bytes -= rxbv; ++ } ++ if ((ssc_dev->rx_bytes < xfer->len) && ++ !SSC_STATE_BSY_GET(ssc_dev->regs->state)) ++ { ++ int rxreq = min(xfer->len - ssc_dev->rx_bytes, ++ (unsigned)(SVIP_SSC_RFIFO_WORDS*4)); ++ ++ ssc_dev->rx_bytes += rxreq; ++ ssc_dev->regs->rxreq = rxreq; ++ } ++ ++ if (ssc_dev->remaining_bytes < 0) ++ { ++ printk("ssc_dev->remaining_bytes = %d! xfer->len = %d, " ++ "rxffl=%d, rxbv=%d\n", ssc_dev->remaining_bytes, xfer->len, ++ rxffl, rxbv); ++ ++ ssc_dev->remaining_bytes = 0; ++ } ++ } ++} ++ ++/* ++ * Submit next message. ++ * lock is held ++ */ ++static void svip_ssc_next_message(struct spi_master *master) ++{ ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ struct spi_message *msg; ++ struct spi_device *spi; ++ ++ BUG_ON(ssc_dev->current_transfer); ++ ++ msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); ++ spi = msg->spi; ++ ++ dev_dbg(master->dev.parent, "start message %p on %p\n", msg, spi); ++ ++ /* select chip if it's not still active */ ++ if (ssc_dev->stay) { ++ if (ssc_dev->stay != spi) { ++ cs_deactivate(ssc_dev, ssc_dev->stay); ++ svip_ssc_setup(spi); ++ cs_activate(ssc_dev, spi); ++ } ++ ssc_dev->stay = NULL; ++ } ++ else { ++ svip_ssc_setup(spi); ++ cs_activate(ssc_dev, spi); ++ } ++ ++ svip_ssc_next_xfer(master, msg); ++} ++ ++/* ++ * Report message completion. ++ * lock is held ++ */ ++static void ++svip_ssc_msg_done(struct spi_master *master, struct svip_ssc_device *ssc_dev, ++ struct spi_message *msg, int status, int stay) ++{ ++ if (!stay || status < 0) ++ cs_deactivate(ssc_dev, msg->spi); ++ else ++ ssc_dev->stay = msg->spi; ++ ++ list_del(&msg->queue); ++ msg->status = status; ++ ++ dev_dbg(master->dev.parent, ++ "xfer complete: %u bytes transferred\n", ++ msg->actual_length); ++ ++ spin_unlock(&ssc_dev->lock); ++ msg->complete(msg->context); ++ spin_lock(&ssc_dev->lock); ++ ++ ssc_dev->current_transfer = NULL; ++ ++ /* continue if needed */ ++ if (list_empty(&ssc_dev->queue) || ssc_dev->stopping) ++ ; /* TODO: disable hardware */ ++ else ++ svip_ssc_next_message(master); ++} ++ ++static irqreturn_t svip_ssc_eir_handler(int irq, void *dev_id) ++{ ++ struct platform_device *pdev = (struct platform_device*)dev_id; ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ ++ dev_err (&pdev->dev, "ERROR: errirq. STATE = 0x%0lx\n", ++ ssc_dev->regs->state); ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t svip_ssc_rir_handler(int irq, void *dev_id) ++{ ++ struct platform_device *pdev = (struct platform_device*)dev_id; ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ struct spi_message *msg; ++ struct spi_transfer *xfer; ++ ++ xfer = ssc_dev->current_transfer; ++ msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); ++ ++ /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt ++ * handler for spurious Interrupts! ++ */ ++ if (!xfer) { ++ dev_dbg(master->dev.parent, ++ "%s(%d): xfer = NULL\n", __FUNCTION__, irq); ++ goto out; ++ } ++ if ( !(xfer->rx_buf) ) { ++ dev_dbg(master->dev.parent, ++ "%s(%d): xfer->rx_buf = NULL\n", __FUNCTION__, irq); ++ goto out; ++ } ++ if (ssc_dev->remaining_bytes > 0) ++ { ++ /* ++ * Keep going, we still have data to send in ++ * the current transfer. ++ */ ++ svip_ssc_next_xfer(master, msg); ++ } ++ ++ if (ssc_dev->remaining_bytes == 0) ++ { ++ msg->actual_length += xfer->len; ++ ++ if (msg->transfers.prev == &xfer->transfer_list) { ++ /* report completed message */ ++ svip_ssc_msg_done(master, ssc_dev, msg, 0, ++ xfer->cs_change); ++ } ++ else { ++ if (xfer->cs_change) { ++ cs_deactivate(ssc_dev, msg->spi); ++ udelay(1); /* not nice in interrupt context */ ++ cs_activate(ssc_dev, msg->spi); ++ } ++ ++ /* Not done yet. Submit the next transfer. */ ++ svip_ssc_next_xfer(master, msg); ++ } ++ } ++out: ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t svip_ssc_tir_handler(int irq, void *dev_id) ++{ ++ struct platform_device *pdev = (struct platform_device*)dev_id; ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ struct spi_message *msg; ++ struct spi_transfer *xfer; ++ int tx_remain; ++ ++ xfer = ssc_dev->current_transfer; ++ msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); ++ ++ /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt ++ * handler for spurious Interrupts! ++ */ ++ if (!xfer) { ++ dev_dbg(master->dev.parent, ++ "%s(%d): xfer = NULL\n", __FUNCTION__, irq); ++ goto out; ++ } ++ if ( !(xfer->tx_buf) ) { ++ dev_dbg(master->dev.parent, ++ "%s(%d): xfer->tx_buf = NULL\n", __FUNCTION__, irq); ++ goto out; ++ } ++ ++ if (ssc_dev->remaining_bytes > 0) ++ { ++ tx_remain = xfer->len - ssc_dev->tx_bytes; ++ if ( tx_remain == 0 ) ++ { ++ dev_dbg(master->dev.parent, ++ "%s(%d): tx_remain = 0\n", __FUNCTION__, irq); ++ } ++ else ++ /* ++ * Keep going, we still have data to send in ++ * the current transfer. ++ */ ++ svip_ssc_next_xfer(master, msg); ++ } ++out: ++ return IRQ_HANDLED; ++} ++ ++static irqreturn_t svip_ssc_fir_handler(int irq, void *dev_id) ++{ ++ struct platform_device *pdev = (struct platform_device*)dev_id; ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ struct spi_message *msg; ++ struct spi_transfer *xfer; ++ ++ xfer = ssc_dev->current_transfer; ++ msg = list_entry(ssc_dev->queue.next, struct spi_message, queue); ++ ++ /* Tx and Rx Interrupts are fairly unpredictable. Just leave interrupt ++ * handler for spurious Interrupts! ++ */ ++ if (!xfer) { ++ dev_dbg(master->dev.parent, ++ "%s(%d): xfer = NULL\n", __FUNCTION__, irq); ++ goto out; ++ } ++ if ( !(xfer->tx_buf) ) { ++ dev_dbg(master->dev.parent, ++ "%s(%d): xfer->tx_buf = NULL\n", __FUNCTION__, irq); ++ goto out; ++ } ++ ++ if (ssc_dev->remaining_bytes > 0) ++ { ++ int tx_remain = xfer->len - ssc_dev->tx_bytes; ++ ++ if (tx_remain == 0) ++ { ++ /* Frame interrupt gets raised _before_ last Rx interrupt */ ++ if (xfer->rx_buf) ++ { ++ svip_ssc_next_xfer(master, msg); ++ if (ssc_dev->remaining_bytes) ++ printk("expected RXTX transfer to be complete!\n"); ++ } ++ ssc_dev->remaining_bytes = 0; ++ } ++ else ++ { ++ ssc_dev->regs->sfcon = SSC_SFCON_PLEN_VAL(0) | ++ SSC_SFCON_DLEN_VAL(SFRAME_SIZE*8-1) | ++ SSC_SFCON_STOP | ++ SSC_SFCON_ICLK_VAL(2) | ++ SSC_SFCON_IDAT_VAL(2) | ++ SSC_SFCON_IAEN | ++ SSC_SFCON_SFEN; ++ } ++ } ++ ++ if (ssc_dev->remaining_bytes == 0) ++ { ++ msg->actual_length += xfer->len; ++ ++ if (msg->transfers.prev == &xfer->transfer_list) { ++ /* report completed message */ ++ svip_ssc_msg_done(master, ssc_dev, msg, 0, ++ xfer->cs_change); ++ } ++ else { ++ if (xfer->cs_change) { ++ cs_deactivate(ssc_dev, msg->spi); ++ udelay(1); /* not nice in interrupt context */ ++ cs_activate(ssc_dev, msg->spi); ++ } ++ ++ /* Not done yet. Submit the next transfer. */ ++ svip_ssc_next_xfer(master, msg); ++ } ++ } ++ ++out: ++ return IRQ_HANDLED; ++} ++ ++/* the spi->mode bits understood by this driver: */ ++#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP) ++ ++static int svip_ssc_setup(struct spi_device *spi) ++{ ++ struct spi_master *master = spi->master; ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ unsigned int bits = spi->bits_per_word; ++ unsigned int br, sck_hz = spi->max_speed_hz; ++ unsigned long flags; ++ ++ if (ssc_dev->stopping) ++ return -ESHUTDOWN; ++ ++ if (spi->chip_select >= master->num_chipselect) { ++ dev_dbg(&spi->dev, ++ "setup: invalid chipselect %u (%u defined)\n", ++ spi->chip_select, master->num_chipselect); ++ return -EINVAL; ++ } ++ ++ if (bits == 0) ++ bits = 8; ++ if (bits != 8) { ++ dev_dbg(&spi->dev, ++ "setup: invalid bits_per_word %u (expect 8)\n", ++ bits); ++ return -EINVAL; ++ } ++ ++ if (spi->mode & ~MODEBITS) { ++ dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", ++ spi->mode & ~MODEBITS); ++ return -EINVAL; ++ } ++ ++ /* Disable SSC */ ++ ssc_dev->regs->whbstate = SSC_WHBSTATE_CLREN; ++ ++ if (sck_hz == 0) ++ sck_hz = 10000; ++ ++ br = ltq_get_fbs0_hz()/(2 *sck_hz); ++ if (ltq_get_fbs0_hz()%(2 *sck_hz) == 0) ++ br = br -1; ++ ssc_dev->regs->br = br; ++ ++ /* set Control Register */ ++ ssc_dev->regs->mcon = SSC_MCON_ENBV | ++ SSC_MCON_RUEN | ++ SSC_MCON_TUEN | ++ SSC_MCON_AEN | ++ SSC_MCON_REN | ++ SSC_MCON_TEN | ++ (spi->mode & SPI_CPOL ? SSC_MCON_PO : 0) | /* Clock Polarity */ ++ (spi->mode & SPI_CPHA ? 0 : SSC_MCON_PH) | /* Tx on trailing edge */ ++ (spi->mode & SPI_LOOP ? SSC_MCON_LB : 0) | /* Loopback */ ++ (spi->mode & SPI_LSB_FIRST ? 0 : SSC_MCON_HB); /* MSB first */ ++ ssc_dev->bus_dir = SSC_UNDEF; ++ ++ /* Enable SSC */ ++ ssc_dev->regs->whbstate = SSC_WHBSTATE_SETEN; ++ asm("sync"); ++ ++ spin_lock_irqsave(&ssc_dev->lock, flags); ++ if (ssc_dev->stay == spi) ++ ssc_dev->stay = NULL; ++ cs_deactivate(ssc_dev, spi); ++ spin_unlock_irqrestore(&ssc_dev->lock, flags); ++ ++ dev_dbg(&spi->dev, ++ "setup: %u Hz bpw %u mode 0x%02x cs %u\n", ++ sck_hz, bits, spi->mode, spi->chip_select); ++ ++ return 0; ++} ++ ++static int svip_ssc_transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct spi_master *master = spi->master; ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ struct spi_transfer *xfer; ++ unsigned long flags; ++ ++ dev_dbg(&spi->dev, "new message %p submitted\n", msg); ++ ++ if (unlikely(list_empty(&msg->transfers) ++ || !spi->max_speed_hz)) { ++ return -EINVAL; ++ } ++ ++ if (ssc_dev->stopping) ++ return -ESHUTDOWN; ++ ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ if (!(xfer->tx_buf || xfer->rx_buf) || (xfer->len == 0)) { ++ dev_dbg(&spi->dev, "missing rx or tx buf\n"); ++ return -EINVAL; ++ } ++ ++ /* FIXME implement these protocol options!! */ ++ if (xfer->bits_per_word || xfer->speed_hz) { ++ dev_dbg(&spi->dev, "no protocol options yet\n"); ++ return -ENOPROTOOPT; ++ } ++ ++#ifdef VERBOSE ++ dev_dbg(spi->dev, ++ " xfer %p: len %u tx %p/%08x rx %p/%08x\n", ++ xfer, xfer->len, ++ xfer->tx_buf, xfer->tx_dma, ++ xfer->rx_buf, xfer->rx_dma); ++#endif ++ } ++ ++ msg->status = -EINPROGRESS; ++ msg->actual_length = 0; ++ ++ spin_lock_irqsave(&ssc_dev->lock, flags); ++ list_add_tail(&msg->queue, &ssc_dev->queue); ++ if (!ssc_dev->current_transfer) ++ { ++ /* start transmission machine, if not started yet */ ++ svip_ssc_next_message(master); ++ } ++ spin_unlock_irqrestore(&ssc_dev->lock, flags); ++ ++ return 0; ++} ++ ++static void svip_ssc_cleanup(struct spi_device *spi) ++{ ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(spi->master); ++ unsigned long flags; ++ ++ if (!spi->controller_state) ++ return; ++ ++ spin_lock_irqsave(&ssc_dev->lock, flags); ++ if (ssc_dev->stay == spi) { ++ ssc_dev->stay = NULL; ++ cs_deactivate(ssc_dev, spi); ++ } ++ spin_unlock_irqrestore(&ssc_dev->lock, flags); ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static int __init svip_ssc_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct spi_master *master; ++ struct svip_ssc_device *ssc_dev; ++ struct resource *res_regs; ++ int irq; ++ ++ ret = -ENOMEM; ++ ++ /* setup spi core then atmel-specific driver state */ ++ master = spi_alloc_master(&pdev->dev, sizeof (*ssc_dev)); ++ if (!master) ++ { ++ dev_err (&pdev->dev, "ERROR: no memory for master spi\n"); ++ goto errout; ++ } ++ ++ ssc_dev = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, master); ++ ++ master->bus_num = pdev->id; ++ master->num_chipselect = 8; ++ master->mode_bits = MODEBITS; ++ master->setup = svip_ssc_setup; ++ master->transfer = svip_ssc_transfer; ++ master->cleanup = svip_ssc_cleanup; ++ ++ spin_lock_init(&ssc_dev->lock); ++ INIT_LIST_HEAD(&ssc_dev->queue); ++ ++ /* retrive register configration */ ++ res_regs = platform_get_resource_byname (pdev, IORESOURCE_MEM, "regs"); ++ if (NULL == res_regs) ++ { ++ dev_err (&pdev->dev, "ERROR: missed 'regs' resource\n"); ++ goto spierr; ++ } ++ ++ ssc_dev->regs = (struct svip_reg_ssc*)KSEG1ADDR(res_regs->start); ++ ++ irq = platform_get_irq_byname (pdev, "tx"); ++ if (irq < 0) ++ goto irqerr; ++ sprintf(ssc_dev->intname[0], "%s_tx", pdev->name); ++ ret = devm_request_irq(&pdev->dev, irq, svip_ssc_tir_handler, ++ IRQF_DISABLED, ssc_dev->intname[0], pdev); ++ if (ret != 0) ++ goto irqerr; ++ ++ irq = platform_get_irq_byname (pdev, "rx"); ++ if (irq < 0) ++ goto irqerr; ++ sprintf(ssc_dev->intname[1], "%s_rx", pdev->name); ++ ret = devm_request_irq(&pdev->dev, irq, svip_ssc_rir_handler, ++ IRQF_DISABLED, ssc_dev->intname[1], pdev); ++ if (ret != 0) ++ goto irqerr; ++ ++ irq = platform_get_irq_byname (pdev, "err"); ++ if (irq < 0) ++ goto irqerr; ++ sprintf(ssc_dev->intname[2], "%s_err", pdev->name); ++ ret = devm_request_irq(&pdev->dev, irq, svip_ssc_eir_handler, ++ IRQF_DISABLED, ssc_dev->intname[2], pdev); ++ if (ret != 0) ++ goto irqerr; ++ ++ irq = platform_get_irq_byname (pdev, "frm"); ++ if (irq < 0) ++ goto irqerr; ++ sprintf(ssc_dev->intname[3], "%s_frm", pdev->name); ++ ret = devm_request_irq(&pdev->dev, irq, svip_ssc_fir_handler, ++ IRQF_DISABLED, ssc_dev->intname[3], pdev); ++ if (ret != 0) ++ goto irqerr; ++ ++ /* ++ * Initialize the Hardware ++ */ ++ ++ /* Clear enable bit, i.e. put SSC into configuration mode */ ++ ssc_dev->regs->whbstate = SSC_WHBSTATE_CLREN; ++ /* enable SSC core to run at fpi clock */ ++ ssc_dev->regs->clc = SSC_CLC_RMC_VAL(1); ++ asm("sync"); ++ ++ /* GPIO CS */ ++ ssc_dev->regs->gpocon = SSC_GPOCON_ISCSBN_VAL(0xFF); ++ ssc_dev->regs->whbgpostat = SSC_WHBGPOSTAT_SETOUTN_VAL(0xFF); /* CS to high */ ++ ++ /* Set Master mode */ ++ ssc_dev->regs->whbstate = SSC_WHBSTATE_SETMS; ++ ++ /* enable and flush RX/TX FIFO */ ++ ssc_dev->regs->rxfcon = SSC_RXFCON_RXFITL_VAL(SVIP_SSC_RFIFO_WORDS-FIFO_HEADROOM) | ++ SSC_RXFCON_RXFLU | /* Receive FIFO Flush */ ++ SSC_RXFCON_RXFEN; /* Receive FIFO Enable */ ++ ++ ssc_dev->regs->txfcon = SSC_TXFCON_TXFITL_VAL(FIFO_HEADROOM) | ++ SSC_TXFCON_TXFLU | /* Transmit FIFO Flush */ ++ SSC_TXFCON_TXFEN; /* Transmit FIFO Enable */ ++ asm("sync"); ++ ++ /* enable IRQ */ ++ ssc_dev->regs->irnen = SSC_IRNEN_E; ++ ++ dev_info(&pdev->dev, "controller at 0x%08lx (irq %d)\n", ++ (unsigned long)ssc_dev->regs, platform_get_irq_byname (pdev, "rx")); ++ ++ ret = spi_register_master(master); ++ if (ret) ++ goto out_reset_hw; ++ ++ return 0; ++ ++out_reset_hw: ++ ++irqerr: ++ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "tx"), pdev); ++ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "rx"), pdev); ++ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "err"), pdev); ++ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "frm"), pdev); ++ ++spierr: ++ ++ spi_master_put(master); ++ ++errout: ++ return ret; ++} ++ ++static int __exit svip_ssc_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ struct spi_message *msg; ++ ++ /* reset the hardware and block queue progress */ ++ spin_lock_irq(&ssc_dev->lock); ++ ssc_dev->stopping = 1; ++ /* TODO: shutdown hardware */ ++ spin_unlock_irq(&ssc_dev->lock); ++ ++ /* Terminate remaining queued transfers */ ++ list_for_each_entry(msg, &ssc_dev->queue, queue) { ++ /* REVISIT unmapping the dma is a NOP on ARM and AVR32 ++ * but we shouldn't depend on that... ++ */ ++ msg->status = -ESHUTDOWN; ++ msg->complete(msg->context); ++ } ++ ++ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "tx"), pdev); ++ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "rx"), pdev); ++ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "err"), pdev); ++ devm_free_irq (&pdev->dev, platform_get_irq_byname (pdev, "frm"), pdev); ++ ++ spi_unregister_master(master); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(master); ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int svip_ssc_suspend(struct platform_device *pdev, pm_message_t mesg) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ ++ clk_disable(ssc_dev->clk); ++ return 0; ++} ++ ++static int svip_ssc_resume(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct svip_ssc_device *ssc_dev = spi_master_get_devdata(master); ++ ++ clk_enable(ssc_dev->clk); ++ return 0; ++} ++#endif ++ ++static struct platform_driver svip_ssc_driver = { ++ .driver = { ++ .name = "ifx_ssc", ++ .owner = THIS_MODULE, ++ }, ++ .probe = svip_ssc_probe, ++#ifdef CONFIG_PM ++ .suspend = svip_ssc_suspend, ++ .resume = svip_ssc_resume, ++#endif ++ .remove = __exit_p(svip_ssc_remove) ++}; ++ ++int __init svip_ssc_init(void) ++{ ++ return platform_driver_register(&svip_ssc_driver); ++} ++ ++void __exit svip_ssc_exit(void) ++{ ++ platform_driver_unregister(&svip_ssc_driver); ++} ++ ++module_init(svip_ssc_init); ++module_exit(svip_ssc_exit); ++ ++MODULE_ALIAS("platform:ifx_ssc"); ++MODULE_DESCRIPTION("Lantiq SSC Controller driver"); ++MODULE_AUTHOR("Andreas Schmidt <andreas.schmidt@infineon.com>"); ++MODULE_AUTHOR("Jevgenijs Grigorjevs <Jevgenijs.Grigorjevs@lantiq.com>"); ++MODULE_LICENSE("GPL"); +Index: linux-3.3.8/net/ipv4/svip_nat.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/net/ipv4/svip_nat.c 2012-07-31 20:04:32.985139213 +0200 +@@ -0,0 +1,1569 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2009 ++ Lantiq Deutschland GmbH ++ Am Campeon 3; 81726 Munich, Germany ++ ++ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, ++ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS ++ SOFTWARE IS FREE OF CHARGE. ++ ++ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS ++ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING ++ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE ++ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD ++ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL ++ PROPERTY INFRINGEMENT. ++ ++ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT ++ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM ++ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ DEALINGS IN THE SOFTWARE. ++ ++ **************************************************************************** ++ ++Description : This file contains implementation of Custom NAT function ++for Infineon's VINETIC-SVIP16 ++ *******************************************************************************/ ++ ++#include <linux/module.h> ++#include <linux/netfilter_ipv4.h> ++#include <linux/if_ether.h> ++#include <linux/netdevice.h> ++#include <linux/inetdevice.h> ++#include <linux/in.h> ++#include <linux/ip.h> ++#include <linux/if_vlan.h> ++#include <linux/udp.h> ++#include <linux/kernel.h> ++#include <linux/version.h> ++#include <linux/proc_fs.h> ++#include <linux/in6.h> /* just to shut up a warning */ ++#include <linux/miscdevice.h> ++#include <asm/checksum.h> ++ ++#include <linux/svip_nat.h> ++ ++MODULE_AUTHOR("Lantiq Deutschland GmbH"); ++MODULE_DESCRIPTION("SVIP Network Address Translation module"); ++MODULE_LICENSE("GPL"); ++ ++#define SVIP_NAT_INFO_STR "@(#)SVIP NAT, version "SVIP_NAT_VERSION ++ ++/** maximum voice packet channels possible on the SVIP LC system ++ (equals maximum number of Codec channels possible) */ ++#define SVIP_SYS_CODEC_NUM ((SVIP_SYS_NUM) * (SVIP_CODEC_NUM)) ++ ++/** end UDP port number of the SVIP Linecard System */ ++#define SVIP_UDP_TO ((SVIP_UDP_FROM) + (SVIP_SYS_CODEC_NUM) - 1) ++ ++/** end UDP port number of the Master SVIP in SVIP Linecard System */ ++#define SVIP_UDP_TO_VOFW0 ((SVIP_UDP_FROM) + (SVIP_CODEC_NUM) - 1) ++ ++#define SVIP_PORT_INRANGE(nPort) \ ++ ((nPort) >= (SVIP_UDP_FROM) && (nPort) <= (SVIP_UDP_TO)) ++ ++#define SVIP_PORT_INDEX(nPort) (nPort - SVIP_UDP_FROM) ++ ++#define SVIP_NET_DEV_ETH0_IDX 0 ++#define SVIP_NET_DEV_VETH0_IDX 1 ++#define SVIP_NET_DEV_LO_IDX 2 ++ ++#define SVIP_NET_DEV_ETH0_NAME "eth0" ++#define SVIP_NET_DEV_ETH1_NAME "eth1" ++#define SVIP_NET_DEV_VETH1_NAME "veth0" ++#define SVIP_NET_DEV_LO_NAME "lo" ++ ++#define SVIP_NAT_STATS_LOC2REM 0 ++#define SVIP_NAT_STATS_REM2LOC 1 ++#define SVIP_NAT_STATS_TYPES 2 ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++#define SVIP_NAT_FOR_EACH_NETDEV(d) for_each_netdev(&init_net, dev) ++#define SVIP_NAT_IP_HDR(ethhdr) ip_hdr(ethhdr) ++#else ++#define SVIP_NAT_FOR_EACH_NETDEV(d) for(d=dev_base; dev; dev = dev->next) ++#define SVIP_NAT_IP_HDR(ethhdr) (ethhdr)->nh.iph ++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) */ ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) (ethhdr)->mac.ethernet ++#elif LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) (ethhdr)->mac.raw ++#else ++#define SVIP_NAT_SKB_MAC_HEADER(ethhdr) skb_mac_header(ethhdr) ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++#define VLAN_DEV_REAL_DEV(dev) vlan_dev_real_dev(dev) ++#define VLAN_DEV_VLAN_ID(dev) vlan_dev_vlan_id(dev) ++#else ++#define VLAN_DEV_REAL_DEV(dev) (VLAN_DEV_INFO(dev)->real_dev) ++#define VLAN_DEV_VLAN_ID(dev) (VLAN_DEV_INFO(dev)->vlan_id) ++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) */ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) ++#define MOD_INC_USE_COUNT ++#define MOD_DEC_USE_COUNT ++#endif ++ ++#if ! ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) && \ ++ (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE))) ++#define VLAN_8021Q_UNUSED ++#endif ++ ++ ++extern spinlock_t vlan_group_lock; ++extern struct net_device *__vlan_find_dev_deep(struct net_device *real_dev, unsigned short VID); ++ ++typedef struct SVIP_NAT_stats ++{ ++ unsigned long inPackets; ++ unsigned long outPackets; ++ unsigned long outErrors; ++} SVIP_NAT_stats_t; ++ ++typedef struct SVIP_NAT_table_entry ++{ ++ SVIP_NAT_IO_Rule_t natRule; ++ SVIP_NAT_stats_t natStats[SVIP_NAT_STATS_TYPES]; ++} SVIP_NAT_table_entry_t; ++ ++/* pointer to the SVIP NAT table */ ++static SVIP_NAT_table_entry_t *pNatTable = NULL; ++ ++struct net_device *net_devs[3]; ++static u32 *paddr_eth0; ++static u32 *paddr_eth0_0; ++static u32 *paddr_veth0; ++static u32 *pmask_veth0; ++ ++static struct semaphore *sem_nat_tbl_access; ++static int proc_read_in_progress = 0; ++ ++static int nDeviceOpen = 0; ++ ++/* saves the NAT table index between subsequent invocation */ ++static int nProcReadIdx = 0; ++ ++static long SVIP_NAT_device_ioctl(struct file *,unsigned int ,unsigned long); ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) ++static int SVIP_NAT_device_release (struct inode *,struct file *); ++#else ++static void SVIP_NAT_device_release (struct inode *,struct file *); ++#endif ++static int SVIP_NAT_device_open (struct inode *,struct file *); ++ ++/* This structure holds the interface functions supported by ++ the SVIP NAT configuration device. */ ++struct file_operations SVIP_NAT_Fops = { ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) ++owner: THIS_MODULE, ++#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,0) */ ++ llseek: NULL, /* seek */ ++ read: NULL, ++ write: NULL, ++ readdir: NULL, /* readdir */ ++ poll: NULL, /* select */ ++ unlocked_ioctl: SVIP_NAT_device_ioctl, /* ioctl */ ++ mmap: NULL, /* mmap */ ++ open: SVIP_NAT_device_open, /* open, */ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) ++ flush: NULL, /* flush */ ++#endif ++ release: SVIP_NAT_device_release /* close */ ++}; ++ ++/** Structure holding MISC module operations */ ++static struct miscdevice SVIP_NAT_miscdev = ++{ ++minor: MINOR_NUM_SVIP_NAT, ++ name: SVIP_NAT_DEVICE_NAME, ++ fops: &SVIP_NAT_Fops ++}; ++ ++#ifdef CONFIG_SVIP_FW_PKT_SNIFFER ++int nSVIP_NAT_Sniffer; ++unsigned char pSVIP_NAT_SnifferMAC[ETH_ALEN]; ++int nSVIP_NAT_SnifferMacSet; ++#endif ++ ++/******************************************************************************/ ++/** ++ Function to read /proc/net/svip_nat/nat proc entry ++ ++ \arguments ++ page - pointer to page buffer ++ start - pointer to start address pointer ++ off - offset ++ count - maximum data length to read ++ eof - end of file flag ++ data - proc read data (provided by the function ++ pointed to by data) ++ ++ \return ++ length of read data ++ ++ \remarks: ++ Each call of this routine forces a copy_to_user of the data returned by ++ 'fn'. This routine will be called by the user until 'len = 0'. ++ ****************************************************************************/ ++static int SVIP_NAT_ProcRead (char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ unsigned long flags; ++ int (*fn)(char *buf, int size); ++ int len; ++ ++ /* If the NAT table index is negative, the reading has completed */ ++ if (nProcReadIdx < 0) ++ { ++ nProcReadIdx = 0; ++ *eof = 1; ++ proc_read_in_progress = 0; ++ up(sem_nat_tbl_access); ++ return 0; ++ } ++ ++ local_irq_save(flags); ++ if (!proc_read_in_progress) ++ { ++ proc_read_in_progress = 1; ++ local_irq_restore(flags); ++ /* we use this semaphore in order to ensure no other party(could be ioctl ++ FIO_SVIP_NAT_RULE_LIST), uses function SVIP_NAT_ProcReadNAT(), during ++ the time read of the proc file takes place */ ++ down(sem_nat_tbl_access); ++ } ++ else ++ { ++ local_irq_restore(flags); ++ } ++ ++ if (data != NULL) ++ { ++ fn = data; ++ len = fn (page, count); ++ /* In this setup each read of the proc entries returns the read data by ++ 'fn' to the user. The user keeps issuing read requests as long as the ++ returned value of 'len' is greater than zero. */ ++ *eof = 1; ++ *start = page; ++ } ++ else ++ { ++ len = 0; ++ } ++ ++ return len; ++} ++ ++#ifdef CONFIG_SVIP_FW_PKT_SNIFFER ++/** ++ Function to read remaining proc entries ++ */ ++static int SVIP_NAT_ProcReadGen (char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int (*fn)(char *buf, int size); ++ int len = 0; ++ ++ MOD_INC_USE_COUNT; ++ ++ if (data == NULL) ++ { ++ MOD_DEC_USE_COUNT; ++ return 0; ++ } ++ ++ fn = data; ++ len = fn (page, count); ++ ++ if (len <= off + count) ++ { ++ *eof = 1; ++ } ++ *start = page + off; ++ len -= off; ++ if (len > count) ++ { ++ len = count; ++ } ++ if (len < 0) ++ { ++ len = 0; ++ } ++ ++ MOD_DEC_USE_COUNT; ++ ++ return len; ++} ++#endif ++ ++/******************************************************************************/ ++/** ++ Function for setting up /proc/net/svip_nat read data ++ ++ \arguments ++ buf - pointer to read buffer ++ count - size of read buffer ++ ++ \return ++ length of read data into buffer ++ ++ \remarks: ++ The global variable 'nProcReadIdx' is used to save the table index where ++ the reading of the NAT table stopped. Reading is stopped when the end of ++ the read buffer is approached. On the next itteration the reading continues ++ from the saved index. ++ *******************************************************************************/ ++static int SVIP_NAT_ProcReadNAT(char *buf, int count) ++{ ++ int i, j; ++ int len = 0; ++ SVIP_NAT_IO_Rule_t *pNatRule; ++ ++ if (nProcReadIdx == -1) ++ { ++ nProcReadIdx = 0; ++ return 0; ++ } ++ ++ if (nProcReadIdx == 0) ++ { ++ len = sprintf(buf+len, ++ "Remote host IP " /* 16 char */ ++ "Remote host MAC " /* 19 char */ ++ "Local host IP " /* 15 char */ ++ "Local host MAC " /* 19 char */ ++ "Local host UDP " /* 16 char */ ++ "Loc->Rem(in/out/err) " /* 22 char */ ++ "Rem->Loc(in/out/err)\n\r"); ++ } ++ ++ for (i = nProcReadIdx; i < SVIP_SYS_CODEC_NUM; i++) ++ { ++ int slen; ++ ++ pNatRule = &pNatTable[i].natRule; ++ ++ if (pNatRule->remIP != 0) ++ { ++ /* make sure not to overwrite the buffer */ ++ if (count < len+120) ++ break; ++ ++ /* remIP */ ++ slen = sprintf(buf+len, "%d.%d.%d.%d", ++ (int)((pNatRule->remIP >> 24) & 0xff), ++ (int)((pNatRule->remIP >> 16) & 0xff), ++ (int)((pNatRule->remIP >> 8) & 0xff), ++ (int)((pNatRule->remIP >> 0) & 0xff)); ++ len += slen; ++ for (j = 0; j < (16-slen); j++) ++ len += sprintf(buf+len, " "); ++ ++ /* remMAC */ ++ slen = 0; ++ for (j = 0; j < ETH_ALEN; j++) ++ { ++ slen += sprintf(buf+len+slen, "%02x%s", ++ pNatRule->remMAC[j], j < ETH_ALEN-1 ? ":" : " "); ++ } ++ len += slen; ++ for (j = 0; j < (19-slen); j++) ++ len += sprintf(buf+len, " "); ++ ++ /* locIP */ ++ slen = sprintf(buf+len, "%d.%d.%d.%d", ++ (int)((pNatRule->locIP >> 24) & 0xff), ++ (int)((pNatRule->locIP >> 16) & 0xff), ++ (int)((pNatRule->locIP >> 8) & 0xff), ++ (int)((pNatRule->locIP >> 0) & 0xff)); ++ len += slen; ++ for (j = 0; j < (15-slen); j++) ++ len += sprintf(buf+len, " "); ++ ++ /* locMAC */ ++ slen = 0; ++ for (j = 0; j < ETH_ALEN; j++) ++ { ++ slen += sprintf(buf+len+slen, "%02x%s", ++ pNatRule->locMAC[j], j < ETH_ALEN-1 ? ":" : " "); ++ } ++ len += slen; ++ for (j = 0; j < (19-slen); j++) ++ len += sprintf(buf+len, " "); ++ ++ /* locUDP */ ++ slen = sprintf(buf+len, "%d", pNatRule->locUDP); ++ len += slen; ++ for (j = 0; j < (16-slen); j++) ++ len += sprintf(buf+len, " "); ++ ++ /* NAT statistics, Local to Remote translation */ ++ slen = sprintf(buf+len, "(%ld/%ld/%ld)", ++ pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].inPackets, ++ pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].outPackets, ++ pNatTable[i].natStats[SVIP_NAT_STATS_LOC2REM].outErrors); ++ len += slen; ++ for (j = 0; j < (22-slen); j++) ++ len += sprintf(buf+len, " "); ++ ++ /* NAT statistics, Remote to Local translation */ ++ len += sprintf(buf+len, "(%ld/%ld/%ld)\n\r", ++ pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].inPackets, ++ pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].outPackets, ++ pNatTable[i].natStats[SVIP_NAT_STATS_REM2LOC].outErrors); ++ } ++ } ++ if (i == SVIP_SYS_CODEC_NUM) ++ nProcReadIdx = -1; /* reading completed */ ++ else ++ nProcReadIdx = i; /* reading still in process, buffer was full */ ++ ++ return len; ++} ++ ++#ifdef CONFIG_SVIP_FW_PKT_SNIFFER ++/** ++ Converts MAC address from ascii to hex respesentaion ++ */ ++static int SVIP_NAT_MacAsciiToHex(const char *pMacStr, unsigned char *pMacHex) ++{ ++ int i=0, c=0, b=0, n=0; ++ ++ memset(pMacHex, 0, ETH_ALEN); ++ while (pMacStr[i] != '\0') ++ { ++ if (n >= 0) ++ { ++ unsigned char nToHex = 0; ++ ++ /* check for hex digit */ ++ if (pMacStr[i] >= '0' && pMacStr[i] <= '9') ++ nToHex = 0x30; ++ else if (pMacStr[i] >= 'a' && pMacStr[i] <= 'f') ++ nToHex = 0x57; ++ else if (pMacStr[i] >= 'A' && pMacStr[i] <= 'F') ++ nToHex = 0x37; ++ else ++ { ++ if (n != 0) ++ { ++ printk(KERN_ERR "SVIP NAT: invalid MAC address format[%s]\n", pMacStr); ++ return -1; ++ } ++ i++; ++ continue; ++ } ++ n^=1; ++ pMacHex[b] |= ((pMacStr[i] - nToHex)&0xf) << (4*n); ++ if (n == 0) ++ { ++ /* advance to next byte, check if complete */ ++ if (++b >= ETH_ALEN) ++ return 0; ++ /* byte completed, next we expect a colon... */ ++ c = 1; ++ /* and, do not check for hex digit */ ++ n = -1; ++ } ++ i++; ++ continue; ++ } ++ if (c == 1) ++ { ++ if (pMacStr[i] == ':') ++ { ++ /* next we expect hex digit, again */ ++ n = 0; ++ } ++ else ++ { ++ printk(KERN_ERR "SVIP NAT: invalid MAC address format[%s]\n", pMacStr); ++ return -1; ++ } ++ } ++ i++; ++ } ++ return 0; ++} ++ ++/** ++ Used to set the destination MAC address of a host where incoming ++ SVIP VoFW packets are to be addressed. In case the address is set ++ to 00:00:00:00:00:00 (the default case), the packets will written ++ out to eth0 with its original MAC addess. ++ ++ \remark ++usage: 'echo "00:03:19:00:15:D1" > cat /proc/net/svip_nat/snifferMAC' ++*/ ++int SVIP_NAT_ProcWriteSnifferMAC (struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ /* at least strlen("xx:xx:xx:xx:xx:xx") characters, followed by '\0' */ ++ if (count >= 18) ++ { ++ int ret; ++ ++ ret = SVIP_NAT_MacAsciiToHex(buffer, pSVIP_NAT_SnifferMAC); ++ ++ if (ret != 0) ++ return 0; ++ ++ if (!(pSVIP_NAT_SnifferMAC[0]==0 && pSVIP_NAT_SnifferMAC[1]==0 && ++ pSVIP_NAT_SnifferMAC[2]==0 && pSVIP_NAT_SnifferMAC[3]==0 && ++ pSVIP_NAT_SnifferMAC[4]==0 && pSVIP_NAT_SnifferMAC[5]==0)) ++ { ++ nSVIP_NAT_SnifferMacSet = 1; ++ } ++ } ++ return count; ++} ++ ++/** ++ Used to read the destination MAC address of a sniffer host ++ */ ++int SVIP_NAT_ProcReadSnifferMAC (char *buf, int count) ++{ ++ int len = 0; ++ ++ len = snprintf(buf, count, "%02x:%02x:%02x:%02x:%02x:%02x\n", ++ pSVIP_NAT_SnifferMAC[0], pSVIP_NAT_SnifferMAC[1], ++ pSVIP_NAT_SnifferMAC[2], pSVIP_NAT_SnifferMAC[3], ++ pSVIP_NAT_SnifferMAC[4], pSVIP_NAT_SnifferMAC[5]); ++ ++ if (len > count) ++ { ++ printk(KERN_ERR "SVIP NAT: Only part of the text could be put into the buffer\n"); ++ return count; ++ } ++ ++ return len; ++} ++ ++/** ++ Used to switch VoFW message sniffer on/off ++ ++ \remark ++usage: 'echo "1" > cat /proc/net/svip_nat/snifferOnOff' ++*/ ++int SVIP_NAT_ProcWriteSnifferOnOff (struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ /* at least one digit expected, followed by '\0' */ ++ if (count >= 2) ++ { ++ int ret, nSnifferOnOff; ++ ++ ret = sscanf(buffer, "%d", &nSnifferOnOff); ++ ++ if (ret != 1) ++ return count; ++ ++ if (nSnifferOnOff > 0) ++ nSnifferOnOff = 1; ++ ++ nSVIP_NAT_Sniffer = nSnifferOnOff; ++ } ++ return count; ++} ++ ++/** ++ Used to read the VoFW message sniffer configuration (on/off) ++ */ ++int SVIP_NAT_ProcReadSnifferOnOff (char *buf, int count) ++{ ++ int len = 0; ++ ++ len = snprintf(buf, count, "%d\n", nSVIP_NAT_Sniffer); ++ ++ if (len > count) ++ { ++ printk(KERN_ERR "SVIP NAT: Only part of the text could be put into the buffer\n"); ++ return count; ++ } ++ ++ return len; ++} ++#endif ++ ++/******************************************************************************/ ++/** ++ Creates proc read/write entries ++ ++ \return ++ 0 on success, -1 on error ++ */ ++/******************************************************************************/ ++static int SVIP_NAT_ProcInstall(void) ++{ ++ struct proc_dir_entry *pProcParentDir, *pProcDir; ++ struct proc_dir_entry *pProcNode; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ pProcParentDir = proc_net; ++#else ++ pProcParentDir = init_net.proc_net; ++#endif ++ pProcDir = proc_mkdir(SVIP_NAT_DEVICE_NAME, pProcParentDir); ++ if (pProcDir == NULL) ++ { ++ printk(KERN_ERR "SVIP NAT: cannot create proc dir %s/%s\n\r", ++ pProcParentDir->name, SVIP_NAT_DEVICE_NAME); ++ return -1; ++ } ++ ++ pProcNode = create_proc_read_entry("nat", S_IFREG|S_IRUGO, pProcDir, ++ SVIP_NAT_ProcRead, (void *)SVIP_NAT_ProcReadNAT); ++ if (pProcNode == NULL) ++ { ++ printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s", ++ pProcDir->name, "nat"); ++ return -1; ++ } ++ ++#ifdef CONFIG_SVIP_FW_PKT_SNIFFER ++ nSVIP_NAT_Sniffer = 0; ++ /* creates proc entry for switching on/off sniffer to VoFW messages */ ++ pProcNode = create_proc_read_entry("snifferOnOff", S_IFREG|S_IRUGO|S_IWUGO, ++ pProcDir, SVIP_NAT_ProcReadGen, (void *)SVIP_NAT_ProcReadSnifferOnOff); ++ if (pProcNode == NULL) ++ { ++ printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s\n\r", ++ pProcDir->name, "snifferOnOff"); ++ return -1; ++ } ++ pProcNode->write_proc = SVIP_NAT_ProcWriteSnifferOnOff; ++ ++ memset (pSVIP_NAT_SnifferMAC, 0, ETH_ALEN); ++ nSVIP_NAT_SnifferMacSet = 0; ++ /* creates proc entry for setting MAC address of sniffer host to VoFW messages */ ++ pProcNode = create_proc_read_entry("snifferMAC", S_IFREG|S_IRUGO|S_IWUGO, ++ pProcDir, SVIP_NAT_ProcReadGen, (void *)SVIP_NAT_ProcReadSnifferMAC); ++ if (pProcNode == NULL) ++ { ++ printk(KERN_ERR "SVIP NAT: cannot create proc entry %s/%s\n\r", ++ pProcDir->name, "snifferMAC"); ++ return -1; ++ } ++ pProcNode->write_proc = SVIP_NAT_ProcWriteSnifferMAC; ++#endif ++ ++ return 0; ++} ++ ++/******************************************************************************/ ++/** ++ No actions done here, simply a check is performed if an open has already ++ been performed. Currently only a single open is allowed as it is a sufficient ++ to have hat a single process configuring the SVIP NAT at one time. ++ ++ \arguments ++ inode - pointer to disk file data ++ file - pointer to device file data ++ ++ \return ++ 0 on success, else -1 ++ */ ++/******************************************************************************/ ++static int SVIP_NAT_device_open(struct inode *inode, struct file *file) ++{ ++ unsigned long flags; ++ struct in_device *in_dev; ++ struct in_ifaddr *ifa; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ local_irq_save(flags); ++#else ++ local_save_flags(flags); ++#endif ++ ++ if (nDeviceOpen) ++ { ++ MOD_INC_USE_COUNT; ++ local_irq_restore(flags); ++ nDeviceOpen++; ++ return 0; ++ } ++ ++ /* find pointer to IP address of eth0 */ ++ if ((in_dev=in_dev_get(net_devs[SVIP_NET_DEV_ETH0_IDX])) != NULL) ++ { ++ for (ifa = in_dev->ifa_list; ifa != NULL; ifa = ifa->ifa_next) ++ { ++ if (!paddr_eth0 && ifa->ifa_address != 0) ++ { ++ paddr_eth0 = &ifa->ifa_address; ++ continue; ++ } ++ if (paddr_eth0 && ifa->ifa_address != 0) ++ { ++ paddr_eth0_0 = &ifa->ifa_address; ++ break; ++ } ++ } ++ in_dev_put(in_dev); ++ } ++ if (paddr_eth0 == NULL || paddr_eth0_0 == NULL) ++ { ++ local_irq_restore(flags); ++ return -ENODATA; ++ } ++ ++ /* find pointer to IP address of veth0 */ ++ if ((in_dev=in_dev_get(net_devs[SVIP_NET_DEV_VETH0_IDX])) != NULL) ++ { ++ for (ifa = in_dev->ifa_list; ifa != NULL; ifa = ifa->ifa_next) ++ { ++ if (ifa->ifa_address != 0) ++ { ++ paddr_veth0 = &ifa->ifa_address; ++ pmask_veth0 = &ifa->ifa_mask; ++ break; ++ } ++ } ++ in_dev_put(in_dev); ++ } ++ if (paddr_veth0 == NULL) ++ { ++ local_irq_restore(flags); ++ return -ENODATA; ++ } ++ ++ MOD_INC_USE_COUNT; ++ nDeviceOpen++; ++ local_irq_restore(flags); ++ ++ return 0; ++} ++ ++ ++/******************************************************************************/ ++/** ++ This function is called when a process closes the SVIP NAT device file ++ ++ \arguments ++ inode - pointer to disk file data ++ file - pointer to device file data ++ ++ \return ++ 0 on success, else -1 ++ ++*/ ++/******************************************************************************/ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) ++static int SVIP_NAT_device_release(struct inode *inode, ++ struct file *file) ++#else ++static void SVIP_NAT_device_release(struct inode *inode, ++ struct file *file) ++#endif ++{ ++ unsigned long flags; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ save_flags(flags); ++ cli(); ++#else ++ local_save_flags(flags); ++#endif ++ ++ /* The device can now be openned by the next caller */ ++ nDeviceOpen--; ++ ++ MOD_DEC_USE_COUNT; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ restore_flags(flags); ++#else ++ local_irq_restore(flags); ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,2,0) ++ return 0; ++#endif ++} ++ ++ ++/******************************************************************************/ ++/** ++ This function is called when a process closes the SVIP NAT device file ++ ++ \arguments ++ inode - pointer to disk file data ++ file - pointer to device file data ++ ioctl_num - ioctl number requested ++ ioctl_param - pointer to data related to the ioctl number ++ ++ \return ++ 0 on success, else -1 ++ ++*/ ++/******************************************************************************/ ++long SVIP_NAT_device_ioctl (struct file *file, ++ unsigned int ioctl_num, unsigned long ioctl_param) ++{ ++ int ret = 0; ++ SVIP_NAT_IO_Rule_t *pNatRule, *pNatRuleIn; ++ SVIP_UDP_PORT_t nPort; ++ int nNatIdx; ++ int bWrite = 0; ++ int bRead = 0; ++ unsigned char *pData = 0; ++ int nSize; ++ ++ if (_IOC_DIR(ioctl_num) & _IOC_WRITE) ++ bWrite = 1; ++ if (_IOC_DIR(ioctl_num) & _IOC_READ) ++ bRead = 1; ++ nSize = _IOC_SIZE(ioctl_num); ++ ++ if (nSize > sizeof(int)) ++ { ++ if (bRead || bWrite) ++ { ++ pData = kmalloc (nSize, GFP_KERNEL); ++ if (bWrite) ++ { ++ if (copy_from_user ((void *)pData, (void *)ioctl_param, nSize) != 0) ++ { ++ printk(KERN_ERR "SVIP NAT: ioctl %x: copy_from_user() failed!\n", ioctl_num); ++ ret = -1; ++ goto error; ++ } ++ } ++ } ++ } ++ ++ switch (ioctl_num) ++ { ++ case FIO_SVIP_NAT_RULE_ADD: ++ ++ pNatRuleIn = (SVIP_NAT_IO_Rule_t *)pData; ++ ++ /* check if destination UDP port is within range */ ++ nPort = ntohs(pNatRuleIn->locUDP); ++ ++ if (!SVIP_PORT_INRANGE(nPort)) ++ { ++ printk(KERN_ERR "SVIP NAT: Error, UDP port(%d) is out of range(%d..%d)\n", ++ nPort, SVIP_UDP_FROM, SVIP_UDP_TO); ++ ret = -1; ++ goto error; ++ } ++ nNatIdx = SVIP_PORT_INDEX(nPort); ++ ++ down(sem_nat_tbl_access); ++ pNatRule = &pNatTable[nNatIdx].natRule; ++ ++ /* add rule to the NAT table */ ++ pNatRule->remIP = pNatRuleIn->remIP; ++ memcpy((char *)pNatRule->remMAC, (char *)pNatRuleIn->remMAC, ETH_ALEN); ++ pNatRule->locIP = pNatRuleIn->locIP; ++ memcpy((char *)pNatRule->locMAC, (char *)pNatRuleIn->locMAC, ETH_ALEN); ++ pNatRule->locUDP = pNatRuleIn->locUDP; ++ ++ memset(pNatTable[nNatIdx].natStats, 0, ++ sizeof(SVIP_NAT_stats_t)*SVIP_NAT_STATS_TYPES); ++ up(sem_nat_tbl_access); ++ break; ++ ++ case FIO_SVIP_NAT_RULE_REMOVE: ++ ++ pNatRuleIn = (SVIP_NAT_IO_Rule_t *)pData; ++ ++ /* check if destination UDP port is within range */ ++ nPort = ntohs(pNatRuleIn->locUDP); ++ if (!SVIP_PORT_INRANGE(nPort)) ++ { ++ printk(KERN_ERR "SVIP NAT: Error, UDP port(%d) is out of range(%d..%d)\n", ++ nPort, SVIP_UDP_FROM, SVIP_UDP_TO); ++ ret = -1; ++ goto error; ++ } ++ nNatIdx = SVIP_PORT_INDEX(nPort); ++ down(sem_nat_tbl_access); ++ /* remove rule from the NAT table */ ++ memset(&pNatTable[nNatIdx], 0, sizeof(SVIP_NAT_table_entry_t)); ++ up(sem_nat_tbl_access); ++ break; ++ ++ case FIO_SVIP_NAT_RULE_LIST: ++ { ++ int len; ++ char buf[256]; ++ ++ down(sem_nat_tbl_access); ++ while (nProcReadIdx != -1) ++ { ++ len = SVIP_NAT_ProcReadNAT(buf, 256); ++ if (len > 0) ++ printk("%s", buf); ++ } ++ nProcReadIdx = 0; ++ up(sem_nat_tbl_access); ++ break; ++ } ++ ++ default: ++ printk(KERN_ERR "SVIP NAT: unsupported ioctl (%x) command for device %s\n", ++ ioctl_num, PATH_SVIP_NAT_DEVICE_NAME); ++ ret = -1; ++ goto error; ++ } ++ ++ if (nSize > sizeof(int)) ++ { ++ if (bRead) ++ { ++ if (copy_to_user ((void *)ioctl_param, (void *)pData, nSize) != 0) ++ { ++ printk(KERN_ERR "SVIP NAT: ioctl %x: copy_to_user() failed!\n", ioctl_num); ++ ret = -1; ++ goto error; ++ } ++ } ++ } ++ ++error: ++ if (pData) ++ kfree(pData); ++ ++ return ret; ++} ++ ++#if 0 ++void dump_msg(unsigned char *pData, unsigned int nLen) ++{ ++ int i; ++ ++ for (i=0; i<nLen; i++) ++ { ++ if (!i || !(i%16)) ++ printk("\n "); ++ else if (i && !(i%4)) ++ printk(" "); ++ printk("%02x", pData[i]); ++ } ++ if (--i%16) ++ printk("\n"); ++} ++#endif ++ ++/******************************************************************************/ ++/** ++ Used to recalculate IP/UDP checksum using the original IP/UDP checksum ++ coming with the packet. The original source and destination IP addresses ++ are accounted for, and, the checksum is updated using the new source and ++ destination IP addresses. ++ ++ \arguments ++ skb - pointer to the receiving socket buffer ++ csum_old - original checksum ++ saddr_old - pointer to original source IP address ++ saddr_new - pointer to new source IP address ++ daddr_old - pointer to original destination IP address ++ daddr_new - pointer to new destination IP address ++ ++ \return ++ recalculated IP/UDP checksum ++ */ ++/******************************************************************************/ ++static inline u16 ip_udp_quick_csum(u16 csum_old, u16 *saddr_old, u16 *saddr_new, ++ u16 *daddr_old, u16 *daddr_new) ++{ ++ u32 sum; ++ ++ sum = csum_old; ++ ++ /* convert back from one's complement */ ++ sum = ~sum & 0xffff; ++ ++ if (sum < saddr_old[0]) sum += 0xffff; ++ sum -= saddr_old[0]; ++ if (sum < saddr_old[1]) sum += 0xffff; ++ sum -= saddr_old[1]; ++ if (sum < daddr_old[0]) sum += 0xffff; ++ sum -= daddr_old[0]; ++ if (sum < daddr_old[1]) sum += 0xffff; ++ sum -= daddr_old[1]; ++ ++ sum += saddr_new[0]; ++ sum += saddr_new[1]; ++ sum += daddr_new[0]; ++ sum += daddr_new[1]; ++ ++ /* take only 16 bits out of the 32 bit sum and add up the carries */ ++ while (sum >> 16) ++ sum = (sum & 0xffff)+((sum >> 16) & 0xffff); ++ ++ /* one's complement the result */ ++ sum = ~sum; ++ ++ return (u16)(sum & 0xffff); ++} ++ ++ ++/******************************************************************************/ ++/** ++ Returns a pointer to an ipv4 address assigned to device dev. The ipv4 ++ instance checked is pointed to by ifa_start. The function is suited for ++ itterative calls. ++ ++ \arguments ++ dev - pointer to network interface ++ ifa_start - pointer to ipv4 instance to return ipv4 address assigned ++ to, NULL for the first one ++ ppifa_addr - output parameter ++ ++ \return ++ pointer to the next ipv4 instance, which can be null if ifa_start was ++ the last instance present ++ */ ++/******************************************************************************/ ++static struct in_ifaddr *get_ifaddr(struct net_device *dev, ++ struct in_ifaddr *ifa_start, unsigned int **ppifa_addr) ++{ ++ struct in_device *in_dev; ++ struct in_ifaddr *ifa = NULL; ++ ++ if ((in_dev=in_dev_get(dev)) != NULL) ++ { ++ if (ifa_start == NULL) ++ ifa = in_dev->ifa_list; ++ else ++ ifa = ifa_start; ++ if (ifa) ++ { ++ *ppifa_addr = &ifa->ifa_address; ++ ifa = ifa->ifa_next; ++ } ++ in_dev_put(in_dev); ++ return ifa; ++ } ++ *ppifa_addr = NULL; ++ return NULL; ++} ++ ++/******************************************************************************/ ++/** ++ This function performs IP NAT for received packets satisfying the ++ following requirements: ++ ++ - packet is destined to local IP host ++ - transport protocol type is UDP ++ - destination UDP port is within range ++ ++ \arguments ++ skb - pointer to the receiving socket buffer ++ ++ \return ++ returns 1 on performed SVIP NAT, else returns 0 ++ ++ \remarks ++ When function returns 0, it indicates the caller to pass the ++ packet up the IP stack to make further decision about it ++ */ ++/******************************************************************************/ ++int do_SVIP_NAT (struct sk_buff *skb) ++{ ++ struct net_device *real_dev; ++ struct iphdr *iph; ++ struct udphdr *udph; ++ SVIP_NAT_IO_Rule_t *pNatRule; ++ int nNatIdx, in_eth0, nDir; ++#ifndef VLAN_8021Q_UNUSED ++ int vlan; ++ unsigned short vid; ++#endif /* ! VLAN_8021Q_UNUSED */ ++ SVIP_UDP_PORT_t nPort; ++ u32 orgSrcIp, orgDstIp, *pSrcIp, *pDstIp; ++ struct ethhdr *ethh; ++ ++ /* do not consider if SVIP NAT device not open. */ ++ if (!nDeviceOpen) ++ { ++ return 0; ++ } ++ ++ /* consider only UDP packets. */ ++ iph = SVIP_NAT_IP_HDR(skb); ++ if (iph->protocol != IPPROTO_UDP) ++ { ++ return 0; ++ } ++ ++ udph = (struct udphdr *)((u_int32_t *)iph + iph->ihl); ++ /* consider only packets which UDP port numbers reside within ++ the predefined SVIP NAT UDP port range. */ ++ if ((!SVIP_PORT_INRANGE(ntohs(udph->dest))) && ++ (!SVIP_PORT_INRANGE(ntohs(udph->source)))) ++ { ++ return 0; ++ } ++ ++#ifndef VLAN_8021Q_UNUSED ++ /* check if packet delivered over VLAN. VLAN packets will be routed over ++ the VLAN interfaces of the respective real Ethernet interface, if one ++ exists(VIDs must match). Else, the packet will be send out as IEEE 802.3 ++ Ethernet frame */ ++ if (skb->dev->priv_flags & IFF_802_1Q_VLAN) ++ { ++ vlan = 1; ++ vid = VLAN_DEV_VLAN_ID(skb->dev); ++ real_dev = VLAN_DEV_REAL_DEV(skb->dev); ++ } ++ else ++ { ++ vlan = 0; ++ vid = 0; ++ real_dev = skb->dev; ++ } ++#endif /* ! VLAN_8021Q_UNUSED */ ++ ++#ifdef CONFIG_SVIP_FW_PKT_SNIFFER ++ /** Debugging feature which can be enabled by writing, ++ 'echo 1 > /proc/net/svip_nat/snifferOnOff'. ++ It copies all packets received on veth0 and, sends them out over eth0. ++ When a destination MAC address is specified through ++ /proc/net/svip_nat/snifferMAC, this MAC addess will substitute the ++ original MAC address of the packet. ++ It is recommended to specify a MAC address of some host where Wireshark ++ runs and sniffs for this traffic, else you may flood your LAN with ++ undeliverable traffic. ++ ++NOTE: In case of VLAN traffic the VLAN header information is lost. */ ++ if (nSVIP_NAT_Sniffer) ++ { ++ if (real_dev == net_devs[SVIP_NET_DEV_VETH0_IDX]) ++ { ++ struct sk_buff *copied_skb; ++ ++ /* gain the Ethernet header from the skb */ ++ skb_push(skb, ETH_HLEN); ++ ++ copied_skb = skb_copy (skb, GFP_ATOMIC); ++ ++ if (nSVIP_NAT_SnifferMacSet == 1) ++ { ++ ethh = (struct ethhdr *)SVIP_NAT_SKB_MAC_HEADER(copied_skb); ++ memcpy((char *)ethh->h_dest, (char *)pSVIP_NAT_SnifferMAC, ETH_ALEN); ++ } ++ copied_skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; ++ dev_queue_xmit(copied_skb); ++ ++ /* skip the ETH header again */ ++ skb_pull(skb, ETH_HLEN); ++ } ++ } ++#endif ++ ++ ++ /* check if packet arrived on eth0 */ ++ if (real_dev == net_devs[SVIP_NET_DEV_ETH0_IDX]) ++ { ++ /* check if destination IP address equals the primary assigned IP address ++ of interface eth0. This is the case of packets originating from a ++ remote peer that are to be delivered to a channel residing on THIS ++ voice linecard system. This is typical SVIP NAT case, therefore this ++ rule is placed on top. */ ++ if (iph->daddr == *paddr_eth0) ++ { ++ nPort = ntohs(udph->dest); ++ nDir = SVIP_NAT_STATS_REM2LOC; ++ } ++ /* check if destination IP address equals the secondary assigned IP address ++ of interface eth0. This is not a typical SVIP NAT case. It is basically ++ there, as someone might like for debugging purpose to use the LCC to route ++ Slave SVIP packets which are part of voice/fax streaming. */ ++ else if (iph->daddr == *paddr_eth0_0) ++ { ++ nPort = ntohs(udph->source); ++ nDir = SVIP_NAT_STATS_LOC2REM; ++ } ++#ifndef VLAN_8021Q_UNUSED ++ /* when the packet did not hit the top two rules, here we check if the packet ++ has addressed any of the IP addresses assigned to the VLAN interface attached ++ to eth0. This is not recommended approach because of the CPU cost incurred. */ ++ else if (vlan) ++ { ++ unsigned int *pifa_addr; ++ struct in_ifaddr *ifa_start = NULL; ++ int i = 0; ++ ++ do ++ { ++ ifa_start = get_ifaddr(skb->dev, ifa_start, &pifa_addr); ++ if (!pifa_addr) ++ { ++ /* VLAN packet received on vlan interface attached to eth0, ++ however no IP address assigned to the interface. ++ The packet is ignored. */ ++ return 0; ++ } ++ if (iph->daddr == *pifa_addr) ++ { ++ /* packet destined to... */ ++ break; ++ } ++ if (!ifa_start) ++ { ++ return 0; ++ } ++ i++; ++ } while (ifa_start); ++ if (!i) ++ { ++ /* ...primary assigned IP address to the VLAN interface. */ ++ nPort = ntohs(udph->dest); ++ nDir = SVIP_NAT_STATS_REM2LOC; ++ } ++ else ++ { ++ /* ...secondary assigned IP address to the VLAN interface. */ ++ nPort = ntohs(udph->source); ++ nDir = SVIP_NAT_STATS_LOC2REM; ++ } ++ } ++#endif /* ! VLAN_8021Q_UNUSED */ ++ else ++ { ++ return 0; ++ } ++ in_eth0 = 1; ++ } ++ /* check if packet arrived on veth0 */ ++ else if (real_dev == net_devs[SVIP_NET_DEV_VETH0_IDX]) ++ { ++ nPort = ntohs(udph->source); ++ nDir = SVIP_NAT_STATS_LOC2REM; ++ in_eth0 = 0; ++ } ++ else ++ { ++ /* packet arrived neither on eth0, nor veth0 */ ++ return 0; ++ } ++ ++ /* calculate the respective index of the NAT table */ ++ nNatIdx = SVIP_PORT_INDEX(nPort); ++ /* process the packet if a respective NAT rule exists */ ++ pNatRule = &pNatTable[nNatIdx].natRule; ++ ++ ethh = (struct ethhdr *)SVIP_NAT_SKB_MAC_HEADER(skb); ++ ++ /* copy packet's original source and destination IP addresses to use ++ later on to perform efficient checksum recalculation */ ++ orgSrcIp = iph->saddr; ++ orgDstIp = iph->daddr; ++ ++ if (in_eth0) ++ { ++ u8 *pDstMac; ++ ++ /* Process packet arrived on eth0 */ ++ ++ if (nDir == SVIP_NAT_STATS_REM2LOC && iph->saddr == pNatRule->remIP) ++ { ++ pDstIp = &pNatRule->locIP; ++ pDstMac = pNatRule->locMAC; ++ } ++ else if (nDir == SVIP_NAT_STATS_LOC2REM && iph->saddr == pNatRule->locIP) ++ { ++ pDstIp = &pNatRule->remIP; ++ pDstMac = pNatRule->remMAC; ++ } ++ else ++ { ++ /* Rule check failed. The packet is passed up the layers, ++ it will be dropped by UDP */ ++ return 0; ++ } ++ ++ if ((*pDstIp & *pmask_veth0) == (*paddr_veth0 & *pmask_veth0)) ++ { ++#ifndef VLAN_8021Q_UNUSED ++ if (vlan) ++ { ++ struct net_device *vlan_dev; ++ ++ spin_lock_bh(&vlan_group_lock); ++ vlan_dev = __vlan_find_dev_deep(net_devs[SVIP_NET_DEV_VETH0_IDX], vid); ++ spin_unlock_bh(&vlan_group_lock); ++ if (vlan_dev) ++ { ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ struct vlan_ethhdr *vethh; ++ ++ skb_push(skb, VLAN_ETH_HLEN); ++ /* reconstruct the VLAN header. ++NOTE: priority information is lost */ ++ vethh = (struct vlan_ethhdr *)skb->data; ++ vethh->h_vlan_proto = htons(ETH_P_8021Q); ++ vethh->h_vlan_TCI = htons(vid); ++ vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); ++ ethh = (struct ethhdr *)vethh; ++#else ++ skb_push(skb, ETH_HLEN); ++#endif ++ skb->dev = vlan_dev; ++ } ++ else ++ { ++ skb->dev = net_devs[SVIP_NET_DEV_VETH0_IDX]; ++ skb_push(skb, ETH_HLEN); ++ } ++ } ++ else ++#endif /* ! VLAN_8021Q_UNUSED */ ++ { ++ skb->dev = net_devs[SVIP_NET_DEV_VETH0_IDX]; ++ skb_push(skb, ETH_HLEN); ++ } ++ pSrcIp = paddr_veth0; ++ } ++ else ++ { ++#ifndef VLAN_8021Q_UNUSED ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ if (vlan) ++ { ++ struct vlan_ethhdr *vethh; ++ ++ /* reconstruct the VLAN header. ++NOTE: priority information is lost */ ++ skb_push(skb, VLAN_ETH_HLEN); ++ vethh = (struct vlan_ethhdr *)skb->data; ++ vethh->h_vlan_proto = htons(ETH_P_8021Q); ++ vethh->h_vlan_TCI = htons(vid); ++ vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); ++ ethh = (struct ethhdr *)vethh; ++ } ++ else ++#endif ++#endif /* ! VLAN_8021Q_UNUSED */ ++ { ++ skb_push(skb, ETH_HLEN); ++ } ++ /* source IP address equals the destination IP address ++ of the incoming packet */ ++ pSrcIp = &iph->daddr; ++ } ++ iph->saddr = *pSrcIp; ++ memcpy((char *)ethh->h_source, (char *)skb->dev->dev_addr, ETH_ALEN); ++ iph->daddr = *pDstIp; ++ memcpy((char *)ethh->h_dest, (char *)pDstMac, ETH_ALEN); ++ } ++ else ++ { ++ /* Process packet arrived on veth0 */ ++ ++ if (iph->saddr != pNatRule->locIP) ++ { ++ /* Rule check failed. The packet is passed up the layers, ++ it will be dropped by UDP */ ++ return 0; ++ } ++ ++ if (!((pNatRule->remIP & *pmask_veth0) == (*paddr_veth0 & *pmask_veth0))) ++ { ++#ifndef VLAN_8021Q_UNUSED ++ if (vlan) ++ { ++ struct net_device *vlan_dev; ++ ++ spin_lock_bh(&vlan_group_lock); ++ vlan_dev = __vlan_find_dev_deep(net_devs[SVIP_NET_DEV_ETH0_IDX], vid); ++ spin_unlock_bh(&vlan_group_lock); ++ if (vlan_dev) ++ { ++ unsigned int *pifa_addr; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ struct vlan_ethhdr *vethh; ++ ++ skb_push(skb, VLAN_ETH_HLEN); ++ /* construct the VLAN header, note priority information is lost */ ++ vethh = (struct vlan_ethhdr *)skb->data; ++ vethh->h_vlan_proto = htons(ETH_P_8021Q); ++ vethh->h_vlan_TCI = htons(vid); ++ vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); ++ ethh = (struct ethhdr *)vethh; ++#else ++ skb_push(skb, ETH_HLEN); ++#endif ++ skb->dev = vlan_dev; ++ ++ get_ifaddr(skb->dev, NULL, &pifa_addr); ++ if (pifa_addr) ++ { ++ pSrcIp = pifa_addr; ++ } ++ else ++ { ++ pSrcIp = paddr_eth0; ++ } ++ } ++ else ++ { ++ skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; ++ pSrcIp = paddr_eth0; ++ skb_push(skb, ETH_HLEN); ++ } ++ } ++ else ++#endif /* ! VLAN_8021Q_UNUSED */ ++ { ++ skb->dev = net_devs[SVIP_NET_DEV_ETH0_IDX]; ++ pSrcIp = paddr_eth0; ++ skb_push(skb, ETH_HLEN); ++ } ++ } ++ else ++ { ++ pSrcIp = paddr_veth0; ++#ifndef VLAN_8021Q_UNUSED ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ++ if (vlan) ++ { ++ struct vlan_ethhdr *vethh; ++ ++ skb_push(skb, VLAN_ETH_HLEN); ++ /* reconstruct the VLAN header. ++NOTE: priority information is lost. */ ++ vethh = (struct vlan_ethhdr *)skb->data; ++ vethh->h_vlan_proto = htons(ETH_P_8021Q); ++ vethh->h_vlan_TCI = htons(vid); ++ vethh->h_vlan_encapsulated_proto = htons(ETH_P_IP); ++ ethh = (struct ethhdr *)vethh; ++ } ++ else ++#endif ++#endif /* ! VLAN_8021Q_UNUSED */ ++ { ++ skb_push(skb, ETH_HLEN); ++ } ++ } ++ iph->saddr = *pSrcIp; ++ memcpy((char *)ethh->h_source, (char *)skb->dev->dev_addr, ETH_ALEN); ++ iph->daddr = pNatRule->remIP; ++ memcpy((char *)ethh->h_dest, (char *)pNatRule->remMAC, ETH_ALEN); ++ } ++ pNatTable[nNatIdx].natStats[nDir].inPackets++; ++ ++ iph->check = ip_udp_quick_csum(iph->check, (u16 *)&orgSrcIp, (u16 *)&iph->saddr, ++ (u16 *)&orgDstIp, (u16 *)&iph->daddr); ++ if (udph->check != 0) ++ { ++ udph->check = ip_udp_quick_csum(udph->check, (u16 *)&orgSrcIp, (u16 *)&iph->saddr, ++ (u16 *)&orgDstIp, (u16 *)&iph->daddr); ++ } ++ ++ /* write the packet out, directly to the network device */ ++ if (dev_queue_xmit(skb) < 0) ++ pNatTable[nNatIdx].natStats[nDir].outErrors++; ++ else ++ pNatTable[nNatIdx].natStats[nDir].outPackets++; ++ ++ return 1; ++} ++ ++/******************************************************************************/ ++/** ++ Function executed upon unloading of the SVIP NAT module. It unregisters the ++ SVIP NAT configuration device and frees the memory used for the NAT table. ++ ++ \remarks: ++ Currently the SVIP NAT module is statically linked into the Linux kernel ++ therefore this routine cannot be executed. ++ *******************************************************************************/ ++static int __init init(void) ++{ ++ int ret = 0; ++ struct net_device *dev; ++ ++ if (misc_register(&SVIP_NAT_miscdev) != 0) ++ { ++ printk(KERN_ERR "%s: cannot register SVIP NAT device node.\n", ++ SVIP_NAT_miscdev.name); ++ return -EIO; ++ } ++ ++ /* allocation of memory for NAT table */ ++ pNatTable = (SVIP_NAT_table_entry_t *)kmalloc( ++ sizeof(SVIP_NAT_table_entry_t) * SVIP_SYS_CODEC_NUM, GFP_ATOMIC); ++ if (pNatTable == NULL) ++ { ++ printk (KERN_ERR "SVIP NAT: Error(%d), allocating memory for NAT table\n", ret); ++ return -1; ++ } ++ ++ /* clear the NAT table */ ++ memset((void *)pNatTable, 0, sizeof(SVIP_NAT_table_entry_t) * SVIP_SYS_CODEC_NUM); ++ ++ if ((sem_nat_tbl_access = kmalloc(sizeof(struct semaphore), GFP_KERNEL))) ++ { ++ sema_init(sem_nat_tbl_access, 1); ++ } ++ ++ SVIP_NAT_ProcInstall(); ++ ++ /* find pointers to 'struct net_device' of eth0 and veth0, respectevely */ ++ read_lock(&dev_base_lock); ++ SVIP_NAT_FOR_EACH_NETDEV(dev) ++ { ++ if (!strcmp(dev->name, SVIP_NET_DEV_ETH0_NAME)) ++ { ++ net_devs[SVIP_NET_DEV_ETH0_IDX] = dev; ++ } ++ if (!strcmp(dev->name, SVIP_NET_DEV_VETH1_NAME)) ++ { ++ net_devs[SVIP_NET_DEV_VETH0_IDX] = dev; ++ } ++ else if (!strcmp(dev->name, SVIP_NET_DEV_ETH1_NAME)) ++ { ++ net_devs[SVIP_NET_DEV_VETH0_IDX] = dev; ++ } ++ } ++ read_unlock(&dev_base_lock); ++ ++ if (net_devs[SVIP_NET_DEV_ETH0_IDX] == NULL || ++ net_devs[SVIP_NET_DEV_VETH0_IDX] == NULL) ++ { ++ printk (KERN_ERR "SVIP NAT: Error, unable to locate eth0 and veth0 interfaces\n"); ++ return -1; ++ } ++ ++ printk ("%s, (c) 2009, Lantiq Deutschland GmbH\n", &SVIP_NAT_INFO_STR[4]); ++ ++ return ret; ++} ++ ++/******************************************************************************/ ++/** ++ Function executed upon unloading of the SVIP NAT module. It unregisters the ++ SVIP NAT configuration device and frees the memory used for the NAT table. ++ ++ \remarks: ++ Currently the SVIP NAT module is statically linked into the Linux kernel ++ therefore this routine cannot be executed. ++ *******************************************************************************/ ++static void __exit fini(void) ++{ ++ MOD_DEC_USE_COUNT; ++ ++ /* unregister SVIP NAT configuration device */ ++ misc_deregister(&SVIP_NAT_miscdev); ++ ++ /* release memory of SVIP NAT table */ ++ if (pNatTable != NULL) ++ { ++ kfree (pNatTable); ++ } ++} ++ ++module_init(init); ++module_exit(fini); +Index: linux-3.3.8/drivers/spi/Kconfig +=================================================================== +--- linux-3.3.8.orig/drivers/spi/Kconfig 2012-07-31 19:51:33.077105873 +0200 ++++ linux-3.3.8/drivers/spi/Kconfig 2012-07-31 19:51:34.153105919 +0200 +@@ -366,6 +366,11 @@ + This driver also supports the ML7213/ML7223/ML7831, a companion chip + for the Atom E6xx series and compatible with the Intel EG20T PCH. + ++config SPI_SVIP ++ tristate "SVIP SPI controller" ++ depends on SOC_SVIP ++ default y ++ + config SPI_TXX9 + tristate "Toshiba TXx9 SPI controller" + depends on GENERIC_GPIO && CPU_TX49XX +Index: linux-3.3.8/drivers/spi/Makefile +=================================================================== +--- linux-3.3.8.orig/drivers/spi/Makefile 2012-07-31 19:51:33.077105873 +0200 ++++ linux-3.3.8/drivers/spi/Makefile 2012-07-31 19:51:34.153105919 +0200 +@@ -61,4 +61,5 @@ + obj-$(CONFIG_SPI_TXX9) += spi-txx9.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o + obj-$(CONFIG_SPI_XWAY) += spi-xway.o ++obj-$(CONFIG_SPI_SVIP) += spi_svip.o + +Index: linux-3.3.8/net/ipv4/Kconfig +=================================================================== +--- linux-3.3.8.orig/net/ipv4/Kconfig 2012-06-01 09:16:13.000000000 +0200 ++++ linux-3.3.8/net/ipv4/Kconfig 2012-07-31 19:51:34.153105919 +0200 +@@ -630,3 +630,10 @@ + on the Internet. + + If unsure, say N. ++ ++config SVIP_NAT ++ bool "Include SVIP NAT" ++ depends on SOC_SVIP ++ default y ++ ---help--- ++ Include the SVIP NAT. +Index: linux-3.3.8/net/ipv4/Makefile +=================================================================== +--- linux-3.3.8.orig/net/ipv4/Makefile 2012-07-31 19:51:33.401105887 +0200 ++++ linux-3.3.8/net/ipv4/Makefile 2012-07-31 19:51:34.153105919 +0200 +@@ -56,3 +56,4 @@ + + obj-$(CONFIG_XFRM) += xfrm4_policy.o xfrm4_state.o xfrm4_input.o \ + xfrm4_output.o ++obj-$(CONFIG_SVIP_NAT) += svip_nat.o +Index: linux-3.3.8/arch/mips/lantiq/svip/switchip_setup.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.3.8/arch/mips/lantiq/svip/switchip_setup.c 2012-07-31 19:51:34.153105919 +0200 +@@ -0,0 +1,666 @@ ++/****************************************************************************** ++ Copyright (c) 2007, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++ ****************************************************************************** ++ Module : switchip_setup.c ++ Date : 2007-11-09 ++ Description : Basic setup of embedded ethernet switch "SwitchIP" ++ Remarks: andreas.schmidt@infineon.com ++ ++ *****************************************************************************/ ++ ++/* TODO: get rid of #ifdef CONFIG_LANTIQ_MACH_EASY336 */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/version.h> ++#include <linux/init.h> ++#include <linux/delay.h> ++#include <linux/workqueue.h> ++#include <linux/time.h> ++ ++#include <base_reg.h> ++#include <es_reg.h> ++#include <sys1_reg.h> ++#include <dma_reg.h> ++#include <lantiq_soc.h> ++ ++static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE; ++static struct svip_reg_es *const es = (struct svip_reg_es *)LTQ_ES_BASE; ++ ++/* PHY Organizationally Unique Identifier (OUI) */ ++#define PHY_OUI_PMC 0x00E004 ++#define PHY_OUI_VITESSE 0x008083 ++#define PHY_OUI_DEFAULT 0xFFFFFF ++ ++unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr); ++void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, ++ unsigned short data); ++ ++static int phy_address[2] = {0, 1}; ++static u32 phy_oui; ++static void switchip_mdio_poll_init(void); ++static void _switchip_mdio_poll(struct work_struct *work); ++ ++/* struct workqueue_struct mdio_poll_task; */ ++static struct workqueue_struct *mdio_poll_workqueue; ++DECLARE_DELAYED_WORK(mdio_poll_work, _switchip_mdio_poll); ++static int old_link_status[2] = {-1, -1}; ++ ++/** ++ * Autonegotiation check. ++ * This funtion checks for link changes. If a link change has occured it will ++ * update certain switch registers. ++ */ ++static void _switchip_check_phy_status(int port) ++{ ++ int new_link_status; ++ unsigned short reg1; ++ ++ reg1 = switchip_phy_read(phy_address[port], 1); ++ if ((reg1 == 0xFFFF) || (reg1 == 0x0000)) ++ return; /* no PHY connected */ ++ ++ new_link_status = reg1 & 4; ++ if (old_link_status[port] ^ new_link_status) { ++ /* link status change */ ++ if (!new_link_status) { ++ if (port == 0) ++ es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p0_ctl); ++ else ++ es_w32_mask(LTQ_ES_P0_CTL_REG_FLP, 0, p1_ctl); ++ ++ /* read again; link bit is latched low! */ ++ reg1 = switchip_phy_read(phy_address[port], 1); ++ new_link_status = reg1 & 4; ++ } ++ ++ if (new_link_status) { ++ unsigned short reg0, reg4, reg5, reg9, reg10; ++ int phy_pause, phy_speed, phy_duplex; ++ int aneg_enable, aneg_cmpt; ++ ++ reg0 = switchip_phy_read(phy_address[port], 0); ++ reg4 = switchip_phy_read(phy_address[port], 4); ++ aneg_enable = reg0 & 0x1000; ++ aneg_cmpt = reg1 & 0x20; ++ ++ if (aneg_enable && aneg_cmpt) { ++ reg5 = switchip_phy_read(phy_address[port], 5); ++ switch (phy_oui) { ++#ifdef CONFIG_LANTIQ_MACH_EASY336 ++ case PHY_OUI_PMC: ++ /* PMC Sierra supports 1Gigabit FD, ++ * only. On successful ++ * auto-negotiation, we are sure this ++ * is what the LP can. */ ++ phy_pause = ((reg4 & reg5) & 0x0080) >> 7; ++ phy_speed = 2; ++ phy_duplex = 1; ++ break; ++#endif ++ case PHY_OUI_VITESSE: ++ case PHY_OUI_DEFAULT: ++ reg9 = switchip_phy_read(phy_address[port], 9); ++ reg10 = switchip_phy_read(phy_address[port], 10); ++ ++ /* Check if advertise and partner ++ * agree on pause */ ++ phy_pause = ((reg4 & reg5) & 0x0400) >> 10; ++ ++ /* Find the best mode both partners ++ * support ++ * Priority: 1GB-FD, 1GB-HD, 100MB-FD, ++ * 100MB-HD, 10MB-FD, 10MB-HD */ ++ phy_speed = ((((reg9<<2) & reg10) ++ & 0x0c00) >> 6) | ++ (((reg4 & reg5) & 0x01e0) >> 5); ++ ++ if (phy_speed >= 0x0020) { ++ phy_speed = 2; ++ phy_duplex = 1; ++ } else if (phy_speed >= 0x0010) { ++ phy_speed = 2; ++ phy_duplex = 0; ++ } else if (phy_speed >= 0x0008) { ++ phy_speed = 1; ++ phy_duplex = 1; ++ } else if (phy_speed >= 0x0004) { ++ phy_speed = 1; ++ phy_duplex = 0; ++ } else if (phy_speed >= 0x0002) { ++ phy_speed = 0; ++ phy_duplex = 1; ++ } else { ++ phy_speed = 0; ++ phy_duplex = 0; ++ } ++ break; ++ default: ++ phy_pause = (reg4 & 0x0400) >> 10; ++ phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); ++ phy_duplex = (reg0 >> 8)&1; ++ break; ++ } ++ } else { ++ /* parallel detection or fixed speed */ ++ phy_pause = (reg4 & 0x0400) >> 10; ++ phy_speed = (reg0 & 0x40 ? 2 : (reg0 >> 13)&1); ++ phy_duplex = (reg0 >> 8)&1; ++ } ++ ++ if (port == 0) { ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0SPD, ++ LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(phy_speed), ++ rgmii_ctl); ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0DUP, ++ LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(phy_duplex), ++ rgmii_ctl); ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0FCE, ++ LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), ++ rgmii_ctl); ++ ++ es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); ++ } else { ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1SPD, ++ LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(phy_speed), ++ rgmii_ctl); ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1DUP, ++ LTQ_ES_RGMII_CTL_REG_P1DUP_VAL(phy_duplex), ++ rgmii_ctl); ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1FCE, ++ LTQ_ES_RGMII_CTL_REG_P0FCE_VAL(phy_pause), ++ rgmii_ctl); ++ ++ es_w32_mask(1, LTQ_ES_P0_CTL_REG_FLP, p1_ctl); ++ } ++ } ++ } ++ old_link_status[port] = new_link_status; ++} ++ ++static void _switchip_mdio_poll(struct work_struct *work) ++{ ++ if (es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) { ++ _switchip_check_phy_status(0); ++ _switchip_check_phy_status(1); ++ } ++ ++ queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); ++} ++ ++static void switchip_mdio_poll_init(void) ++{ ++ mdio_poll_workqueue = create_workqueue("SVIP MDIP poll"); ++ INIT_DELAYED_WORK(&mdio_poll_work, _switchip_mdio_poll); ++ ++ queue_delayed_work(mdio_poll_workqueue, &mdio_poll_work, HZ/2); ++ ++} ++ ++unsigned short switchip_phy_read(unsigned int phyaddr, unsigned int regaddr) ++{ ++ /* TODO: protect MDIO access with semaphore */ ++ es_w32(LTQ_ES_MDIO_CTL_REG_MBUSY ++ | LTQ_ES_MDIO_CTL_REG_OP_VAL(2) /* read operation */ ++ | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) ++ | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); ++ while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); ++ ++ return es_r32(mdio_data) & 0xFFFF; ++} ++EXPORT_SYMBOL(switchip_phy_read); ++ ++void switchip_phy_write(unsigned int phyaddr, unsigned int regaddr, ++ unsigned short data) ++{ ++ /* TODO: protect MDIO access with semaphore */ ++ es_w32(LTQ_ES_MDIO_CTL_REG_WD_VAL(data) ++ | LTQ_ES_MDIO_CTL_REG_MBUSY ++ | LTQ_ES_MDIO_CTL_REG_OP_VAL(1) /* write operation */ ++ | LTQ_ES_MDIO_CTL_REG_PHYAD_VAL(phyaddr) ++ | LTQ_ES_MDIO_CTL_REG_REGAD_VAL(regaddr), mdio_ctl); ++ while (es_r32(mdio_ctl) & LTQ_ES_MDIO_CTL_REG_MBUSY); ++ ++ return; ++} ++EXPORT_SYMBOL(switchip_phy_write); ++ ++const static u32 switch_reset_offset_000[] = { ++ /*b8000000:*/ 0xffffffff, 0x00000001, 0x00000001, 0x00000003, ++ /*b8000010:*/ 0x04070001, 0x04070001, 0x04070001, 0xffffffff, ++ /*b8000020:*/ 0x00001be8, 0x00001be8, 0x00001be8, 0xffffffff, ++ /*b8000030:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, ++ /*b8000040:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, ++ /*b8000050:*/ 0x00000000, 0x00000000, 0x00080004, 0x00020001, ++ /*b8000060:*/ 0x00000000, 0x00000000, 0x00081000, 0x001f7777, ++ /*b8000070:*/ 0x00000000, 0x00000000, 0x0c00ac2b, 0x0000fa50, ++ /*b8000080:*/ 0x00001000, 0x00001800, 0x00000000, 0x00000000, ++ /*b8000090:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b80000a0:*/ 0x00000000, 0x00000050, 0x00000010, 0x00000000, ++ /*b80000b0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b80000c0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b80000d0:*/ 0xffffffff, 0x00000000, 0x00000000 ++}; ++const static u32 switch_reset_offset_100[] = { ++ /*b8000100:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000110:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000120:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000130:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000140:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000150:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000160:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000170:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000180:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b8000190:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b80001a0:*/ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ /*b80001b0:*/ 0x00000000, 0x00000000 ++}; ++ ++/* ++ * Switch Reset. ++ */ ++void switchip_reset(void) ++{ ++ volatile unsigned int *reg; ++ volatile unsigned int rdreg; ++ int i; ++ ++ sys1_w32(SYS1_CLKENR_ETHSW, clkenr); ++ asm("sync"); ++ ++ /* disable P0 */ ++ es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p0_ctl); ++ /* disable P1 */ ++ es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p1_ctl); ++ /* disable P2 */ ++ es_w32_mask(0, LTQ_ES_P0_CTL_REG_SPS_VAL(1), p2_ctl); ++ ++ /************************************** ++ * BEGIN: Procedure to clear MAC table ++ **************************************/ ++ for (i = 0; i < 3; i++) { ++ int result; ++ ++ /* check if access engine is available */ ++ while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); ++ ++ /* initialise to first address */ ++ es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(3) ++ | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(0), adr_tb_ctl2); ++ ++ /* wait while busy */ ++ while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); ++ ++ /* setup the portmap */ ++ es_w32_mask(0, LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1 << i), ++ adr_tb_ctl1); ++ ++ do { ++ /* search for addresses by port */ ++ es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(2) ++ | LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(9), adr_tb_ctl2); ++ ++ /* wait while busy */ ++ while (es_r32(adr_tb_st2) & LTQ_ES_ADR_TB_ST2_REG_BUSY); ++ ++ result = LTQ_ES_ADR_TB_ST2_REG_RSLT_GET(es_r32(adr_tb_st2)); ++ if (result == 0x101) { ++ printk(KERN_ERR "%s, cmd error\n", __func__); ++ return; ++ } ++ /* if Command OK, address found... */ ++ if (result == 0) { ++ unsigned char mac[6]; ++ ++ mac[5] = (es_r32(adr_tb_st0) >> 0) & 0xff; ++ mac[4] = (es_r32(adr_tb_st0) >> 8) & 0xff; ++ mac[3] = (es_r32(adr_tb_st0) >> 16) & 0xff; ++ mac[2] = (es_r32(adr_tb_st0) >> 24) & 0xff; ++ mac[1] = (es_r32(adr_tb_st1) >> 0) & 0xff; ++ mac[0] = (es_r32(adr_tb_st1) >> 8) & 0xff; ++ ++ /* setup address */ ++ es_w32((mac[5] << 0) | ++ (mac[4] << 8) | ++ (mac[3] << 16) | ++ (mac[2] << 24), adr_tb_ctl0); ++ es_w32(LTQ_ES_ADR_TB_CTL1_REG_PMAP_VAL(1<<i) | ++ LTQ_ES_ADR_TB_CTL1_REG_FID_VAL(0) | ++ (mac[0] << 8) | ++ (mac[1] << 0), adr_tb_ctl1); ++ /* erase address */ ++ ++ es_w32(LTQ_ES_ADR_TB_CTL2_REG_CMD_VAL(1) | ++ LTQ_ES_ADR_TB_CTL2_REG_AC_VAL(15), ++ adr_tb_ctl2); ++ ++ /* wait, while busy */ ++ while (es_r32(adr_tb_st2) & ++ LTQ_ES_ADR_TB_ST2_REG_BUSY); ++ } ++ } while (result == 0); ++ } ++ /************************************** ++ * END: Procedure to clear MAC table ++ **************************************/ ++ ++ /* reset RMON counters */ ++ es_w32(LTQ_ES_RMON_CTL_REG_BAS | LTQ_ES_RMON_CTL_REG_CAC_VAL(3), ++ rmon_ctl); ++ ++ /* bring all registers to reset state */ ++ reg = LTQ_ES_PS_REG; ++ for (i = 0; i < ARRAY_SIZE(switch_reset_offset_000); i++) { ++ if ((reg == LTQ_ES_PS_REG) || ++ (reg >= LTQ_ES_ADR_TB_CTL0_REG && ++ reg <= LTQ_ES_ADR_TB_ST2_REG)) ++ continue; ++ ++ if (switch_reset_offset_000[i] != 0xFFFFFFFF) { ++ /* write reset value to register */ ++ *reg = switch_reset_offset_000[i]; ++ /* read register value back */ ++ rdreg = *reg; ++ if (reg == LTQ_ES_SW_GCTL1_REG) ++ rdreg &= ~LTQ_ES_SW_GCTL1_REG_BISTDN; ++ /* compare read value with written one */ ++ if (rdreg != switch_reset_offset_000[i]) { ++ printk(KERN_ERR "%s,%d: reg %08x mismatch " ++ "[has:%08x, expect:%08x]\n", ++ __func__, __LINE__, ++ (unsigned int)reg, rdreg, ++ switch_reset_offset_000[i]); ++ } ++ } ++ reg++; ++ } ++ ++ reg = LTQ_ES_VLAN_FLT0_REG; ++ for (i = 0; i < ARRAY_SIZE(switch_reset_offset_100); i++) { ++ *reg = switch_reset_offset_100[i]; ++ rdreg = *reg; ++ if (rdreg != switch_reset_offset_100[i]) { ++ printk(KERN_ERR "%s,%d: reg %08x mismatch " ++ "[has:%08x, expect:%08x]\n", __func__, __LINE__, ++ (unsigned int)reg, rdreg, ++ switch_reset_offset_100[i]); ++ } ++ reg++; ++ } ++} ++EXPORT_SYMBOL(switchip_reset); ++ ++static u32 get_phy_oui(unsigned char phy_addr) ++{ ++ u32 oui; ++ int i, bit, byte, shift, w; ++ u16 reg_id[2]; ++ ++ /* read PHY identifier registers 1 and 2 */ ++ reg_id[0] = switchip_phy_read(phy_addr, 2); ++ reg_id[1] = switchip_phy_read(phy_addr, 3); ++ ++ oui = 0; ++ w = 1; ++ shift = 7; ++ byte = 1; ++ for (i = 0, bit = 10; i <= 21; i++, bit++) { ++ oui |= ((reg_id[w] & (1<<bit)) ? 1 : 0) << shift; ++ if (!(shift % 8)) { ++ byte++; ++ if (byte == 2) ++ shift = 15; ++ else ++ shift = 21; ++ } else { ++ shift--; ++ } ++ if (w == 1 && bit == 15) { ++ bit = -1; ++ w = 0; ++ } ++ } ++ return oui; ++} ++ ++/* ++ * Switch Initialization. ++ */ ++int switchip_init(void) ++{ ++ int eth_port, phy_present = 0; ++ u16 reg, mode; ++ ++ sys1_w32(SYS1_CLKENR_ETHSW, clkenr); ++ asm("sync"); ++ ++ /* Enable Switch, if not already done so */ ++ if ((es_r32(sw_gctl0) & LTQ_ES_SW_GCTL0_REG_SE) == 0) ++ es_w32_mask(0, LTQ_ES_SW_GCTL0_REG_SE, sw_gctl0); ++ /* Wait for completion of MBIST */ ++ while (LTQ_ES_SW_GCTL1_REG_BISTDN_GET(es_r32(sw_gctl1)) == 0); ++ ++ switchip_reset(); ++ ++ mode = LTQ_ES_RGMII_CTL_REG_IS_GET(es_r32(rgmii_ctl)); ++ eth_port = (mode == 2 ? 1 : 0); ++ ++ /* Set the primary port(port toward backplane) as sniffer port, ++ changing from P2 which is the reset setting */ ++ es_w32_mask(LTQ_ES_SW_GCTL0_REG_SNIFFPN, ++ LTQ_ES_SW_GCTL0_REG_SNIFFPN_VAL(eth_port), ++ sw_gctl0); ++ ++ /* Point MDIO state machine to invalid PHY addresses 8 and 9 */ ++ es_w32_mask(0, LTQ_ES_SW_GCTL0_REG_PHYBA, sw_gctl0); ++ ++ /* Add CRC for packets from DMA to PMAC. ++ Remove CRC for packets from PMAC to DMA. */ ++ es_w32(LTQ_ES_PMAC_HD_CTL_RC | LTQ_ES_PMAC_HD_CTL_AC, pmac_hd_ctl); ++ ++ phy_oui = get_phy_oui(0); ++ switch (phy_oui) { ++#ifdef CONFIG_LANTIQ_MACH_EASY336 ++ case PHY_OUI_PMC: ++ phy_address[0] = (mode == 2 ? -1 : 2); ++ phy_address[1] = (mode == 2 ? 2 : -1); ++ break; ++#endif ++ case PHY_OUI_VITESSE: ++ default: ++ phy_oui = PHY_OUI_DEFAULT; ++ phy_address[0] = (mode == 2 ? 1 : 0); ++ phy_address[1] = (mode == 2 ? 0 : 1); ++ break; ++ } ++ ++ /****** PORT 0 *****/ ++ reg = switchip_phy_read(phy_address[0], 1); ++ if ((reg != 0x0000) && (reg != 0xffff)) { ++ /* PHY connected? */ ++ phy_present |= 1; ++ /* Set Rx- and TxDelay in case of RGMII */ ++ switch (mode) { ++ case 0: /* *RGMII,RGMII */ ++ case 2: /* RGMII,*GMII */ ++ /* program clock delay in PHY, not in SVIP */ ++ ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0RDLY, 0, rgmii_ctl); ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0TDLY, 0, rgmii_ctl); ++ if (phy_oui == PHY_OUI_VITESSE || ++ phy_oui == PHY_OUI_DEFAULT) { ++ switchip_phy_write(phy_address[0], 31, 0x0001); ++ switchip_phy_write(phy_address[0], 28, 0xA000); ++ switchip_phy_write(phy_address[0], 31, 0x0000); ++ } ++ default: ++ break; ++ } ++ if (phy_oui == PHY_OUI_VITESSE || ++ phy_oui == PHY_OUI_DEFAULT) { ++ /* Program PHY advertisements and ++ * restart auto-negotiation */ ++ switchip_phy_write(phy_address[0], 4, 0x05E1); ++ switchip_phy_write(phy_address[0], 9, 0x0300); ++ switchip_phy_write(phy_address[0], 0, 0x3300); ++ } else { ++ reg = switchip_phy_read(phy_address[1], 0); ++ reg |= 0x1000; /* auto-negotiation enable */ ++ switchip_phy_write(phy_address[1], 0, reg); ++ reg |= 0x0200; /* auto-negotiation restart */ ++ switchip_phy_write(phy_address[1], 0, reg); ++ } ++ } else { ++ /* Force SWITCH link with highest capability: ++ * 100M FD for MII ++ * 1G FD for GMII/RGMII ++ */ ++ switch (mode) { ++ case 1: /* *MII,MII */ ++ case 3: /* *MII,RGMII */ ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(1), ++ rgmii_ctl); ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(1), ++ rgmii_ctl); ++ break; ++ case 0: /* *RGMII,RGMII */ ++ case 2: /* RGMII,*GMII */ ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0SPD_VAL(2), ++ rgmii_ctl); ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0DUP_VAL(1), ++ rgmii_ctl); ++ ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P0RDLY, 0, rgmii_ctl); ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P0TDLY_VAL(2), ++ rgmii_ctl); ++ break; ++ } ++ ++ es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); ++ } ++ ++ /****** PORT 1 *****/ ++ reg = switchip_phy_read(phy_address[1], 1); ++ if ((reg != 0x0000) && (reg != 0xffff)) { ++ /* PHY connected? */ ++ phy_present |= 2; ++ /* Set Rx- and TxDelay in case of RGMII */ ++ switch (mode) { ++ case 0: /* *RGMII,RGMII */ ++ case 3: /* *MII,RGMII */ ++ /* program clock delay in PHY, not in SVIP */ ++ ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1RDLY, 0, rgmii_ctl); ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1TDLY, 0, rgmii_ctl); ++ if (phy_oui == PHY_OUI_VITESSE || ++ phy_oui == PHY_OUI_DEFAULT) { ++ switchip_phy_write(phy_address[1], 31, 0x0001); ++ switchip_phy_write(phy_address[1], 28, 0xA000); ++ switchip_phy_write(phy_address[1], 31, 0x0000); ++ } ++ break; ++ case 2: /* RGMII,*GMII */ ++ ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), ++ rgmii_ctl); ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); ++#ifdef CONFIG_LANTIQ_MACH_EASY336 ++ if (phy_oui == PHY_OUI_PMC) { ++ switchip_phy_write(phy_address[1], 24, 0x0510); ++ switchip_phy_write(phy_address[1], 17, 0xA38C); ++ switchip_phy_write(phy_address[1], 17, 0xA384); ++ } ++#endif ++ break; ++ default: ++ break; ++ } ++ /* Program PHY advertisements and restart auto-negotiation */ ++ if (phy_oui == PHY_OUI_VITESSE || ++ phy_oui == PHY_OUI_DEFAULT) { ++ switchip_phy_write(phy_address[1], 4, 0x05E1); ++ switchip_phy_write(phy_address[1], 9, 0x0300); ++ switchip_phy_write(phy_address[1], 0, 0x3300); ++ } else { ++ reg = switchip_phy_read(phy_address[1], 0); ++ reg |= 0x1000; /* auto-negotiation enable */ ++ switchip_phy_write(phy_address[1], 0, reg); ++ reg |= 0x0200; /* auto-negotiation restart */ ++ switchip_phy_write(phy_address[1], 0, reg); ++ } ++ } else { ++ /* Force SWITCH link with highest capability: ++ * 100M FD for MII ++ * 1G FD for GMII/RGMII ++ */ ++ switch (mode) { ++ case 1: /* *MII,MII */ ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(1), ++ rgmii_ctl); ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); ++ break; ++ case 0: /* *RGMII,RGMII */ ++ case 3: /* *MII,RGMII */ ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), ++ rgmii_ctl); ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); ++ es_w32_mask(LTQ_ES_RGMII_CTL_REG_P1RDLY, 0, rgmii_ctl); ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1TDLY_VAL(2), ++ rgmii_ctl); ++ break; ++ case 2: /* RGMII,*GMII */ ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1SPD_VAL(2), ++ rgmii_ctl); ++ es_w32_mask(0, LTQ_ES_RGMII_CTL_REG_P1DUP, rgmii_ctl); ++ break; ++ } ++ es_w32_mask(0, LTQ_ES_P0_CTL_REG_FLP, p0_ctl); ++ } ++ ++ /* ++ * Allow unknown unicast/multicast and broadcasts ++ * on all ports. ++ */ ++ ++ es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_UP_VAL(7), sw_gctl1); ++ es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_BP_VAL(7), sw_gctl1); ++ es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_MP_VAL(7), sw_gctl1); ++ es_w32_mask(0, LTQ_ES_SW_GCTL1_REG_RP_VAL(7), sw_gctl1); ++ ++ /* Enable LAN port(s) */ ++ if (eth_port == 0) ++ es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p0_ctl); ++ else ++ es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p1_ctl); ++ /* Enable CPU Port (Forwarding State) */ ++ es_w32_mask(LTQ_ES_P0_CTL_REG_SPS, 0, p2_ctl); ++ ++ if (phy_present) ++ switchip_mdio_poll_init(); ++ ++ return 0; ++} ++EXPORT_SYMBOL(switchip_init); ++ ++device_initcall(switchip_init); +Index: linux-3.3.8/arch/mips/lantiq/Platform +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/Platform 2012-07-31 19:51:32.289105839 +0200 ++++ linux-3.3.8/arch/mips/lantiq/Platform 2012-07-31 19:51:34.153105919 +0200 +@@ -7,3 +7,4 @@ + load-$(CONFIG_LANTIQ) = 0xffffffff80002000 + cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway + cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon ++cflags-$(CONFIG_SOC_SVIP) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/svip +Index: linux-3.3.8/arch/mips/lantiq/clk.h +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/clk.h 2012-07-31 19:51:33.501105891 +0200 ++++ linux-3.3.8/arch/mips/lantiq/clk.h 2012-07-31 19:51:34.153105919 +0200 +@@ -56,6 +56,10 @@ + extern unsigned long ltq_danube_fpi_hz(void); + extern unsigned long ltq_danube_io_region_clock(void); + ++extern unsigned long ltq_svip_cpu_hz(void); ++extern unsigned long ltq_svip_fpi_hz(void); ++extern unsigned long ltq_svip_io_region_clock(void); ++ + extern unsigned long ltq_ar9_cpu_hz(void); + extern unsigned long ltq_ar9_fpi_hz(void); + +Index: linux-3.3.8/drivers/net/ethernet/Kconfig +=================================================================== +--- linux-3.3.8.orig/drivers/net/ethernet/Kconfig 2012-07-31 19:51:33.105105873 +0200 ++++ linux-3.3.8/drivers/net/ethernet/Kconfig 2012-07-31 19:51:34.153105919 +0200 +@@ -91,6 +91,18 @@ + ---help--- + Support for the MII0 inside the Lantiq SoC + ++config LANTIQ_SVIP_ETH ++ default y ++ tristate "Lantiq SoC SVIP Ethernet driver" ++ depends on SOC_SVIP ++ help ++ Support for the MII0 inside the Lantiq SVIP SoC ++ ++config LANTIQ_SVIP_VIRTUAL_ETH ++ default y ++ tristate "Lantiq SoC SVIP Virtual Ethernet driver" ++ depends on SOC_SVIP ++ + source "drivers/net/ethernet/marvell/Kconfig" + source "drivers/net/ethernet/mellanox/Kconfig" + source "drivers/net/ethernet/micrel/Kconfig" +Index: linux-3.3.8/drivers/net/ethernet/Makefile +=================================================================== +--- linux-3.3.8.orig/drivers/net/ethernet/Makefile 2012-07-31 19:51:33.105105873 +0200 ++++ linux-3.3.8/drivers/net/ethernet/Makefile 2012-07-31 19:51:34.153105919 +0200 +@@ -37,6 +37,8 @@ + obj-$(CONFIG_KORINA) += korina.o + obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o + obj-$(CONFIG_LANTIQ_VRX200) += lantiq_vrx200.o ++obj-$(CONFIG_LANTIQ_SVIP_ETH) += svip_eth.o ++obj-$(CONFIG_LANTIQ_SVIP_VIRTUAL_ETH) += svip_virtual_eth.o + obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/ + obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/ + obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/ diff --git a/target/linux/lantiq/patches-3.3/535-svip_cp1.patch b/target/linux/lantiq/patches-3.3/535-svip_cp1.patch new file mode 100644 index 0000000000..84b483b6f1 --- /dev/null +++ b/target/linux/lantiq/patches-3.3/535-svip_cp1.patch @@ -0,0 +1,81 @@ +Index: linux-3.3.8/arch/mips/lantiq/devices.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/devices.c 2012-07-31 09:45:42.315551926 +0200 ++++ linux-3.3.8/arch/mips/lantiq/devices.c 2012-07-31 09:46:14.051553281 +0200 +@@ -102,19 +102,29 @@ + } + #endif + ++#ifdef CONFIG_SOC_SVIP ++extern unsigned int *prom_cp1_base; ++#else + static unsigned int *cp1_base = 0; ++#endif + unsigned int* + ltq_get_cp1_base(void) + { ++#ifdef CONFIG_SOC_SVIP ++ return prom_cp1_base; ++#else + return cp1_base; ++#endif + } + EXPORT_SYMBOL(ltq_get_cp1_base); + + void __init + ltq_register_tapi(void) + { ++#ifndef CONFIG_SOC_SVIP + #define CP1_SIZE (1 << 20) + dma_addr_t dma; + cp1_base = + (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC)); ++#endif + } +Index: linux-3.3.8/arch/mips/lantiq/prom.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/prom.c 2012-07-31 09:45:42.315551926 +0200 ++++ linux-3.3.8/arch/mips/lantiq/prom.c 2012-07-31 10:31:28.759669332 +0200 +@@ -129,6 +129,7 @@ + } + EXPORT_SYMBOL(ltq_remap_resource); + ++ + void __init prom_init(void) + { + ltq_soc_detect(&soc_info); +Index: linux-3.3.8/arch/mips/lantiq/setup.c +=================================================================== +--- linux-3.3.8.orig/arch/mips/lantiq/setup.c 2012-07-31 09:45:42.315551926 +0200 ++++ linux-3.3.8/arch/mips/lantiq/setup.c 2012-07-31 10:31:35.215669606 +0200 +@@ -21,8 +21,15 @@ + /* set to 1 if the bootloader is BRN-BOOT instead of u-boot */ + unsigned long ltq_brn_boot = 0; + ++#ifdef CONFIG_SOC_SVIP ++unsigned int *prom_cp1_base; ++#endif ++ + void __init plat_mem_setup(void) + { ++#ifdef CONFIG_SOC_SVIP ++ int prom_cp1_size = 0x800000; ++#endif + /* assume 16M as default incase uboot fails to pass proper ramsize */ + unsigned long memsize = 16; + char **envp = (char **) KSEG1ADDR(fw_arg2); +@@ -54,6 +61,14 @@ + envp++; + } + memsize *= 1024 * 1024; ++ ++#ifdef CONFIG_SOC_SVIP ++ memsize -= prom_cp1_size; ++ prom_cp1_base = (unsigned int *)KSEG1ADDR(memsize); ++ ++ printk("Using %ldMB Ram and reserving %dMB for cp1\n", ++ memsize>>20, prom_cp1_size>>20); ++#endif + add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); + } + diff --git a/target/linux/lantiq/svip_be/config-default b/target/linux/lantiq/svip_be/config-default new file mode 100644 index 0000000000..27a06be9de --- /dev/null +++ b/target/linux/lantiq/svip_be/config-default @@ -0,0 +1,39 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +CONFIG_BOARD_SCACHE=y +CONFIG_CLKDEV_LOOKUP=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_FSNOTIFY=y +# CONFIG_GENERIC_PWM is not set +CONFIG_HAVE_MACH_CLKDEV=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +CONFIG_IRQ_FORCED_THREADING=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_MACH_EASY33016=y +CONFIG_LANTIQ_MACH_EASY336=y +CONFIG_LANTIQ_SVIP_ETH=y +CONFIG_LANTIQ_SVIP_VIRTUAL_ETH=y +CONFIG_MDIO_BOARDINFO=y +CONFIG_MIPS_CPU_SCACHE=y +CONFIG_MIPS_L1_CACHE_SHIFT=6 +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_ECC=y +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_SM_COMMON is not set +CONFIG_RTL8306_PHY=y +# CONFIG_SOC_AMAZON_SE is not set +# CONFIG_SOC_FALCON is not set +CONFIG_SOC_SVIP=y +# CONFIG_SOC_TYPE_XWAY is not set +# CONFIG_SOC_XWAY is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_SVIP=y +CONFIG_SVIP_NAT=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB_SUPPORT=y diff --git a/target/linux/lantiq/svip_be/profiles/000-generic.mk b/target/linux/lantiq/svip_be/profiles/000-generic.mk new file mode 100644 index 0000000000..731e4fce5a --- /dev/null +++ b/target/linux/lantiq/svip_be/profiles/000-generic.mk @@ -0,0 +1,8 @@ +define Profile/Generic + NAME:=Generic - all boards + PACKAGES:= +endef + +$(eval $(call Profile,Generic)) + + diff --git a/target/linux/lantiq/svip_be/profiles/001-lantiq.mk b/target/linux/lantiq/svip_be/profiles/001-lantiq.mk new file mode 100644 index 0000000000..5503790aff --- /dev/null +++ b/target/linux/lantiq/svip_be/profiles/001-lantiq.mk @@ -0,0 +1,25 @@ +define Profile/EASY336 + NAME:=EASY336 + PACKAGES:= +endef + +define Profile/EASY336/Description + Lantiq EASY336 evalkit +endef + +$(eval $(call Profile,EASY336)) + +define Profile/EASY33016 + NAME:=EASY33016 + PACKAGES:= \ + kmod-ifxos ifx-vos ifx-evtlog svip-switch \ + voice-lib-tapi voice-lib-cli voice-tapi-cli \ + voice-tapi voice-tapidemo-xt voice-vatests voice-vxt voice-xtbox +endef + +define Profile/EASY33016/Description + Lantiq EASY33016 evalkit +endef + +$(eval $(call Profile,EASY33016)) + diff --git a/target/linux/lantiq/svip_be/target.mk b/target/linux/lantiq/svip_be/target.mk new file mode 100644 index 0000000000..d68e9dd02e --- /dev/null +++ b/target/linux/lantiq/svip_be/target.mk @@ -0,0 +1,11 @@ +ARCH:=mips +SUBTARGET:=svip_be +BOARDNAME:=SVIP Big Endian +FEATURES:=squashfs jffs2 +DEVICE_TYPE:=other + +DEFAULT_PACKAGES+= uboot-svip hostapd-mini + +define Target/Description + Lantiq SVIP Big Endian +endef diff --git a/target/linux/lantiq/svip_le/config-default b/target/linux/lantiq/svip_le/config-default new file mode 100644 index 0000000000..e98ec854db --- /dev/null +++ b/target/linux/lantiq/svip_le/config-default @@ -0,0 +1,35 @@ +CONFIG_ADM6996_PHY=y +CONFIG_AR8216_PHY=y +CONFIG_CLKDEV_LOOKUP=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_FSNOTIFY=y +# CONFIG_GENERIC_PWM is not set +CONFIG_HAVE_MACH_CLKDEV=y +CONFIG_INPUT=y +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_POLLDEV=y +CONFIG_IRQ_FORCED_THREADING=y +# CONFIG_ISDN is not set +CONFIG_LANTIQ_MACH_EASY33016=y +CONFIG_LANTIQ_MACH_EASY336=y +CONFIG_MDIO_BOARDINFO=y +# CONFIG_PCIE_LANTIQ is not set +# CONFIG_PCI_LANTIQ is not set +# CONFIG_PCI_LANTIQ_NONE is not set +CONFIG_RTL8306_PHY=y +# CONFIG_SOC_AMAZON_SE is not set +# CONFIG_SOC_FALCON is not set +CONFIG_SOC_SVIP=y +# CONFIG_SOC_TYPE_XWAY is not set +# CONFIG_SOC_XWAY is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_SVIP=y +CONFIG_SVIP_NAT=y +CONFIG_LANTIQ_SVIP_VIRTUAL_ETH=y +CONFIG_LANTIQ_SVIP_ETH=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +# CONFIG_USB_ARCH_HAS_EHCI is not set +# CONFIG_USB_ARCH_HAS_OHCI is not set +# CONFIG_USB_ARCH_HAS_XHCI is not set +CONFIG_USB_SUPPORT=y diff --git a/target/linux/lantiq/svip_le/profiles/000-generic.mk b/target/linux/lantiq/svip_le/profiles/000-generic.mk new file mode 100644 index 0000000000..731e4fce5a --- /dev/null +++ b/target/linux/lantiq/svip_le/profiles/000-generic.mk @@ -0,0 +1,8 @@ +define Profile/Generic + NAME:=Generic - all boards + PACKAGES:= +endef + +$(eval $(call Profile,Generic)) + + diff --git a/target/linux/lantiq/svip_le/profiles/001-lantiq.mk b/target/linux/lantiq/svip_le/profiles/001-lantiq.mk new file mode 100644 index 0000000000..dd6150e126 --- /dev/null +++ b/target/linux/lantiq/svip_le/profiles/001-lantiq.mk @@ -0,0 +1,10 @@ +define Profile/EASY336 + NAME:=EASY336 + PACKAGES:= +endef + +define Profile/EASY336/Description + Lantiq EASY336 evalkit +endef + +$(eval $(call Profile,EASY336)) diff --git a/target/linux/lantiq/svip_le/target.mk b/target/linux/lantiq/svip_le/target.mk new file mode 100644 index 0000000000..60bcfad714 --- /dev/null +++ b/target/linux/lantiq/svip_le/target.mk @@ -0,0 +1,11 @@ +ARCH:=mipsel +SUBTARGET:=svip_le +BOARDNAME:=SVIP Little Endian +FEATURES:=squashfs jffs2 +DEVICE_TYPE:=other + +DEFAULT_PACKAGES+= uboot-svip hostapd-mini + +define Target/Description + Lantiq SVIP Little Endian +endef diff --git a/target/linux/lantiq/vr9/config-default b/target/linux/lantiq/vr9/config-default index 739f861eab..2e833491ce 100644 --- a/target/linux/lantiq/vr9/config-default +++ b/target/linux/lantiq/vr9/config-default @@ -45,6 +45,7 @@ CONFIG_SCSI_DMA=y # CONFIG_SOC_FALCON is not set CONFIG_SOC_TYPE_XWAY=y CONFIG_SOC_XWAY=y +# CONFIG_SOC_SVIP is not set CONFIG_SPI=y CONFIG_SPI_BITBANG=y CONFIG_SPI_GPIO=y |