diff options
Diffstat (limited to 'target/linux/sunxi/patches-5.4')
15 files changed, 0 insertions, 1213 deletions
diff --git a/target/linux/sunxi/patches-5.4/062-add-sun8i-h3-zeropi-support.patch b/target/linux/sunxi/patches-5.4/062-add-sun8i-h3-zeropi-support.patch deleted file mode 100644 index dc69f70bbe..0000000000 --- a/target/linux/sunxi/patches-5.4/062-add-sun8i-h3-zeropi-support.patch +++ /dev/null @@ -1,79 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -1118,6 +1118,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-h3-orangepi-plus2e.dtb \ - sun8i-h3-orangepi-zero-plus2.dtb \ - sun8i-h3-rervision-dvk.dtb \ -+ sun8i-h3-zeropi.dtb \ - sun8i-r16-bananapi-m2m.dtb \ - sun8i-r16-nintendo-nes-classic.dtb \ - sun8i-r16-nintendo-super-nes-classic.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h3-zeropi.dts -@@ -0,0 +1,66 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+ -+#include "sun8i-h3-nanopi.dtsi" -+ -+/ { -+ model = "FriendlyElec ZeroPi"; -+ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3"; -+ -+ aliases { -+ ethernet0 = &emac; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&gmac_power_pin_nanopi>; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&ehci0 { -+ status = "okay"; -+}; -+ -+&ohci0 { -+ status = "okay"; -+}; -+ -+&pio { -+ gmac_power_pin_nanopi: gmac_power_pin@0 { -+ pins = "PD6"; -+ function = "gpio_out"; -+ }; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ -+ allwinner,leds-active-low; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ status = "okay"; -+ dr_mode = "peripheral"; -+}; -+ -+&usbphy { -+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -+}; diff --git a/target/linux/sunxi/patches-5.4/100-sunxi-h3-add-support-for-nanopi-r1.patch b/target/linux/sunxi/patches-5.4/100-sunxi-h3-add-support-for-nanopi-r1.patch deleted file mode 100644 index 834ea153c8..0000000000 --- a/target/linux/sunxi/patches-5.4/100-sunxi-h3-add-support-for-nanopi-r1.patch +++ /dev/null @@ -1,186 +0,0 @@ -From 5aee0b1272cd5b42933ef629d66b677669e2e8d2 Mon Sep 17 00:00:00 2001 -From: Jayantajit Gogoi <jayanta.gogoi525@gmail.com> -Date: Mon, 12 Oct 2020 05:24:51 +0000 -Subject: [PATCH] sunxi: add support for friendlyarm nanopi r1 - -Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com> ---- - .../devicetree/bindings/arm/sunxi.yaml | 5 + - arch/arm/boot/dts/Makefile | 1 + - arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts | 146 ++++++++++++++++++ - 3 files changed, 152 insertions(+) - create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts - ---- a/Documentation/devicetree/bindings/arm/sunxi.yaml -+++ b/Documentation/devicetree/bindings/arm/sunxi.yaml -@@ -241,6 +241,11 @@ properties: - - const: friendlyarm,nanopi-neo-plus2 - - const: allwinner,sun50i-h5 - -+ - description: FriendlyARM NanoPi R1 -+ items: -+ - const: friendlyarm,nanopi-r1 -+ - const: allwinner,sun8i-h3 -+ - - description: Gemei G9 Tablet - items: - - const: gemei,g9 ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -1109,6 +1109,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ - sun8i-h3-nanopi-m1-plus.dtb \ - sun8i-h3-nanopi-neo.dtb \ - sun8i-h3-nanopi-neo-air.dtb \ -+ sun8i-h3-nanopi-r1.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts -@@ -0,0 +1,146 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com> -+ * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com> -+ */ -+ -+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */ -+#include "sun8i-h3-nanopi.dtsi" -+ -+/ { -+ model = "FriendlyARM NanoPi R1"; -+ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3"; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ vdd_cpux: gpio-regulator { -+ compatible = "regulator-gpio"; -+ pinctrl-names = "default"; -+ regulator-name = "vdd-cpux"; -+ regulator-type = "voltage"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-ramp-delay = <50>; -+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0x1>; -+ states = <1100000 0x0 -+ 1300000 0x1>; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ pinctrl-names = "default"; -+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; -+ }; -+ -+ leds { -+ /delete-node/ pwr; -+ status { -+ label = "nanopi:red:status"; -+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ wan { -+ label = "nanopi:green:wan"; -+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ lan { -+ label = "nanopi:green:lan"; -+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ r_gpio_keys { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sw_r_npi>; -+ -+ /delete-node/ k1; -+ reset { -+ label = "reset"; -+ linux,code = <KEY_RESTART>; -+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpux>; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ sdio_wifi: sdio_wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ interrupt-parent = <&pio>; -+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; -+ interrupt-names = "host-wake"; -+ }; -+}; -+ -+&mmc2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc2_8bit_pins>; -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ bus-width = <8>; -+ non-removable; -+ status = "okay"; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&r_pio { -+ sw_r_npi: key_pins { -+ pins = "PL3"; -+ function = "gpio_in"; -+ }; -+}; diff --git a/target/linux/sunxi/patches-5.4/101-sunxi-h5-add-support-for-nanopi-r1s-h5.patch b/target/linux/sunxi/patches-5.4/101-sunxi-h5-add-support-for-nanopi-r1s-h5.patch deleted file mode 100644 index 339eadcd23..0000000000 --- a/target/linux/sunxi/patches-5.4/101-sunxi-h5-add-support-for-nanopi-r1s-h5.patch +++ /dev/null @@ -1,229 +0,0 @@ -From 9962cb9be2db877c232aaf00db40125c0d7bf4bc Mon Sep 17 00:00:00 2001 -From: Chukun Pan <amadeus@jmu.edu.cn> -Date: Mon, 17 May 2021 00:35:22 +0800 -Subject: [PATCH] arm64: dts: allwinner: h5: Add NanoPi R1S H5 support - -The NanoPi R1S H5 is a open source board made by FriendlyElec. -It has the following features: - -- Allwinner H5, Quad-core Cortex-A53 -- 512MB DDR3 RAM -- 10/100/1000M Ethernet x 2 -- RTL8189ETV WiFi 802.11b/g/n -- USB 2.0 host port (A) -- MicroSD Slot -- Serial Debug Port -- 5V 2A DC power-supply - -Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> -Signed-off-by: Maxime Ripard <maxime@cerno.tech> -Link: https://lore.kernel.org/r/20210516163523.9484-2-amadeus@jmu.edu.cn ---- - arch/arm64/boot/dts/allwinner/Makefile | 1 + - .../dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 195 ++++++++++++++++++ - 2 files changed, 196 insertions(+) - create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts - ---- a/arch/arm64/boot/dts/allwinner/Makefile -+++ b/arch/arm64/boot/dts/allwinner/Makefile -@@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-em - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb -+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb - dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb ---- /dev/null -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -@@ -0,0 +1,190 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn> -+ * -+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is: -+ * Copyright (C) 2017 Antony Antony <antony@phenome.org> -+ * Copyright (C) 2016 ARM Ltd. -+ */ -+ -+/dts-v1/; -+#include "sun50i-h5.dtsi" -+ -+#include <dt-bindings/gpio/gpio.h> -+#include <dt-bindings/input/input.h> -+ -+/ { -+ model = "FriendlyARM NanoPi R1S H5"; -+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5"; -+ -+ aliases { -+ ethernet0 = &emac; -+ ethernet1 = &rtl8189etv; -+ serial0 = &uart0; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ -+ sys { -+ label = "nanopi:red:sys"; -+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; -+ linux,default-trigger = "heartbeat"; -+ }; -+ -+ lan { -+ label = "nanopi:green:lan"; -+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ wan { -+ label = "nanopi:green:wan"; -+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ -+ r-gpio-keys { -+ compatible = "gpio-keys"; -+ -+ reset { -+ label = "reset"; -+ linux,code = <KEY_RESTART>; -+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; -+ }; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ reg_vcc3v3: vcc3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ }; -+ -+ reg_usb0_vbus: usb0-vbus { -+ compatible = "regulator-fixed"; -+ regulator-name = "usb0-vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */ -+ status = "okay"; -+ }; -+ -+ vdd_cpux: gpio-regulator { -+ compatible = "regulator-gpio"; -+ regulator-name = "vdd-cpux"; -+ regulator-type = "voltage"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <1100000>; -+ regulator-max-microvolt = <1300000>; -+ regulator-ramp-delay = <50>; /* 4ms */ -+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; -+ gpios-states = <0x1>; -+ states = <1100000 0x0>, <1300000 0x1>; -+ }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */ -+ post-power-on-delay-ms = <200>; -+ }; -+}; -+ -+&cpu0 { -+ cpu-supply = <&vdd_cpux>; -+}; -+ -+&ehci1 { -+ status = "okay"; -+}; -+ -+&ehci2 { -+ status = "okay"; -+}; -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emac_rgmii_pins>; -+ phy-supply = <®_gmac_3v3>; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-mode = "rgmii"; -+ status = "okay"; -+}; -+ -+&external_mdio { -+ ext_rgmii_phy: ethernet-phy@7 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <7>; -+ }; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ eeprom@51 { -+ compatible = "microchip,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+}; -+ -+&mmc0 { -+ vmmc-supply = <®_vcc3v3>; -+ bus-width = <4>; -+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ -+ status = "okay"; -+}; -+ -+&mmc1 { -+ vmmc-supply = <®_vcc3v3>; -+ vqmmc-supply = <®_vcc3v3>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8189etv: sdio_wifi@1 { -+ reg = <1>; -+ }; -+}; -+ -+&ohci1 { -+ status = "okay"; -+}; -+ -+&ohci2 { -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pa_pins>; -+ status = "okay"; -+}; -+ -+&usb_otg { -+ dr_mode = "peripheral"; -+ status = "okay"; -+}; -+ -+&usbphy { -+ /* USB Type-A port's VBUS is always on */ -+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ -+ usb0_vbus-supply = <®_usb0_vbus>; -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-5.4/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch b/target/linux/sunxi/patches-5.4/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch deleted file mode 100644 index 1ee240afb5..0000000000 --- a/target/linux/sunxi/patches-5.4/102-sunxi-add-OF-node-for-USB-eth-on-NanoPi-R1S-H5.patch +++ /dev/null @@ -1,30 +0,0 @@ -From a896bc1d79e3c00f0aacfe225499d811775616f3 Mon Sep 17 00:00:00 2001 -From: Chukun Pan <amadeus@jmu.edu.cn> -Date: Sun, 10 Oct 2021 21:50:17 +0800 -Subject: [PATCH] arm64: allwinner: add OF node for USB eth on NanoPi R1S H5 - -This adds the OF node for the USB3 ethernet adapter on the FriendlyARM -NanoPi R1S H5. Add the correct value for the RTL8153 LED configuration -register to match the blink behavior of the other port on the device. - -Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> ---- - arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -@@ -111,6 +111,13 @@ - - &ehci1 { - status = "okay"; -+ -+ usb-eth@1 { -+ compatible = "realtek,rtl8153"; -+ reg = <1>; -+ -+ realtek,led-data = <0x78>; -+ }; - }; - - &ehci2 { diff --git a/target/linux/sunxi/patches-5.4/301-orangepi_pc2_usb_otg_to_host_key_power.patch b/target/linux/sunxi/patches-5.4/301-orangepi_pc2_usb_otg_to_host_key_power.patch deleted file mode 100644 index af243ca3e7..0000000000 --- a/target/linux/sunxi/patches-5.4/301-orangepi_pc2_usb_otg_to_host_key_power.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts -@@ -98,7 +98,7 @@ - - sw4 { - label = "sw4"; -- linux,code = <BTN_0>; -+ linux,code = <KEY_POWER>; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; -@@ -238,7 +238,7 @@ - }; - - &usb_otg { -- dr_mode = "otg"; -+ dr_mode = "host"; - status = "okay"; - }; - diff --git a/target/linux/sunxi/patches-5.4/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch b/target/linux/sunxi/patches-5.4/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch deleted file mode 100644 index 1cf94c0b53..0000000000 --- a/target/linux/sunxi/patches-5.4/400-arm64-allwinner-a64-sopine-Add-Sopine-flash-partitio.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 7d87d3dafc4b1ea5659eb71ee6c5fd5308490d1f Mon Sep 17 00:00:00 2001 -From: Oskari Lemmela <oskari@lemmela.net> -Date: Mon, 31 Dec 2018 07:44:49 +0200 -Subject: [PATCH] arm64: allwinner: a64-sopine: Add Sopine flash partitions. - -First 896kB to u-boot. Enough space for SPL, u-boot and ATF. -Next 128kB to u-boot environment and rest to firmware. - -Firmware partition is compatible FIT image dynamic splitting. - -Signed-off-by: Oskari Lemmela <oskari@lemmela.net> ---- - .../boot/dts/allwinner/sun50i-a64-sopine.dtsi | 22 +++++++++++++++++++ - 1 file changed, 22 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine.dtsi -@@ -81,6 +81,28 @@ - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; -+ -+ partitions { -+ compatible = "fixed-partitions"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ partition@0 { -+ label = "u-boot"; -+ reg = <0x000000 0x0E0000>; -+ }; -+ -+ partition@e0000 { -+ label = "u-boot-env"; -+ reg = <0x0E0000 0x020000>; -+ }; -+ -+ partition@100000 { -+ compatible = "denx,fit"; -+ label = "firmware"; -+ reg = <0x100000 0xF00000>; -+ }; -+ }; - }; - }; - diff --git a/target/linux/sunxi/patches-5.4/410-v5.6-arm64-dts-allwinner-a64-olinuxino-Add-bank-supply-re.patch b/target/linux/sunxi/patches-5.4/410-v5.6-arm64-dts-allwinner-a64-olinuxino-Add-bank-supply-re.patch deleted file mode 100644 index 67f7a1536e..0000000000 --- a/target/linux/sunxi/patches-5.4/410-v5.6-arm64-dts-allwinner-a64-olinuxino-Add-bank-supply-re.patch +++ /dev/null @@ -1,58 +0,0 @@ -From f0c3b29f56f0a946df4941edfe2d98e3e766c30f Mon Sep 17 00:00:00 2001 -From: Stefan Mavrodiev <stefan@olimex.com> -Date: Fri, 29 Nov 2019 13:39:40 +0200 -Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: Add bank supply - regulators - -Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL. This -patch adds regulators for them to the pinctrl node. - -Exception is PL which is used by the RSB bus. To avoid circular -dependencies, VCC-PL is omitted. - -On boards with eMMC, VCC-PC is supplied by ELDO1, instead of DCDC1. - -Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> -[Maxime: Changed the r_pio comment a bit] -Signed-off-by: Maxime Ripard <maxime@cerno.tech> ---- - .../dts/allwinner/sun50i-a64-olinuxino-emmc.dts | 4 ++++ - .../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 17 +++++++++++++++++ - 2 files changed, 21 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts -@@ -21,3 +21,7 @@ - cap-mmc-hw-reset; - status = "okay"; - }; -+ -+&pio { -+ vcc-pc-supply = <®_eldo1>; -+}; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -@@ -163,6 +163,23 @@ - status = "okay"; - }; - -+&pio { -+ vcc-pc-supply = <®_dcdc1>; -+ vcc-pd-supply = <®_dcdc1>; -+ vcc-pe-supply = <®_aldo1>; -+ vcc-pg-supply = <®_dldo4>; -+}; -+ -+&r_pio { -+ /* -+ * FIXME: We can't add that supply for now since it would -+ * create a circular dependency between pinctrl, the regulator -+ * and the RSB Bus. -+ * -+ * vcc-pl-supply = <®_aldo2>; -+ */ -+}; -+ - &r_rsb { - status = "okay"; - diff --git a/target/linux/sunxi/patches-5.4/420-v5.7-arm64-dts-allwinner-a64-olinuxino-add-user-red-LED.patch b/target/linux/sunxi/patches-5.4/420-v5.7-arm64-dts-allwinner-a64-olinuxino-add-user-red-LED.patch deleted file mode 100644 index f369cb4f7c..0000000000 --- a/target/linux/sunxi/patches-5.4/420-v5.7-arm64-dts-allwinner-a64-olinuxino-add-user-red-LED.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz> -Date: Wed, 25 Mar 2020 18:11:16 +0100 -Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add user red LED -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -There is a red LED marked as `GPIO_LED1` on the silkscreen and connected -to PE17 by default. So lets add this missing bit in the current hardware -description. - -Signed-off-by: Petr Štetiar <ynezz@true.cz> - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -@@ -70,6 +70,15 @@ - }; - }; - -+ leds { -+ compatible = "gpio-leds"; -+ -+ user { -+ label = "a64-olinuxino:red:user"; -+ gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ -+ }; -+ }; -+ - reg_usb1_vbus: usb1-vbus { - compatible = "regulator-fixed"; - regulator-name = "usb1-vbus"; diff --git a/target/linux/sunxi/patches-5.4/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch b/target/linux/sunxi/patches-5.4/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch deleted file mode 100644 index fa02f48132..0000000000 --- a/target/linux/sunxi/patches-5.4/430-arm64-dts-allwinner-a64-olinuxino-add-status-LED-ali.patch +++ /dev/null @@ -1,32 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Petr=20=C5=A0tetiar?= <ynezz@true.cz> -Date: Thu, 26 Mar 2020 10:09:19 +0100 -Subject: [PATCH] arm64: dts: allwinner: a64: olinuxino: add status LED aliases -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Petr Štetiar <ynezz@true.cz> - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts -@@ -53,6 +53,10 @@ - aliases { - ethernet0 = &emac; - serial0 = &uart0; -+ led-boot = &led_user; -+ led-failsafe = &led_user; -+ led-running = &led_user; -+ led-upgrade = &led_user; - }; - - chosen { -@@ -73,7 +77,7 @@ - leds { - compatible = "gpio-leds"; - -- user { -+ led_user: user { - label = "a64-olinuxino:red:user"; - gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */ - }; diff --git a/target/linux/sunxi/patches-5.4/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch b/target/linux/sunxi/patches-5.4/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch deleted file mode 100644 index 8281f78e06..0000000000 --- a/target/linux/sunxi/patches-5.4/431-arm64-dts-allwinner-nanopi-r1s-h5-add-status-LED.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 1845163a052efac124f00656eb72f38947630a42 Mon Sep 17 00:00:00 2001 -From: Chukun Pan <amadeus@jmu.edu.cn> -Date: Sun, 10 Oct 2021 21:50:18 +0800 -Subject: [PATCH] arm64: dts: allwinner: NanoPi R1S H5: add status LED aliases - -Use the SYS LED on the casing for showing system status. - -Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> ---- - arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 7 ++++++- - 1 file changed, 6 insertions(+), 1 deletion(-) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts -@@ -21,6 +21,11 @@ - ethernet0 = &emac; - ethernet1 = &rtl8189etv; - serial0 = &uart0; -+ -+ led-boot = &led_sys; -+ led-failsafe = &led_sys; -+ led-running = &led_sys; -+ led-upgrade = &led_sys; - }; - - chosen { -@@ -30,7 +35,7 @@ - leds { - compatible = "gpio-leds"; - -- sys { -+ led_sys: sys { - label = "nanopi:red:sys"; - gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; diff --git a/target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch b/target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch deleted file mode 100644 index eb254ee74d..0000000000 --- a/target/linux/sunxi/patches-5.4/440-add-h6-pwm.patch +++ /dev/null @@ -1,305 +0,0 @@ ---- a/drivers/pwm/pwm-sun4i.c -+++ b/drivers/pwm/pwm-sun4i.c -@@ -3,6 +3,10 @@ - * Driver for Allwinner sun4i Pulse Width Modulation Controller - * - * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> -+ * -+ * Limitations: -+ * - When outputing the source clock directly, the PWM logic will be bypassed -+ * and the currently running period is not guaranteed to be completed - */ - - #include <linux/bitops.h> -@@ -16,6 +20,7 @@ - #include <linux/of_device.h> - #include <linux/platform_device.h> - #include <linux/pwm.h> -+#include <linux/reset.h> - #include <linux/slab.h> - #include <linux/spinlock.h> - #include <linux/time.h> -@@ -72,12 +77,15 @@ static const u32 prescaler_table[] = { - - struct sun4i_pwm_data { - bool has_prescaler_bypass; -+ bool has_direct_mod_clk_output; - unsigned int npwm; - }; - - struct sun4i_pwm_chip { - struct pwm_chip chip; -+ struct clk *bus_clk; - struct clk *clk; -+ struct reset_control *rst; - void __iomem *base; - spinlock_t ctrl_lock; - const struct sun4i_pwm_data *data; -@@ -115,6 +123,20 @@ static void sun4i_pwm_get_state(struct p - - val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - -+ /* -+ * PWM chapter in H6 manual has a diagram which explains that if bypass -+ * bit is set, no other setting has any meaning. Even more, experiment -+ * proved that also enable bit is ignored in this case. -+ */ -+ if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && -+ sun4i_pwm->data->has_direct_mod_clk_output) { -+ state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); -+ state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); -+ state->polarity = PWM_POLARITY_NORMAL; -+ state->enabled = true; -+ return; -+ } -+ - if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && - sun4i_pwm->data->has_prescaler_bypass) - prescaler = 1; -@@ -146,13 +168,24 @@ static void sun4i_pwm_get_state(struct p - - static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm, - const struct pwm_state *state, -- u32 *dty, u32 *prd, unsigned int *prsclr) -+ u32 *dty, u32 *prd, unsigned int *prsclr, -+ bool *bypass) - { - u64 clk_rate, div = 0; - unsigned int pval, prescaler = 0; - - clk_rate = clk_get_rate(sun4i_pwm->clk); - -+ *bypass = sun4i_pwm->data->has_direct_mod_clk_output && -+ state->enabled && -+ (state->period * clk_rate >= NSEC_PER_SEC) && -+ (state->period * clk_rate < 2 * NSEC_PER_SEC) && -+ (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); -+ -+ /* Skip calculation of other parameters if we bypass them */ -+ if (*bypass) -+ return 0; -+ - if (sun4i_pwm->data->has_prescaler_bypass) { - /* First, test without any prescaler when available */ - prescaler = PWM_PRESCAL_MASK; -@@ -200,10 +233,11 @@ static int sun4i_pwm_apply(struct pwm_ch - { - struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); - struct pwm_state cstate; -- u32 ctrl; -+ u32 ctrl, duty, period, val; - int ret; -- unsigned int delay_us; -+ unsigned int delay_us, prescaler; - unsigned long now; -+ bool bypass; - - pwm_get_state(pwm, &cstate); - -@@ -218,43 +252,50 @@ static int sun4i_pwm_apply(struct pwm_ch - spin_lock(&sun4i_pwm->ctrl_lock); - ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); - -- if ((cstate.period != state->period) || -- (cstate.duty_cycle != state->duty_cycle)) { -- u32 period, duty, val; -- unsigned int prescaler; -+ ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler, -+ &bypass); -+ if (ret) { -+ dev_err(chip->dev, "period exceeds the maximum value\n"); -+ spin_unlock(&sun4i_pwm->ctrl_lock); -+ if (!cstate.enabled) -+ clk_disable_unprepare(sun4i_pwm->clk); -+ return ret; -+ } - -- ret = sun4i_pwm_calculate(sun4i_pwm, state, -- &duty, &period, &prescaler); -- if (ret) { -- dev_err(chip->dev, "period exceeds the maximum value\n"); -+ if (sun4i_pwm->data->has_direct_mod_clk_output) { -+ if (bypass) { -+ ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); -+ /* We can skip other parameter */ -+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - spin_unlock(&sun4i_pwm->ctrl_lock); -- if (!cstate.enabled) -- clk_disable_unprepare(sun4i_pwm->clk); -- return ret; -+ return 0; -+ } else { -+ ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); - } -+ } - -- if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { -- /* Prescaler changed, the clock has to be gated */ -- ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -- sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); -- -- ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); -- ctrl |= BIT_CH(prescaler, pwm->hwpwm); -- } -+ if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { -+ /* Prescaler changed, the clock has to be gated */ -+ ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -+ sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); - -- val = (duty & PWM_DTY_MASK) | PWM_PRD(period); -- sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); -- sun4i_pwm->next_period[pwm->hwpwm] = jiffies + -- usecs_to_jiffies(cstate.period / 1000 + 1); -- sun4i_pwm->needs_delay[pwm->hwpwm] = true; -+ ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm); -+ ctrl |= BIT_CH(prescaler, pwm->hwpwm); - } - -+ val = (duty & PWM_DTY_MASK) | PWM_PRD(period); -+ sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm)); -+ sun4i_pwm->next_period[pwm->hwpwm] = jiffies + -+ usecs_to_jiffies(cstate.period / 1000 + 1); -+ sun4i_pwm->needs_delay[pwm->hwpwm] = true; -+ - if (state->polarity != PWM_POLARITY_NORMAL) - ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm); - else - ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); - - ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); -+ - if (state->enabled) { - ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); - } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { -@@ -320,6 +361,12 @@ static const struct sun4i_pwm_data sun4i - .npwm = 1, - }; - -+static const struct sun4i_pwm_data sun50i_h6_pwm_data = { -+ .has_prescaler_bypass = true, -+ .has_direct_mod_clk_output = true, -+ .npwm = 2, -+}; -+ - static const struct of_device_id sun4i_pwm_dt_ids[] = { - { - .compatible = "allwinner,sun4i-a10-pwm", -@@ -337,6 +384,9 @@ static const struct of_device_id sun4i_p - .compatible = "allwinner,sun8i-h3-pwm", - .data = &sun4i_pwm_single_bypass, - }, { -+ .compatible = "allwinner,sun50i-h6-pwm", -+ .data = &sun50i_h6_pwm_data, -+ }, { - /* sentinel */ - }, - }; -@@ -361,9 +411,69 @@ static int sun4i_pwm_probe(struct platfo - if (IS_ERR(pwm->base)) - return PTR_ERR(pwm->base); - -- pwm->clk = devm_clk_get(&pdev->dev, NULL); -- if (IS_ERR(pwm->clk)) -+ /* -+ * All hardware variants need a source clock that is divided and -+ * then feeds the counter that defines the output wave form. In the -+ * device tree this clock is either unnamed or called "mod". -+ * Some variants (e.g. H6) need another clock to access the -+ * hardware registers; this is called "bus". -+ * So we request "mod" first (and ignore the corner case that a -+ * parent provides a "mod" clock while the right one would be the -+ * unnamed one of the PWM device) and if this is not found we fall -+ * back to the first clock of the PWM. -+ */ -+ pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); -+ if (IS_ERR(pwm->clk)) { -+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "get mod clock failed %pe\n", -+ pwm->clk); - return PTR_ERR(pwm->clk); -+ } -+ -+ if (!pwm->clk) { -+ pwm->clk = devm_clk_get(&pdev->dev, NULL); -+ if (IS_ERR(pwm->clk)) { -+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "get unnamed clock failed %pe\n", -+ pwm->clk); -+ return PTR_ERR(pwm->clk); -+ } -+ } -+ -+ pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); -+ if (IS_ERR(pwm->bus_clk)) { -+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "get bus clock failed %pe\n", -+ pwm->bus_clk); -+ return PTR_ERR(pwm->bus_clk); -+ } -+ -+ pwm->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); -+ if (IS_ERR(pwm->rst)) { -+ if (PTR_ERR(pwm->rst) != -EPROBE_DEFER) -+ dev_err(&pdev->dev, "get reset failed %pe\n", -+ pwm->rst); -+ return PTR_ERR(pwm->rst); -+ } -+ -+ /* Deassert reset */ -+ ret = reset_control_deassert(pwm->rst); -+ if (ret) { -+ dev_err(&pdev->dev, "cannot deassert reset control: %pe\n", -+ ERR_PTR(ret)); -+ return ret; -+ } -+ -+ /* -+ * We're keeping the bus clock on for the sake of simplicity. -+ * Actually it only needs to be on for hardware register accesses. -+ */ -+ ret = clk_prepare_enable(pwm->bus_clk); -+ if (ret) { -+ dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n", -+ ERR_PTR(ret)); -+ goto err_bus; -+ } - - pwm->chip.dev = &pdev->dev; - pwm->chip.ops = &sun4i_pwm_ops; -@@ -377,19 +487,34 @@ static int sun4i_pwm_probe(struct platfo - ret = pwmchip_add(&pwm->chip); - if (ret < 0) { - dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); -- return ret; -+ goto err_pwm_add; - } - - platform_set_drvdata(pdev, pwm); - - return 0; -+ -+err_pwm_add: -+ clk_disable_unprepare(pwm->bus_clk); -+err_bus: -+ reset_control_assert(pwm->rst); -+ -+ return ret; - } - - static int sun4i_pwm_remove(struct platform_device *pdev) - { - struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); -+ int ret; -+ -+ ret = pwmchip_remove(&pwm->chip); -+ if (ret) -+ return ret; - -- return pwmchip_remove(&pwm->chip); -+ clk_disable_unprepare(pwm->bus_clk); -+ reset_control_assert(pwm->rst); -+ -+ return 0; - } - - static struct platform_driver sun4i_pwm_driver = { diff --git a/target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch b/target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch deleted file mode 100644 index c14e729539..0000000000 --- a/target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch +++ /dev/null @@ -1,35 +0,0 @@ -From: Jernej Skrabec <jernej.skrabec@siol.net> - -Allwinner H6 PWM is similar to that in A20 except that it has additional -bus clock and reset line. - -Note that first PWM channel is connected to output pin and second -channel is used internally, as a clock source to AC200 co-packaged chip. -This means that any combination of these two channels can be used and -thus it doesn't make sense to add pinctrl nodes at this point. - -Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> -Signed-off-by: Clément Péron <peron.clem@gmail.com> ---- - arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ - 1 file changed, 10 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi -@@ -231,6 +231,16 @@ - status = "disabled"; - }; - -+ pwm: pwm@300a000 { -+ compatible = "allwinner,sun50i-h6-pwm"; -+ reg = <0x0300a000 0x400>; -+ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; -+ clock-names = "mod", "bus"; -+ resets = <&ccu RST_BUS_PWM>; -+ #pwm-cells = <3>; -+ status = "disabled"; -+ }; -+ - pio: pinctrl@300b000 { - compatible = "allwinner,sun50i-h6-pinctrl"; - reg = <0x0300b000 0x400>; diff --git a/target/linux/sunxi/patches-5.4/442-arm64-dts-orangepi-one-plus-enable-PWM.patch b/target/linux/sunxi/patches-5.4/442-arm64-dts-orangepi-one-plus-enable-PWM.patch deleted file mode 100644 index 8ebbe3fad8..0000000000 --- a/target/linux/sunxi/patches-5.4/442-arm64-dts-orangepi-one-plus-enable-PWM.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -@@ -10,3 +10,7 @@ - model = "OrangePi One Plus"; - compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; - }; -+ -+&pwm { -+ status = "okay"; -+}; diff --git a/target/linux/sunxi/patches-5.4/443-board-h6-orangepioneplus-fix-missing-ethernet.patch b/target/linux/sunxi/patches-5.4/443-board-h6-orangepioneplus-fix-missing-ethernet.patch deleted file mode 100644 index 88c466d9b9..0000000000 --- a/target/linux/sunxi/patches-5.4/443-board-h6-orangepioneplus-fix-missing-ethernet.patch +++ /dev/null @@ -1,44 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-one-plus.dts -@@ -9,6 +9,41 @@ - / { - model = "OrangePi One Plus"; - compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6"; -+ -+ aliases { -+ serial0 = &uart0; -+ ethernet0 = &emac; -+ }; -+ -+ reg_gmac_3v3: gmac-3v3 { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-gmac-3v3"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ startup-delay-us = <100000>; -+ enable-active-high; -+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */ -+ vin-supply = <®_aldo2>; -+ }; -+}; -+ -+ -+&emac { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&ext_rgmii_pins>; -+ phy-mode = "rgmii"; -+ phy-handle = <&ext_rgmii_phy>; -+ phy-supply = <®_gmac_3v3>; -+ allwinner,rx-delay-ps = <200>; -+ allwinner,tx-delay-ps = <200>; -+ status = "okay"; -+}; -+ -+&mdio { -+ ext_rgmii_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c22"; -+ reg = <1>; -+ }; - }; - - &pwm { diff --git a/target/linux/sunxi/patches-5.4/450-arm64-dts-enable-wifi-on-pine64-boards.patch b/target/linux/sunxi/patches-5.4/450-arm64-dts-enable-wifi-on-pine64-boards.patch deleted file mode 100644 index 8117338029..0000000000 --- a/target/linux/sunxi/patches-5.4/450-arm64-dts-enable-wifi-on-pine64-boards.patch +++ /dev/null @@ -1,72 +0,0 @@ ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts -@@ -78,6 +78,11 @@ - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -+ }; - }; - - &ac_power_supply { -@@ -138,6 +143,21 @@ - reg = <1>; - }; - }; -+ -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ vmmc-supply = <®_dldo4>; -+ vqmmc-supply = <®_eldo1>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8723cs: wifi@1 { -+ reg = <1>; -+ }; -+}; - - &mmc2 { - pinctrl-names = "default"; ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts -@@ -73,6 +73,11 @@ - }; - }; - }; -+ -+ wifi_pwrseq: wifi_pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */ -+ }; - }; - - &codec { -@@ -146,6 +151,21 @@ - status = "okay"; - }; - -+&mmc1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&mmc1_pins>; -+ vmmc-supply = <®_dldo4>; -+ vqmmc-supply = <®_eldo1>; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ bus-width = <4>; -+ non-removable; -+ status = "okay"; -+ -+ rtl8723cs: wifi@1 { -+ reg = <1>; -+ }; -+}; -+ - &ohci0 { - status = "okay"; - }; |