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-rw-r--r--target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch37
1 files changed, 37 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch b/target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch
new file mode 100644
index 0000000000..60e653dcba
--- /dev/null
+++ b/target/linux/sunxi/patches-5.4/441-arm64-dts-add-PWM-node.patch
@@ -0,0 +1,37 @@
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+
+Allwinner H6 PWM is similar to that in A20 except that it has additional
+bus clock and reset line.
+
+Note that first PWM channel is connected to output pin and second
+channel is used internally, as a clock source to AC200 co-packaged chip.
+This means that any combination of these two channels can be used and
+thus it doesn't make sense to add pinctrl nodes at this point.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Clément Péron <peron.clem@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 29824081b43b..6d4bde488f15 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -245,6 +245,16 @@
+ status = "disabled";
+ };
+
++ pwm: pwm@300a000 {
++ compatible = "allwinner,sun50i-h6-pwm";
++ reg = <0x0300a000 0x400>;
++ clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
++ clock-names = "mod", "bus";
++ resets = <&ccu RST_BUS_PWM>;
++ #pwm-cells = <3>;
++ status = "disabled";
++ };
++
+ pio: pinctrl@300b000 {
+ compatible = "allwinner,sun50i-h6-pinctrl";
+ reg = <0x0300b000 0x400>;