diff options
Diffstat (limited to 'target/linux/sunxi/patches-4.9')
14 files changed, 640 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-4.9/0013-arm64-dts-allwinner-add-USB1-related-nodes-of-Allwin.patch b/target/linux/sunxi/patches-4.9/0013-arm64-dts-allwinner-add-USB1-related-nodes-of-Allwin.patch new file mode 100644 index 0000000000..f96570c858 --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0013-arm64-dts-allwinner-add-USB1-related-nodes-of-Allwin.patch @@ -0,0 +1,84 @@ +From a004ee350177ece3c059831ea49293d62aea7ca6 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.xyz> +Date: Tue, 22 Nov 2016 23:58:29 +0800 +Subject: arm64: dts: allwinner: add USB1-related nodes of Allwinner A64 + +Allwinner A64 have two HCI USB controllers, a OTG controller and a USB +PHY device which have two ports. One of the port is wired to both a HCI +USB controller and the OTG controller, which is currently not supported. +The another one is only wired to a HCI controller, and the device node of +OHCI/EHCI controller of the port can be added now. + +Also the A64 USB PHY device node is also added for the HCI controllers to +work. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 46 +++++++++++++++++++++++++++ + 1 file changed, 46 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -42,8 +42,10 @@ + * OTHER DEALINGS IN THE SOFTWARE. + */ + ++#include <dt-bindings/clock/sun50i-a64-ccu.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/sun4i-a10.h> ++#include <dt-bindings/reset/sun50i-a64-ccu.h> + + / { + interrupt-parent = <&gic>; +@@ -120,6 +122,50 @@ + #size-cells = <1>; + ranges; + ++ usbphy: phy@01c19400 { ++ compatible = "allwinner,sun50i-a64-usb-phy"; ++ reg = <0x01c19400 0x14>, ++ <0x01c1b800 0x4>; ++ reg-names = "phy_ctrl", ++ "pmu1"; ++ clocks = <&ccu CLK_USB_PHY0>, ++ <&ccu CLK_USB_PHY1>; ++ clock-names = "usb0_phy", ++ "usb1_phy"; ++ resets = <&ccu RST_USB_PHY0>, ++ <&ccu RST_USB_PHY1>; ++ reset-names = "usb0_reset", ++ "usb1_reset"; ++ status = "disabled"; ++ #phy-cells = <1>; ++ }; ++ ++ ehci1: usb@01c1b000 { ++ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; ++ reg = <0x01c1b000 0x100>; ++ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&ccu CLK_BUS_OHCI1>, ++ <&ccu CLK_BUS_EHCI1>, ++ <&ccu CLK_USB_OHCI1>; ++ resets = <&ccu RST_BUS_OHCI1>, ++ <&ccu RST_BUS_EHCI1>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ ++ ohci1: usb@01c1b400 { ++ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; ++ reg = <0x01c1b400 0x100>; ++ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&ccu CLK_BUS_OHCI1>, ++ <&ccu CLK_USB_OHCI1>; ++ resets = <&ccu RST_BUS_OHCI1>; ++ phys = <&usbphy 1>; ++ phy-names = "usb"; ++ status = "disabled"; ++ }; ++ + ccu: clock@01c20000 { + compatible = "allwinner,sun50i-a64-ccu"; + reg = <0x01c20000 0x400>; diff --git a/target/linux/sunxi/patches-4.9/0014-arm64-dts-allwinner-sort-the-nodes-in-sun50i-a64-pin.patch b/target/linux/sunxi/patches-4.9/0014-arm64-dts-allwinner-sort-the-nodes-in-sun50i-a64-pin.patch new file mode 100644 index 0000000000..4c7d6dafe2 --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0014-arm64-dts-allwinner-sort-the-nodes-in-sun50i-a64-pin.patch @@ -0,0 +1,40 @@ +From ac93c09cdbaf1229c21f67a5db1c3c6df7d503e5 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.xyz> +Date: Tue, 22 Nov 2016 23:58:30 +0800 +Subject: arm64: dts: allwinner: sort the nodes in sun50i-a64-pine64.dts + +In this dts file, uart0 node is put before i2c1. + +Move the uart0 node to the end to satisfy alphebetical order. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -57,12 +57,6 @@ + }; + }; + +-&uart0 { +- pinctrl-names = "default"; +- pinctrl-0 = <&uart0_pins_a>; +- status = "okay"; +-}; +- + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +@@ -72,3 +66,9 @@ + &i2c1_pins { + bias-pull-up; + }; ++ ++&uart0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart0_pins_a>; ++ status = "okay"; ++}; diff --git a/target/linux/sunxi/patches-4.9/0015-arm64-dts-allwinner-enable-EHCI1-OHCI1-and-USB-PHY-n.patch b/target/linux/sunxi/patches-4.9/0015-arm64-dts-allwinner-enable-EHCI1-OHCI1-and-USB-PHY-n.patch new file mode 100644 index 0000000000..451ec595c9 --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0015-arm64-dts-allwinner-enable-EHCI1-OHCI1-and-USB-PHY-n.patch @@ -0,0 +1,47 @@ +From d49f9dbc8f0c4521fa56477d051a3bd1158f2595 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.xyz> +Date: Tue, 22 Nov 2016 23:58:31 +0800 +Subject: arm64: dts: allwinner: enable EHCI1, OHCI1 and USB PHY nodes in + Pine64 + +Pine64 have two USB Type-A ports, which are wired to the two ports of +A64 USB PHY, and the lower port is the EHCI/OHCI1 port. + +Enable the necessary nodes to enable the lower USB port to work. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -57,6 +57,10 @@ + }; + }; + ++&ehci1 { ++ status = "okay"; ++}; ++ + &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; +@@ -67,8 +71,16 @@ + bias-pull-up; + }; + ++&ohci1 { ++ status = "okay"; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; ++ ++&usbphy { ++ status = "okay"; ++}; diff --git a/target/linux/sunxi/patches-4.9/0016-arm64-dts-add-MUSB-node-to-Allwinner-A64-dtsi.patch b/target/linux/sunxi/patches-4.9/0016-arm64-dts-add-MUSB-node-to-Allwinner-A64-dtsi.patch new file mode 100644 index 0000000000..804d00521b --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0016-arm64-dts-add-MUSB-node-to-Allwinner-A64-dtsi.patch @@ -0,0 +1,42 @@ +From 972a3ecdf27f3ebdd1ce0dccd1b548ef3c04b8ed Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.xyz> +Date: Wed, 23 Nov 2016 00:59:01 +0800 +Subject: arm64: dts: add MUSB node to Allwinner A64 dtsi + +Allwinner A64 SoC has a MUSB controller like the one in A33, so add +a node for it, just use the compatible of A33 MUSB. + +Host mode is tested to work properly on Pine64 and will be added into +the device tree of Pine64 in next patch. + +Peripheral mode is also tested on Pine64, by changing dr_mode property +of usb_otg node and use a non-standard USB Type-A to Type-A cable. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -122,6 +122,19 @@ + #size-cells = <1>; + ranges; + ++ usb_otg: usb@01c19000 { ++ compatible = "allwinner,sun8i-a33-musb"; ++ reg = <0x01c19000 0x0400>; ++ clocks = <&ccu CLK_BUS_OTG>; ++ resets = <&ccu RST_BUS_OTG>; ++ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "mc"; ++ phys = <&usbphy 0>; ++ phy-names = "usb"; ++ extcon = <&usbphy 0>; ++ status = "disabled"; ++ }; ++ + usbphy: phy@01c19400 { + compatible = "allwinner,sun50i-a64-usb-phy"; + reg = <0x01c19400 0x14>, diff --git a/target/linux/sunxi/patches-4.9/0017-arm64-dts-enable-the-MUSB-controller-of-Pine64-in-ho.patch b/target/linux/sunxi/patches-4.9/0017-arm64-dts-enable-the-MUSB-controller-of-Pine64-in-ho.patch new file mode 100644 index 0000000000..3992ab6510 --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0017-arm64-dts-enable-the-MUSB-controller-of-Pine64-in-ho.patch @@ -0,0 +1,32 @@ +From f57e8384c5d2417fd8707c577d8e622fc1570b6c Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.xyz> +Date: Wed, 23 Nov 2016 00:59:02 +0800 +Subject: arm64: dts: enable the MUSB controller of Pine64 in host-only mode + +A64 has a MUSB controller wired to the USB PHY 0, which is connected +to the upper USB Type-A port of Pine64. + +As the port is a Type-A female port, enable it in host-only mode in the +device tree, which makes devices with USB Type-A male port can work on +this port (which is originally designed by Pine64 team). + +Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -81,6 +81,11 @@ + status = "okay"; + }; + ++&usb_otg { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &usbphy { + status = "okay"; + }; diff --git a/target/linux/sunxi/patches-4.9/0018-arm64-dts-allwinner-Remove-no-longer-used-pinctrl-su.patch b/target/linux/sunxi/patches-4.9/0018-arm64-dts-allwinner-Remove-no-longer-used-pinctrl-su.patch new file mode 100644 index 0000000000..d2d54e937f --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0018-arm64-dts-allwinner-Remove-no-longer-used-pinctrl-su.patch @@ -0,0 +1,31 @@ +From 4f9758302ccaf753cd4ba6a5eb740392a4d24773 Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai <wens@csie.org> +Date: Tue, 24 Jan 2017 10:32:29 +0800 +Subject: arm64: dts: allwinner: Remove no longer used pinctrl/sun4i-a10.h + header + +All dts files for the sunxi platform have been switched to the generic +pinconf bindings. As a result, the sunxi specific pinctrl macros are +no longer used. + +Remove the #include entry with the following command: + + sed -i -e '/pinctrl\/sun4i-a10.h/D' \ + arch/arm64/boot/dts/allwinner/*.dts? + +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 - + 1 file changed, 1 deletion(-) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -44,7 +44,6 @@ + + #include <dt-bindings/clock/sun50i-a64-ccu.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> +-#include <dt-bindings/pinctrl/sun4i-a10.h> + #include <dt-bindings/reset/sun50i-a64-ccu.h> + + / { diff --git a/target/linux/sunxi/patches-4.9/0019-arm64-allwinner-a64-Add-MMC-nodes.patch b/target/linux/sunxi/patches-4.9/0019-arm64-allwinner-a64-Add-MMC-nodes.patch new file mode 100644 index 0000000000..1f91e9bead --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0019-arm64-allwinner-a64-Add-MMC-nodes.patch @@ -0,0 +1,69 @@ +From f3dff3478a8a7b09f9a92023955a151584658893 Mon Sep 17 00:00:00 2001 +From: Andre Przywara <andre.przywara@arm.com> +Date: Thu, 6 Oct 2016 02:25:22 +0100 +Subject: arm64: allwinner: a64: Add MMC nodes + +The A64 has 3 MMC controllers, one of them being especially targeted to +eMMC. Among other things, it has a data strobe signal and a 8 bits data +width. + +The two other are more usual controllers that will have a 4 bits width at +most and no data strobe signal, which limits it to more usual SD or MMC +peripherals. + +Signed-off-by: Andre Przywara <andre.przywara@arm.com> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> +Acked-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 39 +++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -121,6 +121,45 @@ + #size-cells = <1>; + ranges; + ++ mmc0: mmc@1c0f000 { ++ compatible = "allwinner,sun50i-a64-mmc"; ++ reg = <0x01c0f000 0x1000>; ++ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; ++ clock-names = "ahb", "mmc"; ++ resets = <&ccu RST_BUS_MMC0>; ++ reset-names = "ahb"; ++ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mmc1: mmc@1c10000 { ++ compatible = "allwinner,sun50i-a64-mmc"; ++ reg = <0x01c10000 0x1000>; ++ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; ++ clock-names = "ahb", "mmc"; ++ resets = <&ccu RST_BUS_MMC1>; ++ reset-names = "ahb"; ++ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mmc2: mmc@1c11000 { ++ compatible = "allwinner,sun50i-a64-emmc"; ++ reg = <0x01c11000 0x1000>; ++ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; ++ clock-names = "ahb", "mmc"; ++ resets = <&ccu RST_BUS_MMC2>; ++ reset-names = "ahb"; ++ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; ++ status = "disabled"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ + usb_otg: usb@01c19000 { + compatible = "allwinner,sun8i-a33-musb"; + reg = <0x01c19000 0x0400>; diff --git a/target/linux/sunxi/patches-4.9/0020-arm64-allwinner-a64-Add-MMC-pinctrl-nodes.patch b/target/linux/sunxi/patches-4.9/0020-arm64-allwinner-a64-Add-MMC-pinctrl-nodes.patch new file mode 100644 index 0000000000..f5af0f819a --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0020-arm64-allwinner-a64-Add-MMC-pinctrl-nodes.patch @@ -0,0 +1,50 @@ +From a3e8f4926248b3c12933aacec4432e9b6de004bb Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Mon, 9 Jan 2017 16:39:15 +0100 +Subject: arm64: allwinner: a64: Add MMC pinctrl nodes + +The A64 only has a single set of pins for each MMC controller. Since we +already have boards that require all of them, let's add them to the DTSI. + +Reviewed-by: Andre Przywara <andre.przywara@arm.com> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Tested-by: Florian Vaussard <florian.vaussard@heig-vd.ch> +Acked-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -243,6 +243,31 @@ + function = "i2c1"; + }; + ++ mmc0_pins: mmc0-pins { ++ pins = "PF0", "PF1", "PF2", "PF3", ++ "PF4", "PF5"; ++ function = "mmc0"; ++ drive-strength = <30>; ++ bias-pull-up; ++ }; ++ ++ mmc1_pins: mmc1-pins { ++ pins = "PG0", "PG1", "PG2", "PG3", ++ "PG4", "PG5"; ++ function = "mmc1"; ++ drive-strength = <30>; ++ bias-pull-up; ++ }; ++ ++ mmc2_pins: mmc2-pins { ++ pins = "PC1", "PC5", "PC6", "PC8", "PC9", ++ "PC10","PC11", "PC12", "PC13", ++ "PC14", "PC15", "PC16"; ++ function = "mmc2"; ++ drive-strength = <30>; ++ bias-pull-up; ++ }; ++ + uart0_pins_a: uart0@0 { + pins = "PB8", "PB9"; + function = "uart0"; diff --git a/target/linux/sunxi/patches-4.9/0022-arm64-allwinner-pine64-add-MMC-support.patch b/target/linux/sunxi/patches-4.9/0022-arm64-allwinner-pine64-add-MMC-support.patch new file mode 100644 index 0000000000..c60e5104cf --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0022-arm64-allwinner-pine64-add-MMC-support.patch @@ -0,0 +1,62 @@ +From ebe3ae29c6314217edf40d9ee23c36d610ff0fb8 Mon Sep 17 00:00:00 2001 +From: Andre Przywara <andre.przywara@arm.com> +Date: Tue, 10 Jan 2017 01:22:31 +0000 +Subject: arm64: allwinner: pine64: add MMC support + +All Pine64 boards connect an micro-SD card slot to the first MMC +controller. +Enable the respective DT node and specify the (always-on) regulator +and card-detect pin. +As a micro-SD slot does not feature a write-protect switch, we disable +this feature. + +Signed-off-by: Andre Przywara <andre.przywara@arm.com> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Acked-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts +@@ -44,6 +44,8 @@ + + #include "sun50i-a64.dtsi" + ++#include <dt-bindings/gpio/gpio.h> ++ + / { + model = "Pine64"; + compatible = "pine64,pine64", "allwinner,sun50i-a64"; +@@ -55,6 +57,13 @@ + chosen { + stdout-path = "serial0:115200n8"; + }; ++ ++ reg_vcc3v3: vcc3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ }; + }; + + &ehci1 { +@@ -71,6 +80,17 @@ + bias-pull-up; + }; + ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins>; ++ vmmc-supply = <®_vcc3v3>; ++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; ++ cd-inverted; ++ disable-wp; ++ bus-width = <4>; ++ status = "okay"; ++}; ++ + &ohci1 { + status = "okay"; + }; diff --git a/target/linux/sunxi/patches-4.9/0023-arm64-allwinner-a64-add-UART1-pin-nodes.patch b/target/linux/sunxi/patches-4.9/0023-arm64-allwinner-a64-add-UART1-pin-nodes.patch new file mode 100644 index 0000000000..998d51435f --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0023-arm64-allwinner-a64-add-UART1-pin-nodes.patch @@ -0,0 +1,35 @@ +From e7ba733d32cc9487b62b07219ad911c77764a681 Mon Sep 17 00:00:00 2001 +From: Andre Przywara <andre.przywara@arm.com> +Date: Tue, 10 Jan 2017 01:22:32 +0000 +Subject: arm64: allwinner: a64: add UART1 pin nodes + +On many boards UART1 connects to a Bluetooth chip, so add the pinctrl +nodes for the only pins providing access to that UART. That includes +those pins for hardware flow control (RTS/CTS). + +Signed-off-by: Andre Przywara <andre.przywara@arm.com> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Acked-by: Chen-Yu Tsai <wens@csie.org> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -272,6 +272,16 @@ + pins = "PB8", "PB9"; + function = "uart0"; + }; ++ ++ uart1_pins: uart1_pins { ++ pins = "PG6", "PG7"; ++ function = "uart1"; ++ }; ++ ++ uart1_rts_cts_pins: uart1_rts_cts_pins { ++ pins = "PG8", "PG9"; ++ function = "uart1"; ++ }; + }; + + uart0: serial@1c28000 { diff --git a/target/linux/sunxi/patches-4.9/0024-arm64-allwinner-a64-add-r_ccu-node.patch b/target/linux/sunxi/patches-4.9/0024-arm64-allwinner-a64-add-r_ccu-node.patch new file mode 100644 index 0000000000..19a3589708 --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0024-arm64-allwinner-a64-add-r_ccu-node.patch @@ -0,0 +1,52 @@ +From 791a9e001d3ba3b552888b0bf3c592a50b71f57e Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.xyz> +Date: Tue, 4 Apr 2017 17:50:58 +0800 +Subject: arm64: allwinner: a64: add r_ccu node + +A64 SoC have a CCU (r_ccu) in PRCM block. + +Add the device node for it. + +The mux 3 of R_CCU is an internal oscillator, which is 16MHz according +to the user manual, and has only 30% accuracy based on our experience +on older SoCs. The real mesaured value of it on two Pine64 boards is +around 11MHz, which is around 70% of 16MHz. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -98,6 +98,14 @@ + clock-output-names = "osc32k"; + }; + ++ iosc: internal-osc-clk { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <16000000>; ++ clock-accuracy = <300000000>; ++ clock-output-names = "iosc"; ++ }; ++ + psci { + compatible = "arm,psci-0.2"; + method = "smc"; +@@ -389,5 +397,14 @@ + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + }; ++ ++ r_ccu: clock@1f01400 { ++ compatible = "allwinner,sun50i-a64-r-ccu"; ++ reg = <0x01f01400 0x100>; ++ clocks = <&osc24M>, <&osc32k>, <&iosc>; ++ clock-names = "hosc", "losc", "iosc"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; + }; + }; diff --git a/target/linux/sunxi/patches-4.9/0025-arm64-allwinner-a64-add-R_PIO-pinctrl-node.patch b/target/linux/sunxi/patches-4.9/0025-arm64-allwinner-a64-add-R_PIO-pinctrl-node.patch new file mode 100644 index 0000000000..ff541ce63e --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0025-arm64-allwinner-a64-add-R_PIO-pinctrl-node.patch @@ -0,0 +1,35 @@ +From ec4279053a6434f685246e022be95d2a62f8c608 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.xyz> +Date: Tue, 4 Apr 2017 17:51:00 +0800 +Subject: arm64: allwinner: a64: add R_PIO pinctrl node + +Allwinner A64 have a dedicated pin controller to manage the PL pin bank. +As the driver and the required clock support are added, add the device +node for it. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -406,5 +406,17 @@ + #clock-cells = <1>; + #reset-cells = <1>; + }; ++ ++ r_pio: pinctrl@01f02c00 { ++ compatible = "allwinner,sun50i-a64-r-pinctrl"; ++ reg = <0x01f02c00 0x400>; ++ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&r_ccu 3>, <&osc24M>, <&osc32k>; ++ clock-names = "apb", "hosc", "losc"; ++ gpio-controller; ++ #gpio-cells = <3>; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ }; + }; + }; diff --git a/target/linux/sunxi/patches-4.9/0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch b/target/linux/sunxi/patches-4.9/0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch new file mode 100644 index 0000000000..0d7803775e --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0026-arm64-allwinner-a64-add-pmu0-regs-for-USB-PHY.patch @@ -0,0 +1,29 @@ +From 0d98479738b950e30bb4f782d60099d44076ad67 Mon Sep 17 00:00:00 2001 +From: Icenowy Zheng <icenowy@aosc.io> +Date: Wed, 5 Apr 2017 22:30:34 +0800 +Subject: arm64: allwinner: a64: add pmu0 regs for USB PHY + +The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI +controller pair that can be connected to the PHY0. + +Add the MMIO region for PHY node. + +Signed-off-by: Icenowy Zheng <icenowy@aosc.io> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -184,8 +184,10 @@ + usbphy: phy@01c19400 { + compatible = "allwinner,sun50i-a64-usb-phy"; + reg = <0x01c19400 0x14>, ++ <0x01c1a800 0x4>, + <0x01c1b800 0x4>; + reg-names = "phy_ctrl", ++ "pmu0", + "pmu1"; + clocks = <&ccu CLK_USB_PHY0>, + <&ccu CLK_USB_PHY1>; diff --git a/target/linux/sunxi/patches-4.9/0027-arm64-allwinner-a64-Add-PLL_PERIPH0-clock-to-the-R_C.patch b/target/linux/sunxi/patches-4.9/0027-arm64-allwinner-a64-Add-PLL_PERIPH0-clock-to-the-R_C.patch new file mode 100644 index 0000000000..319dba6591 --- /dev/null +++ b/target/linux/sunxi/patches-4.9/0027-arm64-allwinner-a64-Add-PLL_PERIPH0-clock-to-the-R_C.patch @@ -0,0 +1,32 @@ +From f74994a94063bc85ac1d6ad677ed06b5279c101f Mon Sep 17 00:00:00 2001 +From: Chen-Yu Tsai <wens@csie.org> +Date: Wed, 31 May 2017 15:58:24 +0800 +Subject: arm64: allwinner: a64: Add PLL_PERIPH0 clock to the R_CCU + +The AR100 clock within the R_CCU (PRCM) has the PLL_PERIPH0 as one of +its parents. + +This adds the reference in the device tree describing this relationship. +This patch uses a raw number for the clock index to ease merging by +avoiding cross tree dependencies. + +Signed-off-by: Chen-Yu Tsai <wens@csie.org> +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -403,8 +403,9 @@ + r_ccu: clock@1f01400 { + compatible = "allwinner,sun50i-a64-r-ccu"; + reg = <0x01f01400 0x100>; +- clocks = <&osc24M>, <&osc32k>, <&iosc>; +- clock-names = "hosc", "losc", "iosc"; ++ clocks = <&osc24M>, <&osc32k>, <&iosc>, ++ <&ccu 11>; ++ clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; |