1 files changed, 0 insertions, 47 deletions
diff --git a/target/linux/sunxi/patches-4.4/107-clk-sunxi-add-h3-usbphy-clocks.patch b/target/linux/sunxi/patches-4.4/107-clk-sunxi-add-h3-usbphy-clocks.patch
deleted file mode 100644
index c845d512e4..0000000000
--- a/target/linux/sunxi/patches-4.4/107-clk-sunxi-add-h3-usbphy-clocks.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 7bec0200ac214b5cba44e2c2c4385815be4b9f00 Mon Sep 17 00:00:00 2001
-From: Reinder de Haan <patchesrdh@mveas.com>
-Date: Sun, 15 Nov 2015 20:46:13 +0100
-Subject: [PATCH] clk: sunxi: Add support for the H3 usb phy clocks
-
-The H3 has a usb-phy clk register which is similar to that of earlier
-SoCs, but with support for a larger number of phys. So we can simply add
-a new set of clk-data and a new compatible and be done with it.
-
-Acked-by: Chen-Yu Tsai <wens@csie.org>
-Acked-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
-Signed-off-by: Hans de Goede <hdegoede@redhat.com>
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- Documentation/devicetree/bindings/clock/sunxi.txt |  1 +
- drivers/clk/sunxi/clk-usb.c                       | 12 ++++++++++++
- 2 files changed, 13 insertions(+)
-
---- a/Documentation/devicetree/bindings/clock/sunxi.txt
-+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
-@@ -70,6 +70,7 @@ Required properties:
- 	"allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13
- 	"allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31
- 	"allwinner,sun8i-a23-usb-clk" - for usb gates + resets on A23
-+	"allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
- 	"allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
- 	"allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
- 
---- a/drivers/clk/sunxi/clk-usb.c
-+++ b/drivers/clk/sunxi/clk-usb.c
-@@ -243,3 +243,15 @@ static void __init sun9i_a80_usb_phy_set
- 	sunxi_usb_clk_setup(node, &sun9i_a80_usb_phy_data, &a80_usb_phy_lock);
- }
- CLK_OF_DECLARE(sun9i_a80_usb_phy, "allwinner,sun9i-a80-usb-phy-clk", sun9i_a80_usb_phy_setup);
-+
-+static const struct usb_clk_data sun8i_h3_usb_clk_data __initconst = {
-+	.clk_mask =  BIT(19) | BIT(18) | BIT(17) | BIT(16) |
-+		     BIT(11) | BIT(10) | BIT(9) | BIT(8),
-+	.reset_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
-+};
-+
-+static void __init sun8i_h3_usb_setup(struct device_node *node)
-+{
-+	sunxi_usb_clk_setup(node, &sun8i_h3_usb_clk_data, &sun4i_a10_usb_lock);
-+}
-+CLK_OF_DECLARE(sun8i_h3_usb, "allwinner,sun8i-h3-usb-clk", sun8i_h3_usb_setup);