diff options
Diffstat (limited to 'target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch')
| -rw-r--r-- | target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch | 78 |
1 files changed, 0 insertions, 78 deletions
diff --git a/target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch b/target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch deleted file mode 100644 index 1e40f99d04..0000000000 --- a/target/linux/sunxi/patches-4.14/080-arm64-allwinner-a64-add-SPI-nodes.patch +++ /dev/null @@ -1,78 +0,0 @@ -From b518bb159032aac33503fd4cf98706dc84cc1266 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Stefan=20Br=C3=BCns?= <stefan.bruens@rwth-aachen.de> -Date: Thu, 31 Aug 2017 01:06:37 +0200 -Subject: [PATCH] arm64: allwinner: a64: add SPI nodes -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The A64 SPI controllers are register compatible to the h3/h5 SPI -controllers. - -The A64 has two SPI controllers, each with a single chip select. -The handles for the DMA channels (23/24 for SPI0/SPI1) are omitted, -as the A64 DMA support is currently missing. - -Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> -Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> ---- - arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 41 +++++++++++++++++++ - 1 file changed, 41 insertions(+) - ---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi -@@ -326,6 +326,16 @@ - drive-strength = <40>; - }; - -+ spi0_pins: spi0 { -+ pins = "PC0", "PC1", "PC2", "PC3"; -+ function = "spi0"; -+ }; -+ -+ spi1_pins: spi1 { -+ pins = "PD0", "PD1", "PD2", "PD3"; -+ function = "spi1"; -+ }; -+ - uart0_pins_a: uart0@0 { - pins = "PB8", "PB9"; - function = "uart0"; -@@ -471,6 +481,37 @@ - }; - }; - -+ -+ spi0: spi@01c68000 { -+ compatible = "allwinner,sun8i-h3-spi"; -+ reg = <0x01c68000 0x1000>; -+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; -+ clock-names = "ahb", "mod"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; -+ resets = <&ccu RST_BUS_SPI0>; -+ status = "disabled"; -+ num-cs = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ spi1: spi@01c69000 { -+ compatible = "allwinner,sun8i-h3-spi"; -+ reg = <0x01c69000 0x1000>; -+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; -+ clock-names = "ahb", "mod"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi1_pins>; -+ resets = <&ccu RST_BUS_SPI1>; -+ status = "disabled"; -+ num-cs = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ - gic: interrupt-controller@1c81000 { - compatible = "arm,gic-400"; - reg = <0x01c81000 0x1000>, |