diff options
Diffstat (limited to 'target/linux/sunxi/patches-3.14/183-clk-sunxi-add-usb-clockreg-defs.patch')
| -rw-r--r-- | target/linux/sunxi/patches-3.14/183-clk-sunxi-add-usb-clockreg-defs.patch | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.14/183-clk-sunxi-add-usb-clockreg-defs.patch b/target/linux/sunxi/patches-3.14/183-clk-sunxi-add-usb-clockreg-defs.patch new file mode 100644 index 0000000000..07e8879896 --- /dev/null +++ b/target/linux/sunxi/patches-3.14/183-clk-sunxi-add-usb-clockreg-defs.patch @@ -0,0 +1,76 @@ +From c61dfeb17581d32360a817ba40636aaed85caade Mon Sep 17 00:00:00 2001 +From: Roman Byshko <rbyshko@gmail.com> +Date: Fri, 7 Feb 2014 16:21:50 +0100 +Subject: [PATCH] clk: sunxi: Add USB clock register defintions +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add register definitions for the usb-clk register found on sun4i, sun5i and +sun7i SoCs. + +Signed-off-by: Roman Byshko <rbyshko@gmail.com> +Signed-off-by: Hans de Goede <hdegoede@redhat.com> +Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> +Signed-off-by: Emilio López <emilio@elopez.com.ar> +--- + Documentation/devicetree/bindings/clock/sunxi.txt | 5 +++++ + drivers/clk/sunxi/clk-sunxi.c | 12 ++++++++++++ + 2 files changed, 17 insertions(+) + +diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt +index 0cf679b..ca2b692 100644 +--- a/Documentation/devicetree/bindings/clock/sunxi.txt ++++ b/Documentation/devicetree/bindings/clock/sunxi.txt +@@ -37,6 +37,8 @@ Required properties: + "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31 + "allwinner,sun4i-mod0-clk" - for the module 0 family of clocks + "allwinner,sun7i-a20-out-clk" - for the external output clocks ++ "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 ++ "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 + + Required properties for all clocks: + - reg : shall be the control register address for the clock. +@@ -50,6 +52,9 @@ Required properties for all clocks: + If the clock module only has one output, the name shall be the + module name. + ++And "allwinner,*-usb-clk" clocks also require: ++- reset-cells : shall be set to 1 ++ + Clock consumers should specify the desired clocks they use with a + "clocks" phandle cell. Consumers that are using a gated clock should + provide an additional ID in their clock property. This ID is the +diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c +index 23beb6e..a779c31 100644 +--- a/drivers/clk/sunxi/clk-sunxi.c ++++ b/drivers/clk/sunxi/clk-sunxi.c +@@ -816,6 +816,16 @@ static const struct gates_data sun7i_a20_apb1_gates_data __initconst = { + .mask = { 0xff80ff }, + }; + ++static const struct gates_data sun4i_a10_usb_gates_data __initconst = { ++ .mask = {0x1C0}, ++ .reset_mask = 0x07, ++}; ++ ++static const struct gates_data sun5i_a13_usb_gates_data __initconst = { ++ .mask = {0x140}, ++ .reset_mask = 0x03, ++}; ++ + static void __init sunxi_gates_clk_setup(struct device_node *node, + struct gates_data *data) + { +@@ -1107,6 +1117,8 @@ static const struct of_device_id clk_gates_match[] __initconst = { + {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,}, + {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,}, + {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,}, ++ {.compatible = "allwinner,sun4i-a10-usb-clk", .data = &sun4i_a10_usb_gates_data,}, ++ {.compatible = "allwinner,sun5i-a13-usb-clk", .data = &sun5i_a13_usb_gates_data,}, + {} + }; + +-- +2.0.3 + |