1 files changed, 0 insertions, 77 deletions
diff --git a/target/linux/sunxi/patches-3.14/110-dt-sun6i-add-pll-and-spi-modclocks.patch b/target/linux/sunxi/patches-3.14/110-dt-sun6i-add-pll-and-spi-modclocks.patch
deleted file mode 100644
index 7d8c2cfbd2..0000000000
--- a/target/linux/sunxi/patches-3.14/110-dt-sun6i-add-pll-and-spi-modclocks.patch
+++ /dev/null
@@ -1,77 +0,0 @@
-From 7f94ebf35b017f1664e957857a7f36752e2577cd Mon Sep 17 00:00:00 2001
-From: Maxime Ripard <maxime.ripard@free-electrons.com>
-Date: Wed, 5 Feb 2014 14:05:04 +0100
-Subject: [PATCH] ARM: sun6i: dt: Add PLL6 and SPI module clocks
-
-The module clocks in the A31 are still compatible with the A10 one. Add the SPI
-module clocks and the PLL6 in the device tree to allow their use by the SPI
-controllers.
-
-Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
----
- arch/arm/boot/dts/sun6i-a31.dtsi | 46 ++++++++++++++++++++++++++++++++--------
- 1 file changed, 37 insertions(+), 9 deletions(-)
-
---- a/arch/arm/boot/dts/sun6i-a31.dtsi
-+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
-@@ -83,16 +83,12 @@
- 			clocks = <&osc24M>;
- 		};
- 
--		/*
--		 * This is a dummy clock, to be used as placeholder on
--		 * other mux clocks when a specific parent clock is not
--		 * yet implemented. It should be dropped when the driver
--		 * is complete.
--		 */
--		pll6: pll6 {
-+		pll6: clk@01c20028 {
- 			#clock-cells = <0>;
--			compatible = "fixed-clock";
--			clock-frequency = <0>;
-+			compatible = "allwinner,sun6i-a31-pll6-clk";
-+			reg = <0x01c20028 0x4>;
-+			clocks = <&osc24M>;
-+			clock-output-names = "pll6";
- 		};
- 
- 		cpu: cpu@01c20050 {
-@@ -192,6 +188,38 @@
- 					"apb2_uart1", "apb2_uart2", "apb2_uart3",
- 					"apb2_uart4", "apb2_uart5";
- 		};
-+
-+		spi0_clk: clk@01c200a0 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a0 0x4>;
-+			clocks = <&osc24M>, <&pll6>;
-+			clock-output-names = "spi0";
-+		};
-+
-+		spi1_clk: clk@01c200a4 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a4 0x4>;
-+			clocks = <&osc24M>, <&pll6>;
-+			clock-output-names = "spi1";
-+		};
-+
-+		spi2_clk: clk@01c200a8 {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200a8 0x4>;
-+			clocks = <&osc24M>, <&pll6>;
-+			clock-output-names = "spi2";
-+		};
-+
-+		spi3_clk: clk@01c200ac {
-+			#clock-cells = <0>;
-+			compatible = "allwinner,sun4i-mod0-clk";
-+			reg = <0x01c200ac 0x4>;
-+			clocks = <&osc24M>, <&pll6>;
-+			clock-output-names = "spi3";
-+		};
- 	};
- 
- 	soc@01c00000 {