diff options
Diffstat (limited to 'target/linux/sunxi/patches-3.13/170-8-clk-sunxi-implement-mmc-phasectrl.patch')
-rw-r--r-- | target/linux/sunxi/patches-3.13/170-8-clk-sunxi-implement-mmc-phasectrl.patch | 62 |
1 files changed, 0 insertions, 62 deletions
diff --git a/target/linux/sunxi/patches-3.13/170-8-clk-sunxi-implement-mmc-phasectrl.patch b/target/linux/sunxi/patches-3.13/170-8-clk-sunxi-implement-mmc-phasectrl.patch deleted file mode 100644 index f3b7f5ae91..0000000000 --- a/target/linux/sunxi/patches-3.13/170-8-clk-sunxi-implement-mmc-phasectrl.patch +++ /dev/null @@ -1,62 +0,0 @@ -From fcba369ee1af8657353bb1e37807aa492c462263 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar> -Date: Fri, 20 Sep 2013 20:29:17 -0300 -Subject: [PATCH] clk: sunxi: Implement MMC phase control -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Emilio López <emilio@elopez.com.ar> ---- - drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++ - 1 file changed, 35 insertions(+) - -diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c -index 3283179..46a38b4 100644 ---- a/drivers/clk/sunxi/clk-sunxi.c -+++ b/drivers/clk/sunxi/clk-sunxi.c -@@ -500,6 +500,41 @@ static void __init sun7i_a20_gmac_clk_setup(struct device_node *node) - - - /** -+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control -+ */ -+ -+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output) -+{ -+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) -+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw) -+ -+ struct clk_composite *composite = to_clk_composite(hw); -+ struct clk_hw *rate_hw = composite->rate_hw; -+ struct clk_factors *factors = to_clk_factors(rate_hw); -+ unsigned long flags = 0; -+ u32 reg; -+ -+ if (factors->lock) -+ spin_lock_irqsave(factors->lock, flags); -+ -+ reg = readl(factors->reg); -+ -+ /* set sample clock phase control */ -+ reg &= ~(0x7 << 20); -+ reg |= ((sample & 0x7) << 20); -+ -+ /* set output clock phase control */ -+ reg &= ~(0x7 << 8); -+ reg |= ((output & 0x7) << 8); -+ -+ writel(reg, factors->reg); -+ -+ if (factors->lock) -+ spin_unlock_irqrestore(factors->lock, flags); -+} -+ -+ -+/** - * sunxi_factors_clk_setup() - Setup function for factor clocks - */ - --- -1.8.5.5 - |