diff options
Diffstat (limited to 'target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h')
| -rw-r--r-- | target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h | 108 |
1 files changed, 93 insertions, 15 deletions
diff --git a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h index 2e420a9db4..13fb804436 100644 --- a/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h +++ b/target/linux/rtl838x/files-5.4/drivers/net/dsa/rtl838x.h @@ -54,20 +54,34 @@ #define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880) #define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980) +/* Registers of the internal Serdes of the 8390 */ +#define RTL8390_SDS0_1_XSG0 (0xA000) +#define RTL8390_SDS0_1_XSG1 (0xA100) +#define RTL839X_SDS12_13_XSG0 (0xB800) +#define RTL839X_SDS12_13_XSG1 (0xB900) +#define RTL839X_SDS12_13_PWR0 (0xb880) +#define RTL839X_SDS12_13_PWR1 (0xb980) + /* VLAN registers */ -#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) +#define RTL838X_VLAN_PROFILE (0x3A88) #define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) -#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2)) +#define RTL838X_VLAN_PORT_PB_VLAN (0x3C00) +#define RTL838X_VLAN_PORT_IGR_FLTR (0x3A7C) #define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C) -#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4) +#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A80) +#define RTL839X_VLAN_PROFILE (0x25C0) +#define RTL839X_VLAN_CTRL (0x26D4) +#define RTL839X_VLAN_PORT_PB_VLAN (0x26D8) +#define RTL839X_VLAN_PORT_IGR_FLTR (0x27B4) +#define RTL839X_VLAN_PORT_EGR_FLTR (0x27C4) /* Table 0/1 access registers */ #define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) -#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_DATA_0 (0x6918) #define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) #define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) #define RTL839X_TBL_ACCESS_CTRL_0 (0x1190) -#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_DATA_0 (0x1194) #define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80) #define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2)) @@ -75,12 +89,18 @@ #define RTL838X_MAC_LINK_STS (0xa188) #define RTL839X_MAC_LINK_STS (0x0390) #define RTL838X_MAC_LINK_SPD_STS(port) (0xa190 + (((port >> 4) << 2))) +#define RTL839X_MAC_LINK_SPD_STS(port) (0x03a0 + (((port >> 4) << 2))) #define RTL838X_MAC_LINK_DUP_STS (0xa19c) +#define RTL839X_MAC_LINK_DUP_STS (0x03b0) #define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) +#define RTL839X_MAC_TX_PAUSE_STS (0x03b8) #define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) +#define RTL839X_MAC_RX_PAUSE_STS (0x03c0) #define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) #define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) +#define RTL838X_DMA_IF_CTRL (0x9f58) + /* MAC link state bits */ #define FORCE_EN (1 << 0) #define FORCE_LINK_EN (1 << 1) @@ -105,21 +125,31 @@ #define RTL838X_TBL_ACCESS_L2_CTRL (0x6900) #define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) #define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) -#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) #define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) #define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) +#define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2))) +#define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2))) +#define RTL838X_L2_PORT_SALRN(p) (0x328c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_SALRN(p) (0x38F0 + (((p >> 4) << 2))) /* Port Mirroring */ #define RTL838X_MIR_CTRL(grp) (0x5D00 + (((grp) << 2))) #define RTL838X_MIR_DPM_CTRL(grp) (0x5D20 + (((grp) << 2))) #define RTL838X_MIR_SPM_CTRL(grp) (0x5D10 + (((grp) << 2))) +#define RTL839X_MIR_CTRL(grp) (0x2500 + (((grp) << 2))) +#define RTL839X_MIR_DPM_CTRL(grp) (0x2530 + (((grp) << 2))) +#define RTL839X_MIR_SPM_CTRL(grp) (0x2510 + (((grp) << 2))) enum phy_type { PHY_NONE = 0, PHY_RTL838X_SDS = 1, PHY_RTL8218B_INT = 2, PHY_RTL8218B_EXT = 3, - PHY_RTL8214FC = 4 + PHY_RTL8214FC = 4, + PHY_RTL839X_SDS = 5, }; struct rtl838x_port { @@ -133,20 +163,51 @@ struct rtl838x_port { struct rtl838x_vlan_info { u64 untagged_ports; u64 tagged_ports; - u32 vlan_conf; + u8 profile_id; + bool hash_mc; + bool hash_uc; + u8 fid; +}; + +enum l2_entry_type { + L2_INVALID = 0, + L2_UNICAST = 1, + L2_MULTICAST = 2, + IP4_MULTICAST = 3, + IP6_MULTICAST = 4, +}; + +struct rtl838x_l2_entry { + u8 mac[ETH_ALEN]; + u16 vid; + u16 rvid; + u8 port; + bool valid; + enum l2_entry_type type; + bool is_static; + bool is_ip_mc; + bool is_ipv6_mc; + bool block_da; + bool block_sa; + bool suspended; + bool next_hop; + int age; + u16 mc_portmask_index; }; struct rtl838x_switch_priv; struct rtl838x_reg { - void (*mask_port_reg)(u64 clear, u64 set, int reg); - void (*set_port_reg)(u64 set, int reg); - u64 (*get_port_reg)(int reg); + void (*mask_port_reg_be)(u64 clear, u64 set, int reg); + void (*set_port_reg_be)(u64 set, int reg); + u64 (*get_port_reg_be)(int reg); + void (*mask_port_reg_le)(u64 clear, u64 set, int reg); + void (*set_port_reg_le)(u64 set, int reg); + u64 (*get_port_reg_le)(int reg); int stat_port_rst; int stat_rst; int (*stat_port_std_mib)(int p); - void (*mask_port_iso_ctrl)(u64 clear, u64 set, int port); - void (*set_port_iso_ctrl)(u64 set, int port); + int (*port_iso_ctrl)(int p); int l2_ctrl_0; int l2_ctrl_1; int l2_port_aging_out; @@ -160,10 +221,26 @@ struct rtl838x_reg { int imr_port_link_sts_chg; int imr_glb; void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info); - void (*vlan_set_tagged)(u32 vlan, u64 portmask, u32 conf); + void (*vlan_set_tagged)(u32 vlan, const struct rtl838x_vlan_info *info); void (*vlan_set_untagged)(u32 vlan, u64 portmask); int (*mac_force_mode_ctrl)(int port); - int rst_glb_ctrl; + int (*mac_port_ctrl)(int port); + int (*l2_port_new_salrn)(int port); + int (*l2_port_new_sa_fwd)(int port); + int (*mir_ctrl)(int group); + int (*mir_dpm)(int group); + int (*mir_spm)(int group); + int mac_link_sts; + int mac_link_dup_sts; + int (*mac_link_spd_sts)(int port); + int mac_rx_pause_sts; + int mac_tx_pause_sts; + u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e); + u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e); + int (*vlan_profile)(int profile); + int (*vlan_port_egr_filter)(int port); + int (*vlan_port_igr_filter)(int port); + int (*vlan_port_pb)(int port); }; struct rtl838x_switch_priv { @@ -181,6 +258,7 @@ struct rtl838x_switch_priv { const struct rtl838x_reg *r; u8 cpu_port; u8 port_mask; + u32 fib_entries; }; extern struct rtl838x_soc_info soc_info; |