diff options
Diffstat (limited to 'target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx')
10 files changed, 3078 insertions, 0 deletions
diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig new file mode 100644 index 0000000000..f293832eb5 --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-only +config NET_DSA_RTL83XX + tristate "Realtek RTL838x/RTL839x switch support" + depends on RTL838X + select NET_DSA_TAG_TRAILER + ---help--- + This driver adds support for Realtek RTL83xx series switching. + diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile new file mode 100644 index 0000000000..52cc151a56 --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_NET_DSA_RTL83XX) += common.o dsa.o \ + rtl838x.o rtl839x.o storm.o debugfs.o diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c new file mode 100644 index 0000000000..1b57ddc92c --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/common.c @@ -0,0 +1,407 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/of_mdio.h> +#include <linux/of_platform.h> + +#include <asm/mach-rtl838x/mach-rtl83xx.h> +#include "rtl83xx.h" + +extern struct rtl83xx_soc_info soc_info; + +extern const struct rtl838x_reg rtl838x_reg; +extern const struct rtl838x_reg rtl839x_reg; +extern const struct dsa_switch_ops rtl83xx_switch_ops; + +DEFINE_MUTEX(smi_lock); + + +// TODO: unused +static void dump_fdb(struct rtl838x_switch_priv *priv) +{ + struct rtl838x_l2_entry e; + int i; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < priv->fib_entries; i++) { + priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e); + + if (!e.valid) /* Check for invalid entry */ + continue; + + pr_debug("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n", + e.port, &e.mac[0], e.vid, e.rvid, e.is_ip_mc, e.is_ipv6_mc); + } + + mutex_unlock(&priv->reg_mutex); +} + +// TODO: unused +static void rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port) +{ + u32 cmd, msti = 0; + u32 port_state[4]; + int index, bit, i; + int pos = port; + int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4; + + /* CPU PORT can only be configured on RTL838x */ + if (port >= priv->cpu_port || port > 51) + return; + + mutex_lock(&priv->reg_mutex); + + /* For the RTL839x, the bits are left-aligned in the 128 bit field */ + if (priv->family_id == RTL8390_FAMILY_ID) + pos += 12; + + index = n - (pos >> 4) - 1; + bit = (pos << 1) % 32; + + if (priv->family_id == RTL8380_FAMILY_ID) { + cmd = BIT(15) /* Execute cmd */ + | BIT(14) /* Read */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + } else { + cmd = BIT(16) /* Execute cmd */ + | 0 << 15 /* Read */ + | 5 << 12 /* Table type 0b101 */ + | (msti & 0xfff); + } + priv->r->exec_tbl0_cmd(cmd); + + for (i = 0; i < n; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + + mutex_unlock(&priv->reg_mutex); +} + +int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg) +{ + u32 val; + u32 offset = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + if (phy_addr >= 24 && phy_addr <= 27 + && priv->ports[24].phy == PHY_RTL838X_SDS) { + if (phy_addr == 26) + offset = 0x100; + val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff; + return val; + } + + if (soc_info.family == RTL8390_FAMILY_ID) + rtl839x_read_phy(phy_addr, 0, phy_reg, &val); + else + rtl838x_read_phy(phy_addr, 0, phy_reg, &val); + return val; +} + +int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val) +{ + u32 offset = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + if (phy_addr >= 24 && phy_addr <= 27 + && priv->ports[24].phy == PHY_RTL838X_SDS) { + if (phy_addr == 26) + offset = 0x100; + sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)); + return 0; + } + if (soc_info.family == RTL8390_FAMILY_ID) + return rtl839x_write_phy(phy_addr, 0, phy_reg, val); + else + return rtl838x_write_phy(phy_addr, 0, phy_reg, val); +} + +static int rtl83xx_mdio_read(struct mii_bus *bus, int addr, int regnum) +{ + int ret; + struct rtl838x_switch_priv *priv = bus->priv; + + ret = rtl83xx_dsa_phy_read(priv->ds, addr, regnum); + return ret; +} + +static int rtl83xx_mdio_write(struct mii_bus *bus, int addr, int regnum, + u16 val) +{ + struct rtl838x_switch_priv *priv = bus->priv; + + return rtl83xx_dsa_phy_write(priv->ds, addr, regnum, val); +} + +static void rtl8380_sds_rst(int mac) +{ + u32 offset = (mac == 24) ? 0 : 0x100; + + sw_w32_mask(1 << 11, 0, RTL8380_SDS4_FIB_REG0 + offset); + sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28 + offset); + sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28 + offset); + sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0 + offset); + sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0 + offset); + pr_debug("SERDES reset: %d\n", mac); +} + +static int __init rtl8380_sds_power(int mac, int val) +{ + u32 mode = (val == 1) ? 0x4 : 0x9; + u32 offset = (mac == 24) ? 5 : 0; + + if ((mac != 24) && (mac != 26)) { + pr_err("%s: not a fibre port: %d\n", __func__, mac); + return -1; + } + + sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL); + + rtl8380_sds_rst(mac); + + return 0; +} + +static int __init rtl83xx_mdio_probe(struct rtl838x_switch_priv *priv) +{ + struct device *dev = priv->dev; + struct device_node *dn, *mii_np = dev->of_node; + struct mii_bus *bus; + int ret; + u32 pn; + + pr_debug("In %s\n", __func__); + mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio"); + if (mii_np) { + pr_debug("Found compatible MDIO node!\n"); + } else { + dev_err(priv->dev, "no %s child node found", "mdio-bus"); + return -ENODEV; + } + + priv->mii_bus = of_mdio_find_bus(mii_np); + if (!priv->mii_bus) { + pr_debug("Deferring probe of mdio bus\n"); + return -EPROBE_DEFER; + } + if (!of_device_is_available(mii_np)) + ret = -ENODEV; + + bus = devm_mdiobus_alloc(priv->ds->dev); + if (!bus) + return -ENOMEM; + + bus->name = "rtl838x slave mii"; + bus->read = &rtl83xx_mdio_read; + bus->write = &rtl83xx_mdio_write; + snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id); + bus->parent = dev; + priv->ds->slave_mii_bus = bus; + priv->ds->slave_mii_bus->priv = priv; + + ret = mdiobus_register(priv->ds->slave_mii_bus); + if (ret && mii_np) { + of_node_put(dn); + return ret; + } + + dn = mii_np; + for_each_node_by_name(dn, "ethernet-phy") { + if (of_property_read_u32(dn, "reg", &pn)) + continue; + + priv->ports[pn].dp = dsa_to_port(priv->ds, pn); + + // Check for the integrated SerDes of the RTL8380M first + if (of_property_read_bool(dn, "phy-is-integrated") + && priv->id == 0x8380 && pn >= 24) { + pr_debug("----> FĂ“UND A SERDES\n"); + priv->ports[pn].phy = PHY_RTL838X_SDS; + continue; + } + + if (of_property_read_bool(dn, "phy-is-integrated") + && !of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8218B_INT; + continue; + } + + if (!of_property_read_bool(dn, "phy-is-integrated") + && of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8214FC; + continue; + } + + if (!of_property_read_bool(dn, "phy-is-integrated") + && !of_property_read_bool(dn, "sfp")) { + priv->ports[pn].phy = PHY_RTL8218B_EXT; + continue; + } + } + + /* Disable MAC polling the PHY so that we can start configuration */ + priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl); + + /* Enable PHY control via SoC */ + if (priv->family_id == RTL8380_FAMILY_ID) { + /* Enable PHY control via SoC */ + sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL); + } else { + /* Disable PHY polling via SoC */ + sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL); + } + + /* Power on fibre ports and reset them if necessary */ + if (priv->ports[24].phy == PHY_RTL838X_SDS) { + pr_debug("Powering on fibre ports & reset\n"); + rtl8380_sds_power(24, 1); + rtl8380_sds_power(26, 1); + } + + pr_debug("%s done\n", __func__); + return 0; +} + +static int __init rtl83xx_get_l2aging(struct rtl838x_switch_priv *priv) +{ + int t = sw_r32(priv->r->l2_ctrl_1); + + t &= priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF; + + if (priv->family_id == RTL8380_FAMILY_ID) + t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */ + else + t = (t * 3) / 5; + + pr_debug("L2 AGING time: %d sec\n", t); + pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv->r->l2_port_aging_out)); + return t; +} + +static int __init rtl83xx_sw_probe(struct platform_device *pdev) +{ + int err = 0, i; + struct rtl838x_switch_priv *priv; + struct device *dev = &pdev->dev; + u64 irq_mask; + + pr_debug("Probing RTL838X switch device\n"); + if (!pdev->dev.of_node) { + dev_err(dev, "No DT found\n"); + return -EINVAL; + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS); + + if (!priv->ds) + return -ENOMEM; + priv->ds->dev = dev; + priv->ds->priv = priv; + priv->ds->ops = &rtl83xx_switch_ops; + priv->dev = dev; + + priv->family_id = soc_info.family; + priv->id = soc_info.id; + if (soc_info.family == RTL8380_FAMILY_ID) { + priv->cpu_port = RTL838X_CPU_PORT; + priv->port_mask = 0x1f; + priv->r = &rtl838x_reg; + priv->ds->num_ports = 30; + priv->fib_entries = 8192; + rtl8380_get_version(priv); + } else { + priv->cpu_port = RTL839X_CPU_PORT; + priv->port_mask = 0x3f; + priv->r = &rtl839x_reg; + priv->ds->num_ports = 53; + priv->fib_entries = 16384; + rtl8390_get_version(priv); + } + pr_debug("Chip version %c\n", priv->version); + + err = rtl83xx_mdio_probe(priv); + if (err) { + /* Probing fails the 1st time because of missing ethernet driver + * initialization. Use this to disable traffic in case the bootloader left if on + */ + return err; + } + err = dsa_register_switch(priv->ds); + if (err) { + dev_err(dev, "Error registering switch: %d\n", err); + return err; + } + + /* Enable link and media change interrupts. Are the SERDES masks needed? */ + sw_w32_mask(0, 3, priv->r->isr_glb_src); + /* ... for all ports */ + irq_mask = soc_info.family == RTL8380_FAMILY_ID ? 0x0FFFFFFF : 0xFFFFFFFFFFFFFULL; + priv->r->set_port_reg_le(irq_mask, priv->r->isr_port_link_sts_chg); + priv->r->set_port_reg_le(irq_mask, priv->r->imr_port_link_sts_chg); + + priv->link_state_irq = platform_get_irq(pdev, 0);; + if (priv->family_id == RTL8380_FAMILY_ID) { + err = request_irq(priv->link_state_irq, rtl838x_switch_irq, + IRQF_SHARED, "rtl838x-link-state", priv->ds); + } else { + err = request_irq(priv->link_state_irq, rtl839x_switch_irq, + IRQF_SHARED, "rtl839x-link-state", priv->ds); + } + if (err) { + dev_err(dev, "Error setting up switch interrupt.\n"); + /* Need to free allocated switch here */ + } + + /* Enable interrupts for switch */ + sw_w32(0x1, priv->r->imr_glb); + + rtl83xx_get_l2aging(priv); + +/* + if (priv->family_id == RTL8380_FAMILY_ID) + rtl83xx_storm_control_init(priv); +*/ + + /* Clear all destination ports for mirror groups */ + for (i = 0; i < 4; i++) + priv->mirror_group_ports[i] = -1; + + rtl838x_dbgfs_init(priv); + + return err; +} + +static int rtl83xx_sw_remove(struct platform_device *pdev) +{ + // TODO: + pr_debug("Removing platform driver for rtl83xx-sw\n"); + return 0; +} + +static const struct of_device_id rtl83xx_switch_of_ids[] = { + { .compatible = "realtek,rtl83xx-switch"}, + { /* sentinel */ } +}; + + +MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids); + +static struct platform_driver rtl83xx_switch_driver = { + .probe = rtl83xx_sw_probe, + .remove = rtl83xx_sw_remove, + .driver = { + .name = "rtl83xx-switch", + .pm = NULL, + .of_match_table = rtl83xx_switch_of_ids, + }, +}; + +module_platform_driver(rtl83xx_switch_driver); + +MODULE_AUTHOR("B. Koblitz"); +MODULE_DESCRIPTION("RTL83XX SoC Switch Driver"); +MODULE_LICENSE("GPL"); diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c new file mode 100644 index 0000000000..af24e8fa42 --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/debugfs.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <linux/debugfs.h> + +#include <asm/mach-rtl838x/mach-rtl83xx.h> +#include "rtl838x.h" + +#define RTL838X_DRIVER_NAME "rtl838x" + +static const struct debugfs_reg32 port_ctrl_regs[] = { + { .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), }, + { .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, }, +}; + +void rtl838x_dbgfs_cleanup(struct rtl838x_switch_priv *priv) +{ + debugfs_remove_recursive(priv->dbgfs_dir); + +// kfree(priv->dbgfs_entries); +} + +static int rtl838x_dbgfs_port_init(struct dentry *parent, struct rtl838x_switch_priv *priv, + int port) +{ + struct dentry *port_dir; + struct debugfs_regset32 *port_ctrl_regset; + + port_dir = debugfs_create_dir(priv->ports[port].dp->name, parent); + + debugfs_create_x32("rate_uc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_UC(port))); + + debugfs_create_x32("rate_mc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port))); + + debugfs_create_x32("rate_bc", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_STORM_CTRL_PORT_BC(port))); + + debugfs_create_u32("id", 0444, port_dir, &priv->ports[port].dp->index); + + + debugfs_create_x32("vlan_port_tag_sts_ctrl", 0644, port_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_VLAN_PORT_TAG_STS_CTRL(port))); + + port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL); + if (!port_ctrl_regset) + return -ENOMEM; + + port_ctrl_regset->regs = port_ctrl_regs; + port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs); + port_ctrl_regset->base = RTL838X_SW_BASE + (port << 2); + debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset); + + return 0; +} + +void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv) +{ + struct dentry *rtl838x_dir; + struct dentry *port_dir; + struct debugfs_regset32 *port_ctrl_regset; + int ret, i; + + rtl838x_dir = debugfs_lookup(RTL838X_DRIVER_NAME, NULL); + if (!rtl838x_dir) + rtl838x_dir = debugfs_create_dir(RTL838X_DRIVER_NAME, NULL); + + priv->dbgfs_dir = rtl838x_dir; + + debugfs_create_u32("soc", 0444, rtl838x_dir, + (u32 *)(RTL838X_SW_BASE + RTL838X_MODEL_NAME_INFO)); + + /* Create one directory per port */ + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) { + pr_debug("debugfs, port %d\n", i); + ret = rtl838x_dbgfs_port_init(rtl838x_dir, priv, i); + if (ret) + goto err; + } + } + + /* Create directory for CPU-port */ + port_dir = debugfs_create_dir("cpu_port", rtl838x_dir); port_ctrl_regset = devm_kzalloc(priv->dev, sizeof(*port_ctrl_regset), GFP_KERNEL); + if (!port_ctrl_regset) { + ret = -ENOMEM; + goto err; + } + + port_ctrl_regset->regs = port_ctrl_regs; + port_ctrl_regset->nregs = ARRAY_SIZE(port_ctrl_regs); + port_ctrl_regset->base = RTL838X_SW_BASE + (priv->cpu_port << 2); + debugfs_create_regset32("port_ctrl", 0400, port_dir, port_ctrl_regset); + debugfs_create_u8("id", 0444, port_dir, &priv->cpu_port); + + return; +err: + rtl838x_dbgfs_cleanup(priv); +} diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c new file mode 100644 index 0000000000..a0717e1d9a --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/dsa.c @@ -0,0 +1,1170 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <net/dsa.h> +#include <linux/if_bridge.h> + +#include <asm/mach-rtl838x/mach-rtl83xx.h> +#include "rtl83xx.h" + + +extern struct rtl83xx_soc_info soc_info; + + +static void rtl83xx_print_matrix(void) +{ + unsigned volatile int *ptr8; + volatile u64 *ptr9; + int i; + + if (soc_info.family == RTL8380_FAMILY_ID) { + ptr8 = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0); + for (i = 0; i < 28; i += 8) + pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n", + ptr8[i + 0], ptr8[i + 1], ptr8[i + 2], ptr8[i + 3], + ptr8[i + 4], ptr8[i + 5], ptr8[i + 6], ptr8[i + 7]); + pr_debug("CPU_PORT> %8x\n", ptr8[28]); + } else { + ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0); + for (i = 0; i < 52; i += 4) + pr_debug("> %16llx %16llx %16llx %16llx\n", + ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]); + pr_debug("CPU_PORT> %16llx\n", ptr9[52]); + } + +} + +static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv) +{ + mutex_lock(&priv->reg_mutex); + + /* Enable statistics module: all counters plus debug. + * On RTL839x all counters are enabled by default + */ + if (priv->family_id == RTL8380_FAMILY_ID) + sw_w32_mask(0, 3, RTL838X_STAT_CTRL); + + /* Reset statistics counters */ + sw_w32_mask(0, 1, priv->r->stat_rst); + + mutex_unlock(&priv->reg_mutex); +} + +static void rtl83xx_write_cam(int idx, u32 *r) +{ + u32 cmd = BIT(16) /* Execute cmd */ + | BIT(15) /* Read */ + | BIT(13) /* Table type 0b01 */ + | (idx & 0x3f); + + sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0)); + sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1)); + sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2)); + + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16)); +} + +static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid) +{ + if (priv->family_id == RTL8380_FAMILY_ID) + return rtl838x_hash(priv, mac << 12 | vid); + else + return rtl839x_hash(priv, mac << 12 | vid); +} + +static void rtl83xx_write_hash(int idx, u32 *r) +{ + u32 cmd = BIT(16) /* Execute cmd */ + | 0 << 15 /* Write */ + | 0 << 13 /* Table type 0b00 */ + | (idx & 0x1fff); + + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0)); + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1)); + sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2)); + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16)); +} + +static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv) +{ + int i; + u64 v = 0; + + msleep(1000); + /* Enable all ports with a PHY, including the SFP-ports */ + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) + v |= BIT(i); + } + + pr_debug("%s: %16llx\n", __func__, v); + priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl); + + /* PHY update complete */ + if (priv->family_id == RTL8390_FAMILY_ID) + sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL); + else + sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL); +} + +const struct rtl83xx_mib_desc rtl83xx_mib[] = { + MIB_DESC(2, 0xf8, "ifInOctets"), + MIB_DESC(2, 0xf0, "ifOutOctets"), + MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"), + MIB_DESC(1, 0xe8, "ifInUcastPkts"), + MIB_DESC(1, 0xe4, "ifInMulticastPkts"), + MIB_DESC(1, 0xe0, "ifInBroadcastPkts"), + MIB_DESC(1, 0xdc, "ifOutUcastPkts"), + MIB_DESC(1, 0xd8, "ifOutMulticastPkts"), + MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"), + MIB_DESC(1, 0xd0, "ifOutDiscards"), + MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"), + MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"), + MIB_DESC(1, 0xc4, ".3DeferredTransmissions"), + MIB_DESC(1, 0xc0, ".3LateCollisions"), + MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"), + MIB_DESC(1, 0xb8, ".3SymbolErrors"), + MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"), + MIB_DESC(1, 0xb0, ".3InPauseFrames"), + MIB_DESC(1, 0xac, ".3OutPauseFrames"), + MIB_DESC(1, 0xa8, "DropEvents"), + MIB_DESC(1, 0xa4, "tx_BroadcastPkts"), + MIB_DESC(1, 0xa0, "tx_MulticastPkts"), + MIB_DESC(1, 0x9c, "CRCAlignErrors"), + MIB_DESC(1, 0x98, "tx_UndersizePkts"), + MIB_DESC(1, 0x94, "rx_UndersizePkts"), + MIB_DESC(1, 0x90, "rx_UndersizedropPkts"), + MIB_DESC(1, 0x8c, "tx_OversizePkts"), + MIB_DESC(1, 0x88, "rx_OversizePkts"), + MIB_DESC(1, 0x84, "Fragments"), + MIB_DESC(1, 0x80, "Jabbers"), + MIB_DESC(1, 0x7c, "Collisions"), + MIB_DESC(1, 0x78, "tx_Pkts64Octets"), + MIB_DESC(1, 0x74, "rx_Pkts64Octets"), + MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"), + MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"), + MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"), + MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"), + MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"), + MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"), + MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"), + MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"), + MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"), + MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"), + MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"), + MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"), + MIB_DESC(1, 0x40, "rxMacDiscards") +}; + + +/* DSA callbacks */ + + +static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port) +{ + /* The switch does not tag the frames, instead internally the header + * structure for each packet is tagged accordingly. + */ + return DSA_TAG_PROTO_TRAILER; +} + +static int rtl83xx_setup(struct dsa_switch *ds) +{ + int i; + struct rtl838x_switch_priv *priv = ds->priv; + u64 port_bitmap = BIT_ULL(priv->cpu_port); + + pr_debug("%s called\n", __func__); + + /* Disable MAC polling the PHY so that we can start configuration */ + priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl); + + for (i = 0; i < ds->num_ports; i++) + priv->ports[i].enable = false; + priv->ports[priv->cpu_port].enable = true; + + /* Isolate ports from each other: traffic only CPU <-> port */ + /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows + * traffic from source port i to destination port j + */ + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) { + priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i), + priv->r->port_iso_ctrl(i)); + port_bitmap |= BIT_ULL(i); + } + } + priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port)); + + rtl83xx_print_matrix(); + + rtl83xx_init_stats(priv); + + ds->configure_vlan_while_not_filtering = true; + + /* Enable MAC Polling PHY again */ + rtl83xx_enable_phy_polling(priv); + pr_debug("Please wait until PHY is settled\n"); + msleep(1000); + return 0; +} + +static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port, + unsigned long *supported, + struct phylink_link_state *state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; + + pr_debug("In %s port %d", __func__, port); + + if (!phy_interface_mode_is_rgmii(state->interface) && + state->interface != PHY_INTERFACE_MODE_1000BASEX && + state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII && + state->interface != PHY_INTERFACE_MODE_GMII && + state->interface != PHY_INTERFACE_MODE_QSGMII && + state->interface != PHY_INTERFACE_MODE_INTERNAL && + state->interface != PHY_INTERFACE_MODE_SGMII) { + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); + dev_err(ds->dev, + "Unsupported interface: %d for port %d\n", + state->interface, port); + return; + } + + /* Allow all the expected bits */ + phylink_set(mask, Autoneg); + phylink_set_port_modes(mask); + phylink_set(mask, Pause); + phylink_set(mask, Asym_Pause); + + /* With the exclusion of MII and Reverse MII, we support Gigabit, + * including Half duplex + */ + if (state->interface != PHY_INTERFACE_MODE_MII && + state->interface != PHY_INTERFACE_MODE_REVMII) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + } + + /* On both the 8380 and 8382, ports 24-27 are SFP ports */ + if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID) + phylink_set(mask, 1000baseX_Full); + + phylink_set(mask, 10baseT_Half); + phylink_set(mask, 10baseT_Full); + phylink_set(mask, 100baseT_Half); + phylink_set(mask, 100baseT_Full); + + bitmap_and(supported, supported, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); + bitmap_and(state->advertising, state->advertising, mask, + __ETHTOOL_LINK_MODE_MASK_NBITS); +} + +static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port, + struct phylink_link_state *state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 speed; + + if (port < 0 || port > priv->cpu_port) + return -EINVAL; + + state->link = 0; + if (priv->r->get_port_reg_le(priv->r->mac_link_sts) & BIT_ULL(port)) + state->link = 1; + state->duplex = 0; + if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port)) + state->duplex = 1; + + speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port)); + speed >>= (port % 16) << 1; + switch (speed & 0x3) { + case 0: + state->speed = SPEED_10; + break; + case 1: + state->speed = SPEED_100; + break; + case 2: + state->speed = SPEED_1000; + break; + case 3: + if (port == 24 || port == 26) /* Internal serdes */ + state->speed = SPEED_2500; + else + state->speed = SPEED_100; /* Is in fact 500Mbit */ + } + + state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX); + if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port)) + state->pause |= MLO_PAUSE_RX; + if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port)) + state->pause |= MLO_PAUSE_TX; + return 1; +} + +static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port, + unsigned int mode, + const struct phylink_link_state *state) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u32 reg; + int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3; + + pr_debug("%s port %d, mode %x\n", __func__, port, mode); + + if (port == priv->cpu_port) { + /* Set Speed, duplex, flow control + * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL + * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN + * | MEDIA_SEL + */ + if (priv->family_id == RTL8380_FAMILY_ID) { + sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + /* allow CRC errors on CPU-port */ + sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port)); + } else { + sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port)); + } + return; + } + + reg = sw_r32(priv->r->mac_force_mode_ctrl(port)); + /* Auto-Negotiation does not work for MAC in RTL8390 */ + if (priv->family_id == RTL8380_FAMILY_ID) { + if (mode == MLO_AN_PHY) { + pr_debug("PHY autonegotiates\n"); + reg |= BIT(2); + sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); + return; + } + } + + if (mode != MLO_AN_FIXED) + pr_debug("Fixed state.\n"); + + if (priv->family_id == RTL8380_FAMILY_ID) { + /* Clear id_mode_dis bit, and the existing port mode, let + * RGMII_MODE_EN bet set by mac_link_{up,down} + */ + reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); + + if (state->pause & MLO_PAUSE_TXRX_MASK) { + if (state->pause & MLO_PAUSE_TX) + reg |= TX_PAUSE_EN; + reg |= RX_PAUSE_EN; + } + } + + reg &= ~(3 << speed_bit); + switch (state->speed) { + case SPEED_1000: + reg |= 2 << speed_bit; + break; + case SPEED_100: + reg |= 1 << speed_bit; + break; + } + + if (priv->family_id == RTL8380_FAMILY_ID) { + reg &= ~(DUPLEX_FULL | FORCE_LINK_EN); + if (state->link) + reg |= FORCE_LINK_EN; + if (state->duplex == DUPLEX_FULL) + reg |= DUPLX_MODE; + } + + // Disable AN + if (priv->family_id == RTL8380_FAMILY_ID) + reg &= ~BIT(2); + sw_w32(reg, priv->r->mac_force_mode_ctrl(port)); +} + +static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface) +{ + struct rtl838x_switch_priv *priv = ds->priv; + /* Stop TX/RX to port */ + sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port)); +} + +static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port, + unsigned int mode, + phy_interface_t interface, + struct phy_device *phydev) +{ + struct rtl838x_switch_priv *priv = ds->priv; + /* Restart TX/RX to port */ + sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port)); +} + +static void rtl83xx_get_strings(struct dsa_switch *ds, + int port, u32 stringset, u8 *data) +{ + int i; + + if (stringset != ETH_SS_STATS) + return; + + for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) + strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name, + ETH_GSTRING_LEN); +} + +static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port, + uint64_t *data) +{ + struct rtl838x_switch_priv *priv = ds->priv; + const struct rtl83xx_mib_desc *mib; + int i; + u64 high; + + for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) { + mib = &rtl83xx_mib[i]; + + data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset); + if (mib->size == 2) { + high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4); + data[i] |= high << 32; + } + } +} + +static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset) +{ + if (sset != ETH_SS_STATS) + return 0; + + return ARRAY_SIZE(rtl83xx_mib); +} + +static int rtl83xx_port_enable(struct dsa_switch *ds, int port, + struct phy_device *phydev) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s: %x %d", __func__, (u32) priv, port); + priv->ports[port].enable = true; + + /* enable inner tagging on egress, do not keep any tags */ + sw_w32(1, priv->r->vlan_port_tag_sts_ctrl(port)); + + if (dsa_is_cpu_port(ds, port)) + return 0; + + /* add port to switch mask of CPU_PORT */ + priv->r->mask_port_reg_be(0ULL, BIT_ULL(port), priv->r->port_iso_ctrl(priv->cpu_port)); + + /* add all other ports in the same bridge to switch mask of port */ + priv->r->mask_port_reg_be(0ULL, priv->ports[port].pm, priv->r->port_iso_ctrl(port)); + + return 0; +} + +static void rtl83xx_port_disable(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s %x: %d", __func__, (u32)priv, port); + /* you can only disable user ports */ + if (!dsa_is_user_port(ds, port)) + return; + + /* remove port from switch mask of CPU_PORT */ + priv->r->mask_port_reg_be(BIT_ULL(port), 0, priv->r->port_iso_ctrl(priv->cpu_port)); + + /* remove all other ports in the same bridge from switch mask of port */ + priv->r->mask_port_reg_be(priv->ports[port].pm, 0LL, priv->r->port_iso_ctrl(port)); + + priv->ports[port].enable = false; +} + +static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_eee *e) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s: port %d", __func__, port); + e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full; + if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(9)) + e->advertised |= ADVERTISED_100baseT_Full; + + if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(10)) + e->advertised |= ADVERTISED_1000baseT_Full; + + e->eee_enabled = priv->ports[port].eee_enabled; + pr_debug("enabled: %d, active %x\n", e->eee_enabled, e->advertised); + + if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) { + e->lp_advertised = ADVERTISED_100baseT_Full; + e->lp_advertised |= ADVERTISED_1000baseT_Full; + } + + e->eee_active = !!(e->advertised & e->lp_advertised); + pr_debug("active: %d, lp %x\n", e->eee_active, e->lp_advertised); + + return 0; +} + +static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port, + struct ethtool_eee *e) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s: port %d", __func__, port); + if (e->eee_enabled) { + pr_debug("Globally enabling EEE\n"); + sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL); + } + if (e->eee_enabled) { + pr_debug("Enabling EEE for MAC %d\n", port); + sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port)); + sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN); + sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN); + priv->ports[port].eee_enabled = true; + e->eee_enabled = true; + } else { + pr_debug("Disabling EEE for MAC %d\n", port); + sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port)); + sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN); + sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN); + priv->ports[port].eee_enabled = false; + e->eee_enabled = false; + } + return 0; +} + +/* + * Set Switch L2 Aging time, t is time in milliseconds + * t = 0: aging is disabled + */ +static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF; + + /* Convert time in mseconds to internal value */ + if (t > 0x10000000) { /* Set to maximum */ + t = t_max; + } else { + if (priv->family_id == RTL8380_FAMILY_ID) + t = ((t * 625) / 1000 + 127) / 128; + else + t = (t * 5 + 2) / 3; + } + sw_w32(t, priv->r->l2_ctrl_1); + return 0; +} + +static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port, + struct net_device *bridge) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 port_bitmap = BIT_ULL(priv->cpu_port); + int i; + + pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < ds->num_ports; i++) { + /* Add this port to the port matrix of the other ports in the + * same bridge. If the port is disabled, port matrix is kept + * and not being setup until the port becomes enabled. + */ + if (dsa_is_user_port(ds, i) && i != port) { + if (dsa_to_port(ds, i)->bridge_dev != bridge) + continue; + if (priv->ports[i].enable) + priv->r->mask_port_reg_be(0, BIT_ULL(port), + priv->r->port_iso_ctrl(i)); + priv->ports[i].pm |= BIT_ULL(port); + + port_bitmap |= BIT_ULL(i); + } + } + + /* Add all other ports to this port matrix. */ + if (priv->ports[port].enable) { + priv->r->mask_port_reg_be(0, BIT_ULL(port), + priv->r->port_iso_ctrl(priv->cpu_port)); + priv->r->mask_port_reg_be(0, port_bitmap, + priv->r->port_iso_ctrl(port)); + } + priv->ports[port].pm |= port_bitmap; + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port, + struct net_device *bridge) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 port_bitmap = BIT_ULL(priv->cpu_port); + int i; + + pr_debug("%s %x: %d", __func__, (u32)priv, port); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < ds->num_ports; i++) { + /* Remove this port from the port matrix of the other ports + * in the same bridge. If the port is disabled, port matrix + * is kept and not being setup until the port becomes enabled. + * And the other port's port matrix cannot be broken when the + * other port is still a VLAN-aware port. + */ + if (dsa_is_user_port(ds, i) && i != port) { + if (dsa_to_port(ds, i)->bridge_dev != bridge) + continue; + if (priv->ports[i].enable) + priv->r->mask_port_reg_be(BIT_ULL(port), 0, + priv->r->port_iso_ctrl(i)); + priv->ports[i].pm &= ~BIT_ULL(port); + + port_bitmap &= ~BIT_ULL(i); + } + } + + /* Add all other ports to this port matrix. */ + if (priv->ports[port].enable) + priv->r->mask_port_reg_be(0, port_bitmap, priv->r->port_iso_ctrl(port)); + priv->ports[port].pm &= ~port_bitmap; + + mutex_unlock(&priv->reg_mutex); +} + +static void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, + u8 state) +{ + u32 cmd, msti = 0; + u32 port_state[4]; + int index, bit, i; + int pos = port; + struct rtl838x_switch_priv *priv = ds->priv; + int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4; + + pr_debug("%s: port %d state %2x\n", __func__, port, state); + + /* CPU PORT can only be configured on RTL838x */ + if (port >= priv->cpu_port || port > 51) + return; + + mutex_lock(&priv->reg_mutex); + + /* For the RTL839x, the bits are left-aligned in the 128 bit field */ + if (priv->family_id == RTL8390_FAMILY_ID) + pos += 12; + + index = n - (pos >> 4) - 1; + bit = (pos << 1) % 32; + + if (priv->family_id == RTL8380_FAMILY_ID) { + cmd = BIT(15) /* Execute cmd */ + | BIT(14) /* Read */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + } else { + cmd = BIT(16) /* Execute cmd */ + | 0 << 15 /* Read */ + | 5 << 12 /* Table type 0b101 */ + | (msti & 0xfff); + } + priv->r->exec_tbl0_cmd(cmd); + + for (i = 0; i < n; i++) + port_state[i] = sw_r32(priv->r->tbl_access_data_0(i)); + + pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3); + port_state[index] &= ~(3 << bit); + + switch (state) { + case BR_STATE_DISABLED: /* 0 */ + port_state[index] |= (0 << bit); + break; + case BR_STATE_BLOCKING: /* 4 */ + case BR_STATE_LISTENING: /* 1 */ + port_state[index] |= (1 << bit); + break; + case BR_STATE_LEARNING: /* 2 */ + port_state[index] |= (2 << bit); + break; + case BR_STATE_FORWARDING: /* 3*/ + port_state[index] |= (3 << bit); + default: + break; + } + + if (priv->family_id == RTL8380_FAMILY_ID) { + cmd = BIT(15) /* Execute cmd */ + | 0 << 14 /* Write */ + | 2 << 12 /* Table type 0b10 */ + | (msti & 0xfff); + } else { + cmd = 1 << 16 /* Execute cmd */ + | BIT(15) /* Write */ + | 5 << 12 /* Table type 0b101 */ + | (msti & 0xfff); + } + for (i = 0; i < n; i++) + sw_w32(port_state[i], priv->r->tbl_access_data_0(i)); + priv->r->exec_tbl0_cmd(cmd); + + mutex_unlock(&priv->reg_mutex); +} + +static void rtl83xx_fast_age(struct dsa_switch *ds, int port) +{ + struct rtl838x_switch_priv *priv = ds->priv; + int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0; + + pr_debug("FAST AGE port %d\n", port); + mutex_lock(&priv->reg_mutex); + /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger + * port fields: + * 0-4: Replacing port + * 5-9: Flushed/replaced port + * 10-21: FVID + * 22: Entry types: 1: dynamic, 0: also static + * 23: Match flush port + * 24: Match FVID + * 25: Flush (0) or replace (1) L2 entries + * 26: Status of action (1: Start, 0: Done) + */ + sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl); + + do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s))); + + mutex_unlock(&priv->reg_mutex); +} + +static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port, + bool vlan_filtering) +{ + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s: port %d\n", __func__, port); + mutex_lock(&priv->reg_mutex); + + if (vlan_filtering) { + /* Enable ingress and egress filtering */ + if (port != priv->cpu_port) + sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1), + priv->r->vlan_port_igr_filter(port)); + sw_w32_mask(0, 1 << (port % 32), priv->r->vlan_port_egr_filter(port)); + } else { + /* Disable ingress and egress filtering */ + if (port != priv->cpu_port) + sw_w32_mask(0b11 << ((port % 16) << 1), 0, + priv->r->vlan_port_igr_filter(port)); + sw_w32_mask(1 << (port % 32), 0, priv->r->vlan_port_egr_filter(port)); + } + + /* Do we need to do something to the CPU-Port, too? */ + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("%s: port %d\n", __func__, port); + + mutex_lock(&priv->reg_mutex); + + if (priv->family_id == RTL8380_FAMILY_ID) + rtl838x_vlan_profile_dump(0); + else + rtl839x_vlan_profile_dump(0); + + priv->r->vlan_tables_read(0, &info); + + pr_debug("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n", + info.tagged_ports, info.untagged_ports, info.profile_id, + info.hash_mc_fid, info.hash_uc_fid, info.fid); + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static void rtl83xx_vlan_add(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info = {}; + struct rtl838x_switch_priv *priv = ds->priv; + int v; + + pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__, + port, vlan->vid_begin, vlan->vid_end, vlan->flags); + + if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { + dev_err(priv->dev, "VLAN out of range: %d - %d", + vlan->vid_begin, vlan->vid_end); + return; + } + + mutex_lock(&priv->reg_mutex); + + if (vlan->flags & BRIDGE_VLAN_INFO_PVID) { + /* Set both inner and outer PVID of the port */ + sw_w32((vlan->vid_end << 16) | vlan->vid_end << 2, priv->r->vlan_port_pb(port)); + priv->ports[port].pvid = vlan->vid_end; + } + + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Get port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + + /* new VLAN? */ + if (!info.tagged_ports) { + info.fid = 0; + info.hash_mc_fid = false; + info.hash_uc_fid = false; + info.profile_id = 0; + } + + /* sanitize untagged_ports - must be a subset */ + if (info.untagged_ports & ~info.tagged_ports) + info.untagged_ports = 0; + + info.tagged_ports |= BIT_ULL(port); + if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) + info.untagged_ports |= BIT_ULL(port); + + priv->r->vlan_set_untagged(v, info.untagged_ports); + pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports); + + priv->r->vlan_set_tagged(v, &info); + pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports); + } + + mutex_unlock(&priv->reg_mutex); +} + +static int rtl83xx_vlan_del(struct dsa_switch *ds, int port, + const struct switchdev_obj_port_vlan *vlan) +{ + struct rtl838x_vlan_info info; + struct rtl838x_switch_priv *priv = ds->priv; + int v; + u16 pvid; + + pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__, + port, vlan->vid_begin, vlan->vid_end, vlan->flags); + + if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) { + dev_err(priv->dev, "VLAN out of range: %d - %d", + vlan->vid_begin, vlan->vid_end); + return -ENOTSUPP; + } + + mutex_lock(&priv->reg_mutex); + pvid = priv->ports[port].pvid; + + for (v = vlan->vid_begin; v <= vlan->vid_end; v++) { + /* Reset to default if removing the current PVID */ + if (v == pvid) + sw_w32(0, priv->r->vlan_port_pb(port)); + + /* Get port memberships of this vlan */ + priv->r->vlan_tables_read(v, &info); + + /* remove port from both tables */ + info.untagged_ports &= (~BIT_ULL(port)); + /* always leave vid 1 */ + if (v != 1) + info.tagged_ports &= (~BIT_ULL(port)); + + priv->r->vlan_set_untagged(v, info.untagged_ports); + pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports); + + priv->r->vlan_set_tagged(v, &info); + pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports); + } + mutex_unlock(&priv->reg_mutex); + + return 0; +} + +static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(addr); + u32 key = rtl83xx_hash_key(priv, mac, vid); + struct rtl838x_l2_entry e; + u32 r[3]; + u64 entry; + int idx = -1, err = 0, i; + + mutex_lock(&priv->reg_mutex); + for (i = 0; i < 4; i++) { + entry = priv->r->read_l2_entry_using_hash(key, i, &e); + if (!e.valid) { + idx = (key << 2) | i; + break; + } + if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) { + idx = (key << 2) | i; + break; + } + } + if (idx >= 0) { + r[0] = 3 << 17 | port << 12; // Aging and port + r[0] |= vid; + r[1] = mac >> 16; + r[2] = (mac & 0xffff) << 12; /* rvid = 0 */ + rtl83xx_write_hash(idx, r); + goto out; + } + + /* Hash buckets full, try CAM */ + for (i = 0; i < 64; i++) { + entry = priv->r->read_cam(i, &e); + if (!e.valid) { + if (idx < 0) /* First empty entry? */ + idx = i; + break; + } else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) { + pr_debug("Found entry in CAM\n"); + idx = i; + break; + } + } + if (idx >= 0) { + r[0] = 3 << 17 | port << 12; // Aging + r[0] |= vid; + r[1] = mac >> 16; + r[2] = (mac & 0xffff) << 12; /* rvid = 0 */ + rtl83xx_write_cam(idx, r); + goto out; + } + err = -ENOTSUPP; +out: + mutex_unlock(&priv->reg_mutex); + return err; +} + +static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port, + const unsigned char *addr, u16 vid) +{ + struct rtl838x_switch_priv *priv = ds->priv; + u64 mac = ether_addr_to_u64(addr); + u32 key = rtl83xx_hash_key(priv, mac, vid); + struct rtl838x_l2_entry e; + u32 r[3]; + u64 entry; + int idx = -1, err = 0, i; + + pr_debug("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key); + mutex_lock(&priv->reg_mutex); + for (i = 0; i < 4; i++) { + entry = priv->r->read_l2_entry_using_hash(key, i, &e); + if (!e.valid) + continue; + if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) { + idx = (key << 2) | i; + break; + } + } + + if (idx >= 0) { + r[0] = r[1] = r[2] = 0; + rtl83xx_write_hash(idx, r); + goto out; + } + + /* Check CAM for spillover from hash buckets */ + for (i = 0; i < 64; i++) { + entry = priv->r->read_cam(i, &e); + if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) { + idx = i; + break; + } + } + if (idx >= 0) { + r[0] = r[1] = r[2] = 0; + rtl83xx_write_cam(idx, r); + goto out; + } + err = -ENOENT; +out: + mutex_unlock(&priv->reg_mutex); + return err; +} + +static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port, + dsa_fdb_dump_cb_t *cb, void *data) +{ + struct rtl838x_l2_entry e; + struct rtl838x_switch_priv *priv = ds->priv; + int i; + u32 fid; + u32 pkey; + u64 mac; + + mutex_lock(&priv->reg_mutex); + + for (i = 0; i < priv->fib_entries; i++) { + priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e); + + if (!e.valid) + continue; + + if (e.port == port) { + fid = (i & 0x3ff) | (e.rvid & ~0x3ff); + mac = ether_addr_to_u64(&e.mac[0]); + pkey = rtl838x_hash(priv, mac << 12 | fid); + fid = (pkey & 0x3ff) | (fid & ~0x3ff); + pr_debug("-> mac %016llx, fid: %d\n", mac, fid); + cb(e.mac, e.vid, e.is_static, data); + } + } + + for (i = 0; i < 64; i++) { + priv->r->read_cam(i, &e); + + if (!e.valid) + continue; + + if (e.port == port) + cb(e.mac, e.vid, e.is_static, data); + } + + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror, + bool ingress) +{ + /* We support 4 mirror groups, one destination port per group */ + int group; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("In %s\n", __func__); + + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] == mirror->to_local_port) + break; + } + if (group >= 4) { + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] < 0) + break; + } + } + + if (group >= 4) + return -ENOSPC; + + pr_debug("Using group %d\n", group); + mutex_lock(&priv->reg_mutex); + + if (priv->family_id == RTL8380_FAMILY_ID) { + /* Enable mirroring to port across VLANs (bit 11) */ + sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group)); + } else { + /* Enable mirroring to destination port */ + sw_w32((mirror->to_local_port << 4) | 1, RTL839X_MIR_CTRL(group)); + } + + if (ingress && (priv->r->get_port_reg_be(priv->r->mir_spm(group)) & (1ULL << port))) { + mutex_unlock(&priv->reg_mutex); + return -EEXIST; + } + if ((!ingress) && (priv->r->get_port_reg_be(priv->r->mir_dpm(group)) & (1ULL << port))) { + mutex_unlock(&priv->reg_mutex); + return -EEXIST; + } + + if (ingress) + priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_spm(group)); + else + priv->r->mask_port_reg_be(0, 1ULL << port, priv->r->mir_dpm(group)); + + priv->mirror_group_ports[group] = mirror->to_local_port; + mutex_unlock(&priv->reg_mutex); + return 0; +} + +static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port, + struct dsa_mall_mirror_tc_entry *mirror) +{ + int group = 0; + struct rtl838x_switch_priv *priv = ds->priv; + + pr_debug("In %s\n", __func__); + for (group = 0; group < 4; group++) { + if (priv->mirror_group_ports[group] == mirror->to_local_port) + break; + } + if (group >= 4) + return; + + mutex_lock(&priv->reg_mutex); + if (mirror->ingress) { + /* Ingress, clear source port matrix */ + priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_spm(group)); + } else { + /* Egress, clear destination port matrix */ + priv->r->mask_port_reg_be(1ULL << port, 0, priv->r->mir_dpm(group)); + } + + if (!(sw_r32(priv->r->mir_spm(group)) || sw_r32(priv->r->mir_dpm(group)))) { + priv->mirror_group_ports[group] = -1; + sw_w32(0, priv->r->mir_ctrl(group)); + } + + mutex_unlock(&priv->reg_mutex); +} + +const struct dsa_switch_ops rtl83xx_switch_ops = { + .get_tag_protocol = rtl83xx_get_tag_protocol, + .setup = rtl83xx_setup, + + .phy_read = rtl83xx_dsa_phy_read, + .phy_write = rtl83xx_dsa_phy_write, + + .phylink_validate = rtl83xx_phylink_validate, + .phylink_mac_link_state = rtl83xx_phylink_mac_link_state, + .phylink_mac_config = rtl83xx_phylink_mac_config, + .phylink_mac_link_down = rtl83xx_phylink_mac_link_down, + .phylink_mac_link_up = rtl83xx_phylink_mac_link_up, + + .get_strings = rtl83xx_get_strings, + .get_ethtool_stats = rtl83xx_get_ethtool_stats, + .get_sset_count = rtl83xx_get_sset_count, + + .port_enable = rtl83xx_port_enable, + .port_disable = rtl83xx_port_disable, + + .get_mac_eee = rtl83xx_get_mac_eee, + .set_mac_eee = rtl83xx_set_mac_eee, + + .set_ageing_time = rtl83xx_set_l2aging, + .port_bridge_join = rtl83xx_port_bridge_join, + .port_bridge_leave = rtl83xx_port_bridge_leave, + .port_stp_state_set = rtl83xx_port_stp_state_set, + .port_fast_age = rtl83xx_fast_age, + + .port_vlan_filtering = rtl83xx_vlan_filtering, + .port_vlan_prepare = rtl83xx_vlan_prepare, + .port_vlan_add = rtl83xx_vlan_add, + .port_vlan_del = rtl83xx_vlan_del, + + .port_fdb_add = rtl83xx_port_fdb_add, + .port_fdb_del = rtl83xx_port_fdb_del, + .port_fdb_dump = rtl83xx_port_fdb_dump, + + .port_mirror_add = rtl83xx_port_mirror_add, + .port_mirror_del = rtl83xx_port_mirror_del, +}; + diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c new file mode 100644 index 0000000000..c7b5873e99 --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.c @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/mach-rtl838x/mach-rtl83xx.h> +#include "rtl83xx.h" + +extern struct mutex smi_lock; + + +static inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32)clear, (u32)set, reg); +} + +static inline void rtl838x_set_port_reg(u64 set, int reg) +{ + sw_w32(set, reg); +} + +static inline u64 rtl838x_get_port_reg(int reg) +{ + return ((u64) sw_r32(reg)); +} + +static inline int rtl838x_stat_port_std_mib(int p) +{ + return RTL838X_STAT_PORT_STD_MIB + (p << 8); +} + +static inline int rtl838x_port_iso_ctrl(int p) +{ + return RTL838X_PORT_ISO_CTRL(p); +} + +static inline void rtl838x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & BIT(15)); +} + +static inline void rtl838x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & BIT(15)); +} + +static inline int rtl838x_tbl_access_data_0(int i) +{ + return RTL838X_TBL_ACCESS_DATA_0(i); +} + +static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 cmd, v; + + cmd = BIT(15) /* Execute cmd */ + | BIT(14) /* Read */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + rtl838x_exec_tbl0_cmd(cmd); + info->tagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0)); + v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)); + info->profile_id = v & 0x7; + info->hash_mc_fid = !!(v & 0x8); + info->hash_uc_fid = !!(v & 0x10); + info->fid = (v >> 5) & 0x3f; + + + cmd = BIT(15) /* Execute cmd */ + | BIT(14) /* Read */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + rtl838x_exec_tbl1_cmd(cmd); + info->untagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0)); +} + +static void rtl838x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 cmd = BIT(15) /* Execute cmd */ + | 0 << 14 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + u32 v; + + sw_w32(info->tagged_ports, RTL838X_TBL_ACCESS_DATA_0(0)); + + v = info->profile_id; + v |= info->hash_mc_fid ? 0x8 : 0; + v |= info->hash_uc_fid ? 0x10 : 0; + v |= ((u32)info->fid) << 5; + + sw_w32(v, RTL838X_TBL_ACCESS_DATA_0(1)); + rtl838x_exec_tbl0_cmd(cmd); +} + +static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + u32 cmd = BIT(15) /* Execute cmd */ + | 0 << 14 /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + sw_w32(portmask & 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0)); + rtl838x_exec_tbl1_cmd(cmd); +} + +static inline int rtl838x_mac_force_mode_ctrl(int p) +{ + return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl838x_mac_port_ctrl(int p) +{ + return RTL838X_MAC_PORT_CTRL(p); +} + +static inline int rtl838x_l2_port_new_salrn(int p) +{ + return RTL838X_L2_PORT_NEW_SALRN(p); +} + +static inline int rtl838x_l2_port_new_sa_fwd(int p) +{ + return RTL838X_L2_PORT_NEW_SA_FWD(p); +} + +static inline int rtl838x_mir_ctrl(int group) +{ + return RTL838X_MIR_CTRL(group); +} + +static inline int rtl838x_mir_dpm(int group) +{ + return RTL838X_MIR_DPM_CTRL(group); +} + +static inline int rtl838x_mir_spm(int group) +{ + return RTL838X_MIR_SPM_CTRL(group); +} + +static inline int rtl838x_mac_link_spd_sts(int p) +{ + return RTL838X_MAC_LINK_SPD_STS(p); +} + +static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e) +{ + u64 entry; + u32 r[3]; + + /* Search in SRAM, with hash and at position in hash bucket (0-3) */ + u32 idx = (0 << 14) | (hash << 2) | position; + + u32 cmd = BIT(16) /* Execute cmd */ + | BIT(15) /* Read */ + | 0 << 13 /* Table type 0b00 */ + | (idx & 0x1fff); + + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16)); + r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0)); + r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1)); + r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2)); + + e->mac[0] = (r[1] >> 20); + e->mac[1] = (r[1] >> 12); + e->mac[2] = (r[1] >> 4); + e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + e->mac[4] = (r[2] >> 20); + e->mac[5] = (r[2] >> 12); + e->is_static = !!((r[0] >> 19) & 1); + e->vid = r[0] & 0xfff; + e->rvid = r[2] & 0xfff; + e->port = (r[0] >> 12) & 0x1f; + + e->valid = true; + if (!(r[0] >> 17)) /* Check for invalid entry */ + e->valid = false; + + if (e->valid) + pr_debug("Found in Hash: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); + + entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff); + return entry; +} + +static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e) +{ + u64 entry; + u32 r[3]; + + u32 cmd = BIT(16) /* Execute cmd */ + | BIT(15) /* Read */ + | BIT(13) /* Table type 0b01 */ + | (idx & 0x3f); + sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16)); + r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0)); + r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1)); + r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2)); + + e->mac[0] = (r[1] >> 20); + e->mac[1] = (r[1] >> 12); + e->mac[2] = (r[1] >> 4); + e->mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28); + e->mac[4] = (r[2] >> 20); + e->mac[5] = (r[2] >> 12); + e->is_static = !!((r[0] >> 19) & 1); + e->vid = r[0] & 0xfff; + e->rvid = r[2] & 0xfff; + e->port = (r[0] >> 12) & 0x1f; + + e->valid = true; + if (!(r[0] >> 17)) /* Check for invalid entry */ + e->valid = false; + + if (e->valid) + pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); + + entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff); + return entry; +} + +static inline int rtl838x_vlan_profile(int profile) +{ + return RTL838X_VLAN_PROFILE(profile); +} + +static inline int rtl838x_vlan_port_egr_filter(int port) +{ + return RTL838X_VLAN_PORT_EGR_FLTR; +} + +static inline int rtl838x_vlan_port_igr_filter(int port) +{ + return RTL838X_VLAN_PORT_IGR_FLTR(port); +} + +static inline int rtl838x_vlan_port_pb(int port) +{ + return RTL838X_VLAN_PORT_PB_VLAN(port); +} + +static inline int rtl838x_vlan_port_tag_sts_ctrl(int port) +{ + return RTL838X_VLAN_PORT_TAG_STS_CTRL(port); +} + +const struct rtl838x_reg rtl838x_reg = { + .mask_port_reg_be = rtl838x_mask_port_reg, + .set_port_reg_be = rtl838x_set_port_reg, + .get_port_reg_be = rtl838x_get_port_reg, + .mask_port_reg_le = rtl838x_mask_port_reg, + .set_port_reg_le = rtl838x_set_port_reg, + .get_port_reg_le = rtl838x_get_port_reg, + .stat_port_rst = RTL838X_STAT_PORT_RST, + .stat_rst = RTL838X_STAT_RST, + .stat_port_std_mib = rtl838x_stat_port_std_mib, + .port_iso_ctrl = rtl838x_port_iso_ctrl, + .l2_ctrl_0 = RTL838X_L2_CTRL_0, + .l2_ctrl_1 = RTL838X_L2_CTRL_1, + .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT, + .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL, + .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl838x_tbl_access_data_0, + .isr_glb_src = RTL838X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL838X_IMR_GLB, + .vlan_tables_read = rtl838x_vlan_tables_read, + .vlan_set_tagged = rtl838x_vlan_set_tagged, + .vlan_set_untagged = rtl838x_vlan_set_untagged, + .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl, + .mac_port_ctrl = rtl838x_mac_port_ctrl, + .l2_port_new_salrn = rtl838x_l2_port_new_salrn, + .l2_port_new_sa_fwd = rtl838x_l2_port_new_sa_fwd, + .mir_ctrl = rtl838x_mir_ctrl, + .mir_dpm = rtl838x_mir_dpm, + .mir_spm = rtl838x_mir_spm, + .mac_link_sts = RTL838X_MAC_LINK_STS, + .mac_link_dup_sts = RTL838X_MAC_LINK_DUP_STS, + .mac_link_spd_sts = rtl838x_mac_link_spd_sts, + .mac_rx_pause_sts = RTL838X_MAC_RX_PAUSE_STS, + .mac_tx_pause_sts = RTL838X_MAC_TX_PAUSE_STS, + .read_l2_entry_using_hash = rtl838x_read_l2_entry_using_hash, + .read_cam = rtl838x_read_cam, + .vlan_profile = rtl838x_vlan_profile, + .vlan_port_egr_filter = rtl838x_vlan_port_egr_filter, + .vlan_port_igr_filter = rtl838x_vlan_port_igr_filter, + .vlan_port_pb = rtl838x_vlan_port_pb, + .vlan_port_tag_sts_ctrl = rtl838x_vlan_port_tag_sts_ctrl, +}; + +irqreturn_t rtl838x_switch_irq(int irq, void *dev_id) +{ + struct dsa_switch *ds = dev_id; + u32 status = sw_r32(RTL838X_ISR_GLB_SRC); + u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG); + u32 link; + int i; + + /* Clear status */ + sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG); + pr_debug("RTL8380 Link change: status: %x, ports %x\n", status, ports); + + for (i = 0; i < 28; i++) { + if (ports & BIT(i)) { + link = sw_r32(RTL838X_MAC_LINK_STS); + if (link & BIT(i)) + dsa_port_phylink_mac_change(ds, i, true); + else + dsa_port_phylink_mac_change(ds, i, false); + } + } + return IRQ_HANDLED; +} + +int rtl838x_smi_wait_op(int timeout) +{ + do { + timeout--; + udelay(10); + } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0)); + if (timeout <= 0) + return -1; + return 0; +} + +/* + * Reads a register in a page from the PHY + */ +int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + u32 v; + u32 park_page; + + if (port > 31) { + *val = 0xffff; + return 0; + } + + if (page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2); + v = reg << 20 | page << 3; + sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1); + sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +/* + * Write to a register in a page of the PHY + */ +int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + u32 v; + u32 park_page; + + val &= 0xffff; + if (port > 31 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + sw_w32(BIT(port), RTL838X_SMI_ACCESS_PHY_CTRL_0); + mdelay(10); + + sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2); + + park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2); + v = reg << 20 | page << 3 | 0x4; + sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1); + sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1); + + if (rtl838x_smi_wait_op(10000)) + goto timeout; + + mutex_unlock(&smi_lock); + return 0; + +timeout: + mutex_unlock(&smi_lock); + return -ETIMEDOUT; +} + +void rtl8380_get_version(struct rtl838x_switch_priv *priv) +{ + u32 rw_save, info_save; + u32 info; + + rw_save = sw_r32(RTL838X_INT_RW_CTRL); + sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL); + + info_save = sw_r32(RTL838X_CHIP_INFO); + sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO); + + info = sw_r32(RTL838X_CHIP_INFO); + sw_w32(info_save, RTL838X_CHIP_INFO); + sw_w32(rw_save, RTL838X_INT_RW_CTRL); + + if ((info & 0xFFFF) == 0x6275) { + if (((info >> 16) & 0x1F) == 0x1) + priv->version = RTL8380_VERSION_A; + else if (((info >> 16) & 0x1F) == 0x2) + priv->version = RTL8380_VERSION_B; + else + priv->version = RTL8380_VERSION_B; + } else { + priv->version = '-'; + } +} + +/* + * Applies the same hash algorithm as the one used currently by the ASIC + */ +u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 h1, h2, h3, h; + + if (sw_r32(priv->r->l2_ctrl_0) & 1) { + h1 = (seed >> 11) & 0x7ff; + h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f); + + h2 = (seed >> 33) & 0x7ff; + h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f); + + h3 = (seed >> 44) & 0x7ff; + h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf); + + h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff); + h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff); + } else { + h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff) + ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff) + ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff); + } + + return h; +} + +void rtl838x_vlan_profile_dump(int index) +{ + u32 profile; + + if (index < 0 || index > 7) + return; + + profile = sw_r32(RTL838X_VLAN_PROFILE(index)); + + pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \ + IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x", + index, profile & 1, (profile >> 1) & 0x1ff, (profile >> 10) & 0x1ff, + (profile >> 19) & 0x1ff); +} diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h new file mode 100644 index 0000000000..1ebb4dff72 --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h @@ -0,0 +1,293 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _RTL838X_H +#define _RTL838X_H + +#include <net/dsa.h> + +/* + * Register definition + */ +#define RTL838X_CPU_PORT 28 +#define RTL839X_CPU_PORT 52 + +#define RTL838X_MAC_PORT_CTRL(port) (0xd560 + (((port) << 7))) +#define RTL839X_MAC_PORT_CTRL(port) (0x8004 + (((port) << 7))) +#define RTL838X_RST_GLB_CTRL_0 (0x003c) +#define RTL838X_MAC_FORCE_MODE_CTRL (0xa104) +#define RTL839X_MAC_FORCE_MODE_CTRL (0x02bc) + +#define RTL838X_DMY_REG31 (0x3b28) +#define RTL838X_SDS_MODE_SEL (0x0028) +#define RTL838X_SDS_CFG_REG (0x0034) +#define RTL838X_INT_MODE_CTRL (0x005c) +#define RTL838X_CHIP_INFO (0x00d8) +#define RTL839X_CHIP_INFO (0x0ff4) +#define RTL838X_SDS4_REG28 (0xef80) +#define RTL838X_SDS4_DUMMY0 (0xef8c) +#define RTL838X_SDS5_EXT_REG6 (0xf18c) +#define RTL838X_PORT_ISO_CTRL(port) (0x4100 + ((port) << 2)) +#define RTL839X_PORT_ISO_CTRL(port) (0x1400 + ((port) << 3)) +#define RTL8380_SDS4_FIB_REG0 (0xF800) +#define RTL838X_STAT_PORT_STD_MIB (0x1200) +#define RTL839X_STAT_PORT_STD_MIB (0xC000) +#define RTL838X_STAT_RST (0x3100) +#define RTL839X_STAT_RST (0xF504) +#define RTL838X_STAT_PORT_RST (0x3104) +#define RTL839X_STAT_PORT_RST (0xF508) +#define RTL838X_STAT_CTRL (0x3108) +#define RTL839X_STAT_CTRL (0x04cc) + +/* Registers of the internal Serdes of the 8390 */ +#define RTL8390_SDS0_1_XSG0 (0xA000) +#define RTL8390_SDS0_1_XSG1 (0xA100) +#define RTL839X_SDS12_13_XSG0 (0xB800) +#define RTL839X_SDS12_13_XSG1 (0xB900) +#define RTL839X_SDS12_13_PWR0 (0xb880) +#define RTL839X_SDS12_13_PWR1 (0xb980) + +/* Registers of the internal Serdes of the 8380 */ +#define MAPLE_SDS4_REG0r RTL838X_SDS4_REG28 +#define MAPLE_SDS5_REG0r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_REG3r RTL838X_SDS4_DUMMY0 +#define MAPLE_SDS5_REG3r (RTL838X_SDS4_REG28 + 0x100) +#define MAPLE_SDS4_FIB_REG0r (RTL838X_SDS4_REG28 + 0x880) +#define MAPLE_SDS5_FIB_REG0r (RTL838X_SDS4_REG28 + 0x980) + +/* VLAN registers */ +#define RTL838X_VLAN_PROFILE(idx) (0x3A88 + ((idx) << 2)) +#define RTL838X_VLAN_PORT_EGR_FLTR (0x3A84) +#define RTL838X_VLAN_PORT_PB_VLAN(port) (0x3C00 + ((port) << 2)) +#define RTL838X_VLAN_PORT_IGR_FLTR(port) (0x3A7C + (((port >> 4) << 2))) +#define RTL838X_VLAN_PORT_IGR_FLTR_0 (0x3A7C) +#define RTL838X_VLAN_PORT_IGR_FLTR_1 (0x3A7C + 4) +#define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) (0xA530 + (((port) << 2))) +#define RTL839X_VLAN_PROFILE(idx) (0x25C0 + (((idx) << 3))) +#define RTL839X_VLAN_CTRL (0x26D4) +#define RTL839X_VLAN_PORT_PB_VLAN(port) (0x26D8 + (((port) << 2))) +#define RTL839X_VLAN_PORT_IGR_FLTR(port) (0x27B4 + (((port >> 4) << 2))) +#define RTL839X_VLAN_PORT_EGR_FLTR(port) (0x27C4 + (((port >> 5) << 2))) +#define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) (0x6828 + (((port) << 2))) + +/* Table 0/1 access registers */ +#define RTL838X_TBL_ACCESS_CTRL_0 (0x6914) +#define RTL838X_TBL_ACCESS_DATA_0(idx) (0x6918 + ((idx) << 2)) +#define RTL838X_TBL_ACCESS_CTRL_1 (0xA4C8) +#define RTL838X_TBL_ACCESS_DATA_1(idx) (0xA4CC + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_CTRL_0 (0x1190) +#define RTL839X_TBL_ACCESS_DATA_0(idx) (0x1194 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_CTRL_1 (0x6b80) +#define RTL839X_TBL_ACCESS_DATA_1(idx) (0x6b84 + ((idx) << 2)) + +/* MAC handling */ +#define RTL838X_MAC_LINK_STS (0xa188) +#define RTL839X_MAC_LINK_STS (0x0390) +#define RTL838X_MAC_LINK_SPD_STS(port) (0xa190 + (((port >> 4) << 2))) +#define RTL839X_MAC_LINK_SPD_STS(port) (0x03a0 + (((port >> 4) << 2))) +#define RTL838X_MAC_LINK_DUP_STS (0xa19c) +#define RTL839X_MAC_LINK_DUP_STS (0x03b0) +#define RTL838X_MAC_TX_PAUSE_STS (0xa1a0) +#define RTL839X_MAC_TX_PAUSE_STS (0x03b8) +#define RTL838X_MAC_RX_PAUSE_STS (0xa1a4) +#define RTL839X_MAC_RX_PAUSE_STS (0x03c0) +#define RTL838X_EEE_TX_TIMER_GIGA_CTRL (0xaa04) +#define RTL838X_EEE_TX_TIMER_GELITE_CTRL (0xaa08) + +#define RTL838X_DMA_IF_CTRL (0x9f58) + +/* MAC link state bits */ +#define FORCE_EN (1 << 0) +#define FORCE_LINK_EN (1 << 1) +#define NWAY_EN (1 << 2) +#define DUPLX_MODE (1 << 3) +#define TX_PAUSE_EN (1 << 6) +#define RX_PAUSE_EN (1 << 7) + +/* EEE */ +#define RTL838X_MAC_EEE_ABLTY (0xa1a8) +#define RTL838X_EEE_PORT_TX_EN (0x014c) +#define RTL838X_EEE_PORT_RX_EN (0x0150) +#define RTL838X_EEE_CLK_STOP_CTRL (0x0148) + +/* L2 functionality */ +#define RTL838X_L2_CTRL_0 (0x3200) +#define RTL839X_L2_CTRL_0 (0x3800) +#define RTL838X_L2_CTRL_1 (0x3204) +#define RTL839X_L2_CTRL_1 (0x3804) +#define RTL838X_L2_PORT_AGING_OUT (0x3358) +#define RTL839X_L2_PORT_AGING_OUT (0x3b74) +#define RTL838X_TBL_ACCESS_L2_CTRL (0x6900) +#define RTL839X_TBL_ACCESS_L2_CTRL (0x1180) +#define RTL838X_TBL_ACCESS_L2_DATA(idx) (0x6908 + ((idx) << 2)) +#define RTL839X_TBL_ACCESS_L2_DATA(idx) (0x1184 + ((idx) << 2)) +#define RTL838X_L2_TBL_FLUSH_CTRL (0x3370) +#define RTL839X_L2_TBL_FLUSH_CTRL (0x3ba0) +#define RTL838X_L2_PORT_NEW_SALRN(p) (0x328c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_NEW_SALRN(p) (0x38F0 + (((p >> 4) << 2))) +#define RTL838X_L2_PORT_NEW_SA_FWD(p) (0x3294 + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_NEW_SA_FWD(p) (0x3900 + (((p >> 4) << 2))) +#define RTL838X_L2_PORT_SALRN(p) (0x328c + (((p >> 4) << 2))) +#define RTL839X_L2_PORT_SALRN(p) (0x38F0 + (((p >> 4) << 2))) + +/* Port Mirroring */ +#define RTL838X_MIR_CTRL(grp) (0x5D00 + (((grp) << 2))) +#define RTL838X_MIR_DPM_CTRL(grp) (0x5D20 + (((grp) << 2))) +#define RTL838X_MIR_SPM_CTRL(grp) (0x5D10 + (((grp) << 2))) +#define RTL839X_MIR_CTRL(grp) (0x2500 + (((grp) << 2))) +#define RTL839X_MIR_DPM_CTRL(grp) (0x2530 + (((grp) << 2))) +#define RTL839X_MIR_SPM_CTRL(grp) (0x2510 + (((grp) << 2))) + +/* Storm control */ +#define RTL838X_STORM_CTRL (0x4700) +#define RTL839X_STORM_CTRL (0x1800) +#define RTL838X_STORM_CTRL_LB_CTRL(p) (0x4884 + (((p) << 2))) +#define RTL838X_STORM_CTRL_BURST_PPS_0 (0x4874) +#define RTL838X_STORM_CTRL_BURST_PPS_1 (0x4878) +#define RTL838X_STORM_CTRL_BURST_0 (0x487c) +#define RTL838X_STORM_CTRL_BURST_1 (0x4880) +#define RTL838X_SCHED_CTRL (0xB980) +#define RTL838X_SCHED_LB_TICK_TKN_CTRL_0 (0xAD58) +#define RTL838X_SCHED_LB_TICK_TKN_CTRL_1 (0xAD5C) +#define RTL839X_SCHED_LB_TICK_TKN_CTRL_0 (0x1804) +#define RTL839X_SCHED_LB_TICK_TKN_CTRL_1 (0x1808) +#define RTL838X_SCHED_LB_THR (0xB984) +#define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C) +#define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710) +#define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714) +#define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p) (0x180c + (((p >> 5) << 2))) +#define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p) (0x1814 + (((p >> 5) << 2))) +#define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p) (0x181c + (((p >> 5) << 2))) +#define RTL838X_STORM_CTRL_PORT_UC(p) (0x4718 + (((p) << 2))) +#define RTL838X_STORM_CTRL_PORT_MC(p) (0x478c + (((p) << 2))) +#define RTL838X_STORM_CTRL_PORT_BC(p) (0x4800 + (((p) << 2))) + +/* Attack prevention */ +#define RTL838X_ATK_PRVNT_PORT_EN (0x5B00) +#define RTL838X_ATK_PRVNT_CTRL (0x5B04) +#define RTL838X_ATK_PRVNT_ACT (0x5B08) +#define RTL838X_ATK_PRVNT_STS (0x5B1C) + +enum phy_type { + PHY_NONE = 0, + PHY_RTL838X_SDS = 1, + PHY_RTL8218B_INT = 2, + PHY_RTL8218B_EXT = 3, + PHY_RTL8214FC = 4, + PHY_RTL839X_SDS = 5, +}; + +struct rtl838x_port { + bool enable; + u64 pm; + u16 pvid; + bool eee_enabled; + enum phy_type phy; + const struct dsa_port *dp; +}; + +struct rtl838x_vlan_info { + u64 untagged_ports; + u64 tagged_ports; + u8 profile_id; + bool hash_mc_fid; + bool hash_uc_fid; + u8 fid; +}; + +enum l2_entry_type { + L2_INVALID = 0, + L2_UNICAST = 1, + L2_MULTICAST = 2, + IP4_MULTICAST = 3, + IP6_MULTICAST = 4, +}; + +struct rtl838x_l2_entry { + u8 mac[6]; + u16 vid; + u16 rvid; + u8 port; + bool valid; + enum l2_entry_type type; + bool is_static; + bool is_ip_mc; + bool is_ipv6_mc; + bool block_da; + bool block_sa; + bool suspended; + bool next_hop; + int age; + u16 mc_portmask_index; +}; + +struct rtl838x_switch_priv; + +struct rtl838x_reg { + void (*mask_port_reg_be)(u64 clear, u64 set, int reg); + void (*set_port_reg_be)(u64 set, int reg); + u64 (*get_port_reg_be)(int reg); + void (*mask_port_reg_le)(u64 clear, u64 set, int reg); + void (*set_port_reg_le)(u64 set, int reg); + u64 (*get_port_reg_le)(int reg); + int stat_port_rst; + int stat_rst; + int (*stat_port_std_mib)(int p); + int (*port_iso_ctrl)(int p); + int l2_ctrl_0; + int l2_ctrl_1; + int l2_port_aging_out; + int smi_poll_ctrl; + int l2_tbl_flush_ctrl; + void (*exec_tbl0_cmd)(u32 cmd); + void (*exec_tbl1_cmd)(u32 cmd); + int (*tbl_access_data_0)(int i); + int isr_glb_src; + int isr_port_link_sts_chg; + int imr_port_link_sts_chg; + int imr_glb; + void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info); + void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info); + void (*vlan_set_untagged)(u32 vlan, u64 portmask); + int (*mac_force_mode_ctrl)(int port); + int (*mac_port_ctrl)(int port); + int (*l2_port_new_salrn)(int port); + int (*l2_port_new_sa_fwd)(int port); + int (*mir_ctrl)(int group); + int (*mir_dpm)(int group); + int (*mir_spm)(int group); + int mac_link_sts; + int mac_link_dup_sts; + int (*mac_link_spd_sts)(int port); + int mac_rx_pause_sts; + int mac_tx_pause_sts; + u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e); + u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e); + int (*vlan_profile)(int profile); + int (*vlan_port_egr_filter)(int port); + int (*vlan_port_igr_filter)(int port); + int (*vlan_port_pb)(int port); + int (*vlan_port_tag_sts_ctrl)(int port); +}; + +struct rtl838x_switch_priv { + /* Switch operation */ + struct dsa_switch *ds; + struct device *dev; + u16 id; + u16 family_id; + char version; + struct rtl838x_port ports[54]; /* TODO: correct size! */ + struct mutex reg_mutex; + int link_state_irq; + int mirror_group_ports[4]; + struct mii_bus *mii_bus; + const struct rtl838x_reg *r; + u8 cpu_port; + u8 port_mask; + u32 fib_entries; + struct dentry *dbgfs_dir; +}; + +void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv); + +#endif /* _RTL838X_H */ diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c new file mode 100644 index 0000000000..8dd123f609 --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl839x.c @@ -0,0 +1,514 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/mach-rtl838x/mach-rtl83xx.h> +#include "rtl83xx.h" + +extern struct mutex smi_lock; + + +static inline void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg); + sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4); +} + +static inline u64 rtl839x_get_port_reg_be(int reg) +{ + u64 v = sw_r32(reg); + + v <<= 32; + v |= sw_r32(reg + 4); + return v; +} + +static inline void rtl839x_set_port_reg_be(u64 set, int reg) +{ + sw_w32(set >> 32, reg); + sw_w32(set & 0xffffffff, reg + 4); +} + +static inline void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg) +{ + sw_w32_mask((u32)clear, (u32)set, reg); + sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4); +} + +static inline void rtl839x_set_port_reg_le(u64 set, int reg) +{ + sw_w32(set, reg); + sw_w32(set >> 32, reg + 4); +} + +static inline u64 rtl839x_get_port_reg_le(int reg) +{ + u64 v = sw_r32(reg + 4); + + v <<= 32; + v |= sw_r32(reg); + return v; +} + +static inline int rtl839x_stat_port_std_mib(int p) +{ + return RTL839X_STAT_PORT_STD_MIB + (p << 8); +} + +static inline int rtl839x_port_iso_ctrl(int p) +{ + return RTL839X_PORT_ISO_CTRL(p); +} + +static inline void rtl839x_exec_tbl0_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16)); +} + +static inline void rtl839x_exec_tbl1_cmd(u32 cmd) +{ + sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1); + do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16)); +} + +static inline int rtl839x_tbl_access_data_0(int i) +{ + return RTL839X_TBL_ACCESS_DATA_0(i); +} + +static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 cmd; + u64 v; + u32 u, w; + + cmd = BIT(16) /* Execute cmd */ + | 0 << 15 /* Read */ + | 0 << 12 /* Table type 0b000 */ + | (vlan & 0xfff); + rtl839x_exec_tbl0_cmd(cmd); + + v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0)); + v <<= 32; + u = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)); + v |= u; + info->tagged_ports = v >> 11; + + w = sw_r32(RTL838X_TBL_ACCESS_DATA_0(2)); + + info->profile_id = w >> 30 | ((u & 1) << 2); + info->hash_mc_fid = !!(u & 2); + info->hash_uc_fid = !!(u & 4); + info->fid = (u >> 3) & 0xff; + + cmd = BIT(16) /* Execute cmd */ + | 0 << 15 /* Read */ + | 0 << 12 /* Table type 0b000 */ + | (vlan & 0xfff); + rtl839x_exec_tbl1_cmd(cmd); + v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0)); + v <<= 32; + v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1)); + info->untagged_ports = v >> 11; +} + +static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info) +{ + u32 cmd = BIT(16) /* Execute cmd */ + | BIT(15) /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + u32 w; + u64 v = info->tagged_ports << 11; + + v |= info->profile_id >> 2; + v |= info->hash_mc_fid ? 2 : 0; + v |= info->hash_uc_fid ? 4 : 0; + v |= ((u32)info->fid) << 3; + rtl839x_set_port_reg_be(v, RTL838X_TBL_ACCESS_DATA_0(0)); + + w = info->profile_id; + sw_w32(w << 30, RTL838X_TBL_ACCESS_DATA_0(2)); + rtl839x_exec_tbl0_cmd(cmd); +} + +static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask) +{ + u32 cmd = BIT(16) /* Execute cmd */ + | BIT(15) /* Write */ + | 0 << 12 /* Table type 0b00 */ + | (vlan & 0xfff); + rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0)); + rtl839x_exec_tbl1_cmd(cmd); +} + +static inline int rtl839x_mac_force_mode_ctrl(int p) +{ + return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2); +} + +static inline int rtl839x_mac_port_ctrl(int p) +{ + return RTL839X_MAC_PORT_CTRL(p); +} + +static inline int rtl839x_l2_port_new_salrn(int p) +{ + return RTL839X_L2_PORT_NEW_SALRN(p); +} + +static inline int rtl839x_l2_port_new_sa_fwd(int p) +{ + return RTL839X_L2_PORT_NEW_SA_FWD(p); +} + +static inline int rtl839x_mir_ctrl(int group) +{ + return RTL839X_MIR_CTRL(group); +} + +static inline int rtl839x_mir_dpm(int group) +{ + return RTL839X_MIR_DPM_CTRL(group); +} + +static inline int rtl839x_mir_spm(int group) +{ + return RTL839X_MIR_SPM_CTRL(group); +} + +static inline int rtl839x_mac_link_spd_sts(int p) +{ + return RTL839X_MAC_LINK_SPD_STS(p); +} + +static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e) +{ + u64 entry; + u32 r[3]; + + /* Search in SRAM, with hash and at position in hash bucket (0-3) */ + u32 idx = (0 << 14) | (hash << 2) | position; + + u32 cmd = BIT(17) /* Execute cmd */ + | 0 << 16 /* Read */ + | 0 << 14 /* Table type 0b00 */ + | (idx & 0x3fff); + + sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17)); + r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0)); + r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1)); + r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2)); + + /* Table contains different entry types, we need to identify the right one: + * Check for MC entries, first + */ + e->is_ip_mc = !!(r[2] & BIT(31)); + e->is_ipv6_mc = !!(r[2] & BIT(30)); + e->type = L2_INVALID; + if (!e->is_ip_mc) { + e->mac[0] = (r[0] >> 12); + e->mac[1] = (r[0] >> 4); + e->mac[2] = ((r[1] >> 28) | (r[0] << 4)); + e->mac[3] = (r[1] >> 20); + e->mac[4] = (r[1] >> 12); + e->mac[5] = (r[1] >> 4); + + /* Is it a unicast entry? check multicast bit */ + if (!(e->mac[0] & 1)) { + e->is_static = !!((r[2] >> 18) & 1); + e->vid = (r[2] >> 4) & 0xfff; + e->rvid = (r[0] >> 20) & 0xfff; + e->port = (r[2] >> 24) & 0x3f; + e->block_da = !!(r[2] & BIT(19)); + e->block_sa = !!(r[2] & BIT(20)); + e->suspended = !!(r[2] & BIT(17)); + e->next_hop = !!(r[2] & BIT(16)); + if (e->next_hop) + pr_debug("Found next hop entry, need to read data\n"); + e->age = (r[2] >> 21) & 3; + e->valid = true; + if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */ + e->valid = false; + else + e->type = L2_UNICAST; + } else { + e->valid = true; + e->type = L2_MULTICAST; + e->mc_portmask_index = (r[2]>>6) & 0xfff; + } + } + if (e->is_ip_mc) { + e->valid = true; + e->type = IP4_MULTICAST; + } + if (e->is_ipv6_mc) { + e->valid = true; + e->type = IP6_MULTICAST; + } + + entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff); + return entry; +} + +static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e) +{ + u64 entry; + u32 r[3]; + + u32 cmd = BIT(17) /* Execute cmd */ + | 0 << 16 /* Read */ + | BIT(14) /* Table type 0b01 */ + | (idx & 0x3f); + sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL); + do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17)); + r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0)); + r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1)); + r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2)); + + e->mac[0] = (r[0] >> 12); + e->mac[1] = (r[0] >> 4); + e->mac[2] = ((r[1] >> 28) | (r[0] << 4)); + e->mac[3] = (r[1] >> 20); + e->mac[4] = (r[1] >> 12); + e->mac[5] = (r[1] >> 4); + e->is_static = !!((r[2] >> 18) & 1); + e->vid = (r[2] >> 4) & 0xfff; + e->rvid = (r[0] >> 20) & 0xfff; + e->port = (r[2] >> 24) & 0x3f; + + e->valid = true; + if (!(r[2] & 0x10fd0000)) /* Check for invalid entry */ + e->valid = false; + + if (e->valid) + pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]); + + entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff); + return entry; +} + +static inline int rtl839x_vlan_profile(int profile) +{ + return RTL839X_VLAN_PROFILE(profile); +} + +static inline int rtl839x_vlan_port_egr_filter(int port) +{ + return RTL839X_VLAN_PORT_EGR_FLTR(port); +} + +static inline int rtl839x_vlan_port_igr_filter(int port) +{ + return RTL839X_VLAN_PORT_IGR_FLTR(port); +} + +static inline int rtl839x_vlan_port_pb(int port) +{ + return RTL839X_VLAN_PORT_PB_VLAN(port); +} + +static inline int rtl839x_vlan_port_tag_sts_ctrl(int port) +{ + return RTL839X_VLAN_PORT_TAG_STS_CTRL(port); +} + +const struct rtl838x_reg rtl839x_reg = { + .mask_port_reg_be = rtl839x_mask_port_reg_be, + .set_port_reg_be = rtl839x_set_port_reg_be, + .get_port_reg_be = rtl839x_get_port_reg_be, + .mask_port_reg_le = rtl839x_mask_port_reg_le, + .set_port_reg_le = rtl839x_set_port_reg_le, + .get_port_reg_le = rtl839x_get_port_reg_le, + .stat_port_rst = RTL839X_STAT_PORT_RST, + .stat_rst = RTL839X_STAT_RST, + .stat_port_std_mib = rtl839x_stat_port_std_mib, + .port_iso_ctrl = rtl839x_port_iso_ctrl, + .l2_ctrl_0 = RTL839X_L2_CTRL_0, + .l2_ctrl_1 = RTL839X_L2_CTRL_1, + .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT, + .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL, + .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL, + .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd, + .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd, + .tbl_access_data_0 = rtl839x_tbl_access_data_0, + .isr_glb_src = RTL839X_ISR_GLB_SRC, + .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG, + .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG, + .imr_glb = RTL839X_IMR_GLB, + .vlan_tables_read = rtl839x_vlan_tables_read, + .vlan_set_tagged = rtl839x_vlan_set_tagged, + .vlan_set_untagged = rtl839x_vlan_set_untagged, + .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl, + .mac_port_ctrl = rtl839x_mac_port_ctrl, + .l2_port_new_salrn = rtl839x_l2_port_new_salrn, + .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd, + .mir_ctrl = rtl839x_mir_ctrl, + .mir_dpm = rtl839x_mir_dpm, + .mir_spm = rtl839x_mir_spm, + .mac_link_sts = RTL839X_MAC_LINK_STS, + .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS, + .mac_link_spd_sts = rtl839x_mac_link_spd_sts, + .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS, + .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS, + .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash, + .read_cam = rtl839x_read_cam, + .vlan_profile = rtl839x_vlan_profile, + .vlan_port_egr_filter = rtl839x_vlan_port_egr_filter, + .vlan_port_igr_filter = rtl839x_vlan_port_igr_filter, + .vlan_port_pb = rtl839x_vlan_port_pb, + .vlan_port_tag_sts_ctrl = rtl839x_vlan_port_tag_sts_ctrl, +}; + +irqreturn_t rtl839x_switch_irq(int irq, void *dev_id) +{ + struct dsa_switch *ds = dev_id; + u32 status = sw_r32(RTL839X_ISR_GLB_SRC); + u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG); + u64 link; + int i; + + /* Clear status */ + rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG); + pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports); + + for (i = 0; i < 52; i++) { + if (ports & (1ULL << i)) { + link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS); + if (link & (1ULL << i)) + dsa_port_phylink_mac_change(ds, i, true); + else + dsa_port_phylink_mac_change(ds, i, false); + } + } + return IRQ_HANDLED; +} + +// TODO: unused +int rtl8390_sds_power(int mac, int val) +{ + u32 offset = (mac == 48) ? 0x0 : 0x100; + u32 mode = val ? 0 : 1; + + pr_debug("In %s: mac %d, set %d\n", __func__, mac, val); + + if ((mac != 48) && (mac != 49)) { + pr_err("%s: not an SFP port: %d\n", __func__, mac); + return -1; + } + + // Set bit 1003. 1000 starts at 7c + sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset); + + return 0; +} + +int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val) +{ + u32 v; + + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + + sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL); + v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + sw_w32(0x1ff, RTL839X_PHYREG_CTRL); + + v |= 1; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + do { + } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + + *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff; + + mutex_unlock(&smi_lock); + return 0; +} + +int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val) +{ + u32 v; + int err = 0; + + val &= 0xffff; + if (port > 63 || page > 4095 || reg > 31) + return -ENOTSUPP; + + mutex_lock(&smi_lock); + /* Clear both port registers */ + sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0)); + sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4); + sw_w32_mask(0, BIT(port), RTL839X_PHYREG_PORT_CTRL(port)); + + sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL); + + v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23; + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + sw_w32(0x1ff, RTL839X_PHYREG_CTRL); + + v |= BIT(3) | 1; /* Write operation and execute */ + sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL); + + do { + } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1); + + if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2) + err = -EIO; + + mutex_unlock(&smi_lock); + return err; +} + +void rtl8390_get_version(struct rtl838x_switch_priv *priv) +{ + u32 info; + + sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO); + info = sw_r32(RTL839X_CHIP_INFO); + pr_debug("Chip-Info: %x\n", info); + priv->version = RTL8390_VERSION_A; +} + +u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed) +{ + u32 h1, h2, h; + + if (sw_r32(priv->r->l2_ctrl_0) & 1) { + h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) + ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) + ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f)); + h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) + ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) + ^ (seed & 0x3f)); + h = (h1 << 6) | h2; + } else { + h = (seed >> 60) + ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f)) + ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff) + ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff); + } + + return h; +} + +void rtl839x_vlan_profile_dump(int index) +{ + u32 profile, profile1; + + if (index < 0 || index > 7) + return; + + profile1 = sw_r32(RTL839X_VLAN_PROFILE(index) + 4); + profile = sw_r32(RTL839X_VLAN_PROFILE(index)); + + pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \ + IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x", + index, profile & 1, (profile >> 1) & 0xfff, (profile >> 13) & 0xfff, + (profile1) & 0xfff); +} diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h new file mode 100644 index 0000000000..3953512525 --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl83xx.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _NET_DSA_RTL83XX_H +#define _NET_DSA_RTL83XX_H + +#include <net/dsa.h> +#include "rtl838x.h" + + +#define RTL8380_VERSION_A 'A' +#define RTL8390_VERSION_A 'A' +#define RTL8380_VERSION_B 'B' + +struct fdb_update_work { + struct work_struct work; + struct net_device *ndev; + u64 macs[]; +}; + +#define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name} +struct rtl83xx_mib_desc { + unsigned int size; + unsigned int offset; + const char *name; +}; + +void __init rtl83xx_storm_control_init(struct rtl838x_switch_priv *priv); + +/* RTL838x-specific */ +u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed); +irqreturn_t rtl838x_switch_irq(int irq, void *dev_id); +void rtl8380_get_version(struct rtl838x_switch_priv *priv); +void rtl838x_vlan_profile_dump(int index); +int rtl83xx_dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg); + +/* RTL839x-specific */ +u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed); +irqreturn_t rtl839x_switch_irq(int irq, void *dev_id); +void rtl8390_get_version(struct rtl838x_switch_priv *priv); +void rtl839x_vlan_profile_dump(int index); +int rtl83xx_dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val); + +#endif /* _NET_DSA_RTL83XX_H */ + diff --git a/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/storm.c b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/storm.c new file mode 100644 index 0000000000..de0af033f3 --- /dev/null +++ b/target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/storm.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/mach-rtl838x/mach-rtl83xx.h> +#include "rtl83xx.h" + + +static void rtl83xx_storm_enable(struct rtl838x_switch_priv *priv, int port, bool enable) +{ + // Enable Storm control for that port for UC, MC, and BC + if (enable) + sw_w32(0x7, RTL838X_STORM_CTRL_LB_CTRL(port)); + else + sw_w32(0x0, RTL838X_STORM_CTRL_LB_CTRL(port)); +} + +void __init rtl83xx_storm_control_init(struct rtl838x_switch_priv *priv) +{ + int i; + + pr_debug("Enabling Storm control\n"); + // TICK_PERIOD_PPS + if (priv->id == 0x8380) + sw_w32_mask(0x3ff << 20, 434 << 20, RTL838X_SCHED_LB_TICK_TKN_CTRL_0); + + // Set burst rate + sw_w32(0x00008000, RTL838X_STORM_CTRL_BURST_0); // UC + sw_w32(0x80008000, RTL838X_STORM_CTRL_BURST_1); // MC and BC + + // Set burst Packets per Second to 32 + sw_w32(0x00000020, RTL838X_STORM_CTRL_BURST_PPS_0); // UC + sw_w32(0x00200020, RTL838X_STORM_CTRL_BURST_PPS_1); // MC and BC + + // Include IFG in storm control + sw_w32_mask(0, BIT(6), RTL838X_STORM_CTRL); + // Rate control is based on bytes/s (0 = packets) + sw_w32_mask(0, BIT(5), RTL838X_STORM_CTRL); + // Bandwidth control includes preamble and IFG (10 Bytes) + sw_w32_mask(0, 1, RTL838X_SCHED_CTRL); + + // On SoCs except RTL8382M, set burst size of port egress + if (priv->id != 0x8382) + sw_w32_mask(0xffff, 0x800, RTL838X_SCHED_LB_THR); + + /* Enable storm control on all ports with a PHY and limit rates, + * for UC and MC for both known and unknown addresses */ + for (i = 0; i < priv->cpu_port; i++) { + if (priv->ports[i].phy) { + sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_UC(i)); + sw_w32(BIT(18) | 0x8000, RTL838X_STORM_CTRL_PORT_MC(i)); + sw_w32(0x000, RTL838X_STORM_CTRL_PORT_BC(i)); + rtl83xx_storm_enable(priv, i, true); + } + } + + // Attack prevention, enable all attack prevention measures + //sw_w32(0x1ffff, RTL838X_ATK_PRVNT_CTRL); + /* Attack prevention, drop (bit = 0) problematic packets on all ports. + * Setting bit = 1 means: trap to CPU + */ + //sw_w32(0, RTL838X_ATK_PRVNT_ACT); + // Enable attack prevention on all ports + //sw_w32(0x0fffffff, RTL838X_ATK_PRVNT_PORT_EN); +} + |