diff options
Diffstat (limited to 'target/linux/rb532-2.6')
| -rw-r--r-- | target/linux/rb532-2.6/Makefile | 22 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/config | 1335 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/100-rb5xx_support.patch | 5606 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/110-korina_ethernet.patch | 1375 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/120-cf.patch | 990 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/130-custom_partitions.patch | 311 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/200-bridge_resource_hack.patch | 13 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/210-pci_fixes.patch | 46 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/220-serial_fix.patch | 18 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/230-dma_limit.patch | 13 | ||||
| -rw-r--r-- | target/linux/rb532-2.6/patches/240-via_rhine_performance.patch | 461 |
11 files changed, 10190 insertions, 0 deletions
diff --git a/target/linux/rb532-2.6/Makefile b/target/linux/rb532-2.6/Makefile new file mode 100644 index 0000000000..30fa1a85a1 --- /dev/null +++ b/target/linux/rb532-2.6/Makefile @@ -0,0 +1,22 @@ +# +# Copyright (C) 2006 OpenWrt.org +# +# This is free software, licensed under the GNU General Public License v2. +# See /LICENSE for more information. +# +include $(TOPDIR)/rules.mk + +LINUX_VERSION:=2.6.17 +LINUX_RELEASE:=1 +LINUX_KERNEL_MD5SUM:=37ddefe96625502161f075b9d907f21e + +include ./config +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/kernel-build.mk + +$(LINUX_DIR)/.patched: $(LINUX_DIR)/.unpacked + [ -d ../generic-$(KERNEL)/patches ] && $(PATCH) $(LINUX_DIR) ../generic-$(KERNEL)/patches + [ -d ./patches ] && $(PATCH) $(LINUX_DIR) ./patches + @$(CP) config $(LINUX_DIR)/.config + touch $@ + diff --git a/target/linux/rb532-2.6/config b/target/linux/rb532-2.6/config new file mode 100644 index 0000000000..eaa3771d11 --- /dev/null +++ b/target/linux/rb532-2.6/config @@ -0,0 +1,1335 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.17 +# Sun Jun 18 17:29:23 2006 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MIPS_EV64120 is not set +# CONFIG_MIPS_EV96100 is not set +# CONFIG_MIPS_IVR is not set +# CONFIG_MIPS_ITE8172 is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MIPS_ATLAS is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SEAD is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MOMENCO_JAGUAR_ATX is not set +# CONFIG_MOMENCO_OCELOT is not set +# CONFIG_MOMENCO_OCELOT_3 is not set +# CONFIG_MOMENCO_OCELOT_C is not set +# CONFIG_MOMENCO_OCELOT_G is not set +# CONFIG_MIPS_XXS1500 is not set +# CONFIG_PNX8550_V2PCI is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_DDB5074 is not set +# CONFIG_DDB5476 is not set +# CONFIG_DDB5477 is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_QEMU is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_PTSWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SNI_RM200_PCI is not set +# CONFIG_TOSHIBA_JMR3927 is not set +CONFIG_MIKROTIK_RB500=y +# CONFIG_TOSHIBA_RBTX4927 is not set +# CONFIG_TOSHIBA_RBTX4938 is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_MIPS_L1_CACHE_SHIFT=4 + +# +# CPU selection +# +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +# CONFIG_MIPS_MT is not set +# CONFIG_64BIT_PHYS_ADDR is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set + +# +# Code maturity level options +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +CONFIG_SYSCTL=y +# CONFIG_AUDIT is not set +# CONFIG_IKCONFIG is not set +# CONFIG_RELAY is not set +CONFIG_INITRAMFS_SOURCE="" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EMBEDDED=y +# CONFIG_KALLSYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +# CONFIG_ELF_CORE is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SHMEM=y +CONFIG_SLAB=y +# CONFIG_TINY_SHMEM is not set +CONFIG_BASE_SMALL=0 +# CONFIG_SLOB is not set + +# +# Loadable module support +# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_KMOD is not set + +# +# Block layer +# +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_LSF is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_MMU=y + +# +# PCCARD (PCMCIA/CardBus) support +# +CONFIG_PCCARD=m +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=m +# CONFIG_PCMCIA_LOAD_CIS is not set +# CONFIG_PCMCIA_IOCTL is not set +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +# CONFIG_YENTA is not set +# CONFIG_PD6729 is not set +# CONFIG_I82092 is not set + +# +# PCI Hotplug Support +# +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Networking +# +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_NETDEBUG is not set +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_FWMARK=y +CONFIG_IP_ROUTE_MULTIPATH=y +# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +# CONFIG_IP_PNP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +# CONFIG_NET_IPGRE_BROADCAST is not set +CONFIG_IPSEC_NAT_TRAVERSAL=y +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_TCP_CONG_ADVANCED=y + +# +# TCP congestion control +# +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CUBIC=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_VEGAS=y +CONFIG_TCP_CONG_SCALABLE=m + +# +# IP: Virtual Server Configuration +# +# CONFIG_IP_VS is not set +CONFIG_IPV6=m +# CONFIG_IPV6_PRIVACY is not set +CONFIG_IPV6_ROUTER_PREF=y +# CONFIG_IPV6_ROUTE_INFO is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +# CONFIG_IPV6_TUNNEL is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK is not set +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=y + +# +# IP: Netfilter Configuration +# +CONFIG_IP_NF_CONNTRACK=y +CONFIG_IP_NF_CT_ACCT=y +CONFIG_IP_NF_CONNTRACK_MARK=y +# CONFIG_IP_NF_CONNTRACK_EVENTS is not set +# CONFIG_IP_NF_CT_PROTO_SCTP is not set +CONFIG_IP_NF_FTP=y +CONFIG_IP_NF_IRC=y +# CONFIG_IP_NF_NETBIOS_NS is not set +CONFIG_IP_NF_TFTP=m +CONFIG_IP_NF_AMANDA=m +CONFIG_IP_NF_PPTP=m +CONFIG_IP_NF_H323=m +CONFIG_IP_NF_SIP=m +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_IPRANGE=m +CONFIG_IP_NF_MATCH_IPP2P=m +CONFIG_IP_NF_MATCH_TOS=m +CONFIG_IP_NF_MATCH_TIME=m +CONFIG_IP_NF_MATCH_RECENT=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_DSCP=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_MATCH_OWNER=m +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_HASHLIMIT is not set +CONFIG_IP_NF_MATCH_LAYER7=m +# CONFIG_IP_NF_MATCH_LAYER7_DEBUG is not set +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_IMQ=m +# CONFIG_IP_NF_TARGET_LOG is not set +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_TARGET_TCPMSS=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_NAT_NEEDED=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_IP_NF_TARGET_ROUTE=m +# CONFIG_IP_NF_TARGET_NETMAP is not set +# CONFIG_IP_NF_TARGET_SAME is not set +# CONFIG_IP_NF_NAT_SNMP_BASIC is not set +CONFIG_IP_NF_NAT_IRC=y +CONFIG_IP_NF_NAT_FTP=y +CONFIG_IP_NF_NAT_TFTP=m +CONFIG_IP_NF_NAT_AMANDA=m +CONFIG_IP_NF_NAT_PPTP=m +CONFIG_IP_NF_NAT_H323=m +CONFIG_IP_NF_NAT_SIP=m +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_TOS=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_DSCP=m +CONFIG_IP_NF_TARGET_TTL=m +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set +CONFIG_IP_NF_RAW=m +# CONFIG_IP_NF_ARPTABLES is not set +CONFIG_IP_NF_SET=m +CONFIG_IP_NF_SET_MAX=256 +CONFIG_IP_NF_SET_HASHSIZE=1024 +CONFIG_IP_NF_SET_IPMAP=m +CONFIG_IP_NF_SET_MACIPMAP=m +CONFIG_IP_NF_SET_PORTMAP=m +CONFIG_IP_NF_SET_IPHASH=m +CONFIG_IP_NF_SET_NETHASH=m +CONFIG_IP_NF_SET_IPTREE=m +CONFIG_IP_NF_MATCH_SET=m +CONFIG_IP_NF_TARGET_SET=m + +# +# IPv6: Netfilter Configuration (EXPERIMENTAL) +# +CONFIG_IP6_NF_QUEUE=m +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_HL is not set +CONFIG_IP6_NF_MATCH_OWNER=m +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_IMQ=m +# CONFIG_IP6_NF_TARGET_LOG is not set +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_ROUTE=m +CONFIG_IP6_NF_MANGLE=m +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_RAW is not set + +# +# Bridge: Netfilter Configuration +# +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_ULOG=m + +# +# DCCP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_DCCP is not set + +# +# SCTP Configuration (EXPERIMENTAL) +# +# CONFIG_IP_SCTP is not set + +# +# TIPC Configuration (EXPERIMENTAL) +# +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_BRIDGE=y +CONFIG_VLAN_8021Q=y +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_NET_DIVERT is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set + +# +# QoS and/or fair queueing +# +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_CLK_JIFFIES=y +# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set +# CONFIG_NET_SCH_CLK_CPU is not set + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFQ=m +CONFIG_NET_SCH_ESFQ=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_DSMARK=m +# CONFIG_NET_SCH_NETEM is not set +CONFIG_NET_SCH_INGRESS=m + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_ROUTE=y +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +# CONFIG_CLS_U32_PERF is not set +# CONFIG_CLS_U32_MARK is not set +CONFIG_NET_CLS_RSVP=m +CONFIG_NET_CLS_RSVP6=m +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_CLS_POLICE=y +# CONFIG_NET_CLS_IND is not set +CONFIG_NET_ESTIMATOR=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +CONFIG_AX25=m +# CONFIG_AX25_DAMA_SLAVE is not set +# CONFIG_NETROM is not set +# CONFIG_ROSE is not set + +# +# AX.25 network device drivers +# +CONFIG_MKISS=m +# CONFIG_6PACK is not set +# CONFIG_BPQETHER is not set +# CONFIG_BAYCOM_SER_FDX is not set +# CONFIG_BAYCOM_SER_HDX is not set +# CONFIG_YAM is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +CONFIG_IEEE80211=m +# CONFIG_IEEE80211_DEBUG is not set +CONFIG_IEEE80211_CRYPT_WEP=m +CONFIG_IEEE80211_CRYPT_CCMP=m +CONFIG_IEEE80211_CRYPT_TKIP=m +CONFIG_IEEE80211_SOFTMAC=m +# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set +CONFIG_WIRELESS_EXT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y + +# +# Connector - unified userspace <-> kernelspace linker +# +CONFIG_CONNECTOR=m + +# +# Memory Technology Devices (MTD) +# +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_OBSOLETE_CHIPS is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +CONFIG_MTD_BLOCK2MTD=y + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set + +# +# NAND Flash Device Drivers +# +# CONFIG_MTD_NAND is not set + +# +# OneNAND Flash Device Drivers +# +# CONFIG_MTD_ONENAND is not set + +# +# Parallel port support +# +# CONFIG_PARPORT is not set + +# +# Plug and Play support +# + +# +# Block devices +# +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_RAM is not set +CONFIG_BLK_DEV_INITRD=y +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +CONFIG_BLK_DEV_CF_MIPS=y + +# +# ATA/ATAPI/MFM/RLL support +# +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set + +# +# Multi-device support (RAID and LVM) +# +# CONFIG_MD is not set + +# +# Fusion MPT device support +# +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_IEEE1394 is not set + +# +# I2O device support +# +# CONFIG_I2O is not set + +# +# Network device support +# +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_EQUALIZER is not set +CONFIG_IMQ=m +# CONFIG_IMQ_BEHAVIOR_AA is not set +# CONFIG_IMQ_BEHAVIOR_AB is not set +CONFIG_IMQ_BEHAVIOR_BA=y +# CONFIG_IMQ_BEHAVIOR_BB is not set +CONFIG_IMQ_NUM_DEVS=2 +CONFIG_TUN=m + +# +# ARCnet devices +# +# CONFIG_ARCNET is not set + +# +# PHY device support +# +# CONFIG_PHYLIB is not set + +# +# Ethernet (10 or 100Mbit) +# +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +CONFIG_KORINA=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_DM9000 is not set + +# +# Tulip family network device support +# +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_DGRS is not set +# CONFIG_EEPRO100 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +CONFIG_VIA_RHINE=y +# CONFIG_VIA_RHINE_MMIO is not set +# CONFIG_LAN_SAA9730 is not set + +# +# Ethernet (1000 Mbit) +# +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set + +# +# Ethernet (10000 Mbit) +# +# CONFIG_CHELSIO_T1 is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set + +# +# Token Ring devices +# +# CONFIG_TR is not set + +# +# Wireless LAN (non-hamradio) +# +CONFIG_NET_RADIO=y +CONFIG_NET_WIRELESS_RTNETLINK=y + +# +# Obsolete Wireless cards support (pre-802.11) +# +# CONFIG_STRIP is not set +# CONFIG_PCMCIA_WAVELAN is not set +# CONFIG_PCMCIA_NETWAVE is not set + +# +# Wireless 802.11 Frequency Hopping cards support +# +# CONFIG_PCMCIA_RAYCS is not set + +# +# Wireless 802.11b ISA/PCI cards support +# +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +# CONFIG_HERMES is not set +# CONFIG_ATMEL is not set + +# +# Wireless 802.11b Pcmcia/Cardbus cards support +# +# CONFIG_AIRO_CS is not set +# CONFIG_PCMCIA_WL3501 is not set + +# +# Prism GT/Duette 802.11(a/b/g) PCI/Cardbus support +# +# CONFIG_PRISM54 is not set +CONFIG_HOSTAP=m +CONFIG_HOSTAP_FIRMWARE=y +CONFIG_HOSTAP_FIRMWARE_NVRAM=y +# CONFIG_HOSTAP_PLX is not set +# CONFIG_HOSTAP_PCI is not set +CONFIG_HOSTAP_CS=m +# CONFIG_BCM43XX is not set +CONFIG_NET_WIRELESS=y + +# +# PCMCIA network device support +# +# CONFIG_NET_PCMCIA is not set + +# +# Wan interfaces +# +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +# CONFIG_PPP_MULTILINK is not set +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +# CONFIG_PPP_SYNC_TTY is not set +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +# CONFIG_SLIP is not set +# CONFIG_SHAPER is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set + +# +# ISDN subsystem +# +# CONFIG_ISDN is not set + +# +# Telephony Support +# +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_TSDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +# CONFIG_SERIAL_8250_CS is not set +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set + +# +# IPMI +# +# CONFIG_IPMI_HANDLER is not set + +# +# Watchdog Cards +# +# CONFIG_WATCHDOG is not set +# CONFIG_RTC is not set +# CONFIG_GEN_RTC is not set +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# Ftape, the floppy tape device driver +# +# CONFIG_DRM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_RAW_DRIVER is not set + +# +# TPM devices +# +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set + +# +# I2C support +# +# CONFIG_I2C is not set + +# +# SPI support +# +# CONFIG_SPI is not set +# CONFIG_SPI_MASTER is not set + +# +# Dallas's 1-wire bus +# +# CONFIG_W1 is not set + +# +# Hardware Monitoring support +# +# CONFIG_HWMON is not set +# CONFIG_HWMON_VID is not set + +# +# Misc devices +# + +# +# Multimedia devices +# +# CONFIG_VIDEO_DEV is not set +CONFIG_VIDEO_V4L2=y + +# +# Digital Video Broadcasting Devices +# +# CONFIG_DVB is not set + +# +# Graphics support +# +# CONFIG_FB is not set + +# +# Sound +# +# CONFIG_SOUND is not set + +# +# USB support +# +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +# CONFIG_USB is not set + +# +# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# + +# +# USB Gadget Support +# +# CONFIG_USB_GADGET is not set + +# +# MMC/SD Card support +# +# CONFIG_MMC is not set + +# +# LED devices +# +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y + +# +# InfiniBand support +# +# CONFIG_INFINIBAND is not set + +# +# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# + +# +# Real Time Clock +# +# CONFIG_RTC_CLASS is not set + +# +# File systems +# +CONFIG_EXT2_FS=m +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=m +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_JBD=m +# CONFIG_JBD_DEBUG is not set +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +CONFIG_JFS_FS=m +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_QUOTA is not set +# CONFIG_XFS_SECURITY is not set +# CONFIG_XFS_POSIX_ACL is not set +# CONFIG_XFS_RT is not set +# CONFIG_OCFS2_FS is not set +CONFIG_MINIX_FS=m +# CONFIG_ROMFS_FS is not set +CONFIG_INOTIFY=y +# CONFIG_QUOTA is not set +# CONFIG_DNOTIFY is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_DEVFS_FS=y +CONFIG_DEVFS_MOUNT=y +# CONFIG_DEVFS_DEBUG is not set +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_RAMFS=y +# CONFIG_CONFIGFS_FS is not set + +# +# Miscellaneous filesystems +# +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_SUMMARY is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_SQUASHFS_VMALLOC is not set +# CONFIG_VXFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set + +# +# Network File Systems +# +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +CONFIG_NFS_V4=y +# CONFIG_NFS_DIRECTIO is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_CIFS=m +# CONFIG_CIFS_STATS is not set +# CONFIG_CIFS_XATTR is not set +# CONFIG_CIFS_EXPERIMENTAL is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +CONFIG_OPENWRT_PARTITION=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +CONFIG_MAC_PARTITION=y +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set + +# +# Native Language Support +# +CONFIG_NLS=m +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=m +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=m +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=m +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=m + +# +# Profiling support +# +# CONFIG_PROFILING is not set + +# +# Kernel hacking +# +# CONFIG_PRINTK_TIME is not set +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_DEBUG_FS is not set +CONFIG_CROSSCOMPILE=y +CONFIG_CMDLINE="root=/dev/mtdblock1 rootfstype=squashfs,jffs2 noinitrd console=ttyS0,115200" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set + +# +# Cryptographic options +# +CONFIG_CRYPTO=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=m +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_TGR192 is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_SERPENT is not set +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_DEFLATE=m +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Hardware crypto devices +# + +# +# Library routines +# +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC32=y +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m diff --git a/target/linux/rb532-2.6/patches/100-rb5xx_support.patch b/target/linux/rb532-2.6/patches/100-rb5xx_support.patch new file mode 100644 index 0000000000..f846c78c2b --- /dev/null +++ b/target/linux/rb532-2.6/patches/100-rb5xx_support.patch @@ -0,0 +1,5606 @@ +diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig +--- linux.old/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200 ++++ linux.dev/arch/mips/Kconfig 2006-10-11 21:56:38.000000000 +0200 +@@ -742,6 +742,19 @@ + select SYS_SUPPORTS_BIG_ENDIAN + select TOSHIBA_BOARDS + ++config MIKROTIK_RB500 ++ bool "Support for RB5xx boards" ++ select HW_HAS_PCI ++ select IRQ_CPU ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_SUPPORTS_LITTLE_ENDIAN ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SWAP_IO_SPACE ++ select DMA_NONCOHERENT ++ help ++ Support the Mikrotik(tm) Routerboard 500 series, ++ such as the RB532. ++ + config TOSHIBA_RBTX4927 + bool "Toshiba TBTX49[23]7 board" + select DMA_NONCOHERENT +@@ -1028,7 +1041,7 @@ + + config MIPS_L1_CACHE_SHIFT + int +- default "4" if MACH_DECSTATION ++ default "4" if MACH_DECSTATION || MIKROTIK_RB500 + default "7" if SGI_IP27 + default "5" + +diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile +--- linux.old/arch/mips/Makefile 2006-10-11 21:55:59.000000000 +0200 ++++ linux.dev/arch/mips/Makefile 2006-10-11 21:56:38.000000000 +0200 +@@ -580,6 +580,13 @@ + load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000 + + # ++# Routerboard 532 board ++# ++core-$(CONFIG_MIKROTIK_RB500) += arch/mips/rb500/ ++cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434 ++load-$(CONFIG_MIKROTIK_RB500) += 0xffffffff80101000 ++ ++# + # Toshiba RBTX4927 board or + # Toshiba RBTX4937 board + # +diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c +--- linux.old/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200 ++++ linux.dev/arch/mips/mm/tlbex.c 2006-10-11 21:56:38.000000000 +0200 +@@ -876,7 +876,6 @@ + case CPU_R10000: + case CPU_R12000: + case CPU_R14000: +- case CPU_4KC: + case CPU_SB1: + case CPU_SB1A: + case CPU_4KSC: +@@ -904,6 +903,7 @@ + tlbw(p); + break; + ++ case CPU_4KC: + case CPU_4KEC: + case CPU_24K: + case CPU_34K: +diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c +--- linux.old/arch/mips/pci/fixup-rb500.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/pci/fixup-rb500.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,49 @@ ++/* ++ * Copyright 2001 MontaVista Software Inc. ++ * Author: MontaVista Software, Inc. ++ * stevel@mvista.com or source@mvista.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/config.h> ++#include <linux/types.h> ++#include <linux/pci.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++ ++#include <asm/rc32434/rc32434.h> ++ ++static int __devinitdata irq_map[2][12] = { ++ { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 }, ++ { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 } ++}; ++ ++int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ int irq = 0; ++ ++ if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) { ++ irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)]; ++ } ++ return irq + GROUP4_IRQ_BASE + 4; ++} ++ +diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile +--- linux.old/arch/mips/pci/Makefile 2006-06-18 03:49:35.000000000 +0200 ++++ linux.dev/arch/mips/pci/Makefile 2006-10-11 21:56:38.000000000 +0200 +@@ -57,3 +57,4 @@ + obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-tx4938.o ops-tx4938.o + obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o + obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o ++obj-$(CONFIG_MIKROTIK_RB500) += pci-rc32434.o ops-rc32434.o fixup-rb500.o +diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c +--- linux.old/arch/mips/pci/ops-rc32434.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/pci/ops-rc32434.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,195 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * pci_ops for IDT EB434 board ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb ++ * ++ * Initial Release ++ * ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#include <linux/config.h> ++#include <linux/init.h> ++#include <linux/pci.h> ++#include <linux/types.h> ++#include <linux/delay.h> ++ ++#include <asm/cpu.h> ++#include <asm/io.h> ++ ++#include <asm/rc32434/rc32434.h> ++#include <asm/rc32434/pci.h> ++ ++#define PCI_ACCESS_READ 0 ++#define PCI_ACCESS_WRITE 1 ++ ++ ++#define PCI_CFG_SET(bus,slot,func,off) \ ++ (rc32434_pci->pcicfga = (0x80000000 | \ ++ ((bus) << 16) | ((slot)<<11) | \ ++ ((func)<<8) | (off))) ++ ++static inline int config_access(unsigned char access_type, struct pci_bus *bus, ++ unsigned int devfn, unsigned char where, ++ u32 * data) ++{ ++ unsigned int slot = PCI_SLOT(devfn); ++ u8 func = PCI_FUNC(devfn); ++ ++ /* Setup address */ ++ PCI_CFG_SET(bus->number, slot, func, where); ++ rc32434_sync(); ++ ++ if (access_type == PCI_ACCESS_WRITE) ++ rc32434_pci->pcicfgd = *data; ++ else ++ *data = rc32434_pci->pcicfgd; ++ ++ rc32434_sync(); ++ ++ return 0; ++} ++ ++ ++/* ++ * We can't address 8 and 16 bit words directly. Instead we have to ++ * read/write a 32bit word and mask/modify the data we actually want. ++ */ ++static int read_config_byte(struct pci_bus *bus, unsigned int devfn, ++ int where, u8 * val) ++{ ++ u32 data; ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); ++ *val = (data >> ((where & 3) << 3)) & 0xff; ++ return ret; ++} ++ ++static int read_config_word(struct pci_bus *bus, unsigned int devfn, ++ int where, u16 * val) ++{ ++ u32 data; ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); ++ *val = (data >> ((where & 3) << 3)) & 0xffff; ++ return ret; ++} ++ ++static int read_config_dword(struct pci_bus *bus, unsigned int devfn, ++ int where, u32 * val) ++{ ++ int ret; ++ ++ ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); ++ return ret; ++} ++ ++static int ++write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, ++ u8 val) ++{ ++ u32 data = 0; ++ ++ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) ++ return -1; ++ ++ data = (data & ~(0xff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++ ++static int ++write_config_word(struct pci_bus *bus, unsigned int devfn, int where, ++ u16 val) ++{ ++ u32 data = 0; ++ ++ if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) ++ return -1; ++ ++ data = (data & ~(0xffff << ((where & 3) << 3))) | ++ (val << ((where & 3) << 3)); ++ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) ++ return -1; ++ ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++ ++static int ++write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, ++ u32 val) ++{ ++ if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) ++ return -1; ++ ++ return PCIBIOS_SUCCESSFUL; ++} ++ ++static int pci_config_read(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 * val) ++{ ++ switch (size) { ++ case 1: ++ return read_config_byte(bus, devfn, where, (u8 *) val); ++ case 2: ++ return read_config_word(bus, devfn, where, (u16 *) val); ++ default: ++ return read_config_dword(bus, devfn, where, val); ++ } ++} ++ ++static int pci_config_write(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 val) ++{ ++ switch (size) { ++ case 1: ++ return write_config_byte(bus, devfn, where, (u8) val); ++ case 2: ++ return write_config_word(bus, devfn, where, (u16) val); ++ default: ++ return write_config_dword(bus, devfn, where, val); ++ } ++} ++ ++struct pci_ops rc32434_pci_ops = { ++ .read = pci_config_read, ++ .write = pci_config_write, ++}; +diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c +--- linux.old/arch/mips/pci/pci-rc32434.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/pci/pci-rc32434.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,234 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * PCI initialization for IDT EB434 board ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb ++ * ++ * Initial Release ++ * ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#include <linux/config.h> ++#include <linux/types.h> ++#include <linux/pci.h> ++#include <linux/kernel.h> ++#include <linux/init.h> ++ ++#include <asm/rc32434/rc32434.h> ++#include <asm/rc32434/pci.h> ++ ++#define PCI_ACCESS_READ 0 ++#define PCI_ACCESS_WRITE 1 ++ ++/* define an unsigned array for the PCI registers */ ++unsigned int korinaCnfgRegs[25] = { ++ KORINA_CNFG1, KORINA_CNFG2, KORINA_CNFG3, KORINA_CNFG4, ++ KORINA_CNFG5, KORINA_CNFG6, KORINA_CNFG7, KORINA_CNFG8, ++ KORINA_CNFG9, KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12, ++ KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16, ++ KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20, ++ KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24 ++}; ++static struct resource rc32434_res_pci_mem1; ++static struct resource rc32434_res_pci_mem2; ++ ++static struct resource rc32434_res_pci_mem1 = { ++ .name = "PCI MEM1", ++ .start = 0x50000000, ++ .end = 0x5FFFFFFF, ++ .flags = IORESOURCE_MEM, ++ .parent = &rc32434_res_pci_mem1, ++ .sibling = NULL, ++ .child = &rc32434_res_pci_mem2 ++}; ++ ++static struct resource rc32434_res_pci_mem2 = { ++ .name = "PCI Mem2", ++ .start = 0x60000000, ++ .end = 0x6FFFFFFF, ++ .flags = IORESOURCE_MEM, ++ .parent = &rc32434_res_pci_mem1, ++ .sibling = NULL, ++ .child = NULL ++}; ++ ++static struct resource rc32434_res_pci_io1 = { ++ .name = "PCI I/O1", ++ .start = 0x18800000, ++ .end = 0x188FFFFF, ++ .flags = IORESOURCE_IO, ++}; ++ ++extern struct pci_ops rc32434_pci_ops; ++ ++#define PCI_MEM1_START PCI_ADDR_START ++#define PCI_MEM1_END PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1 ++#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN ++#define PCI_MEM2_END PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN) - 1 ++#define PCI_IO1_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) ++#define PCI_IO1_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1 ++#define PCI_IO2_START PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN ++#define PCI_IO2_END PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1 ++ ++ ++struct pci_controller rc32434_controller2; ++ ++struct pci_controller rc32434_controller = { ++ .pci_ops = &rc32434_pci_ops, ++ .mem_resource = &rc32434_res_pci_mem1, ++ .io_resource = &rc32434_res_pci_io1, ++ .mem_offset = 0, ++ .io_offset = 0, ++ ++}; ++ ++#ifdef __MIPSEB__ ++#define PCI_ENDIAN_FLAG PCILBAC_sb_m ++#else ++#define PCI_ENDIAN_FLAG 0 ++#endif ++ ++static int __init rc32434_pcibridge_init(void) ++{ ++ unsigned int pcicValue, pcicData = 0; ++ unsigned int dummyRead, pciCntlVal; ++ int loopCount; ++ unsigned int pciConfigAddr; ++ ++ pcicValue = rc32434_pci->pcic; ++ pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN; ++ if (!((pcicValue == PCIM_H_EA) || ++ (pcicValue == PCIM_H_IA_FIX) || ++ (pcicValue == PCIM_H_IA_RR))) { ++ printk("PCI init error!!!\n"); ++ /* Not in Host Mode, return ERROR */ ++ return -1; ++ } ++ /* Enables the Idle Grant mode, Arbiter Parking */ ++ pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m); ++ rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */ ++ /* Zero out the PCI status & PCI Status Mask */ ++ for(;;) ++ { ++ pcicData = rc32434_pci->pcis; ++ if (!(pcicData & PCIS_rip_m)) ++ break; ++ } ++ ++ rc32434_pci->pcis = 0; ++ rc32434_pci->pcism = 0xFFFFFFFF; ++ /* Zero out the PCI decoupled registers */ ++ rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */ ++ rc32434_pci->pcidas=0; /* clear the status */ ++ rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */ ++ /* Mask PCI Messaging Interrupts */ ++ rc32434_pci_msg->pciiic = 0; ++ rc32434_pci_msg->pciiim = 0xFFFFFFFF; ++ rc32434_pci_msg->pciioic = 0; ++ rc32434_pci_msg->pciioim = 0; ++ ++ ++ /* Setup PCILB0 as Memory Window */ ++ rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START); ++ ++ /* setup the PCI map address as same as the local address */ ++ ++ rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START); ++ ++ ++ /* Setup PCILBA1 as MEM */ ++ rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG); ++ dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */ ++ rc32434_pci->pcilba[1].a = 0x60000000; ++ rc32434_pci->pcilba[1].m = 0x60000000; ++ ++ /* setup PCILBA2 as IO Window*/ ++ rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG); ++ dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */ ++ rc32434_pci->pcilba[2].a = 0x18C00000; ++ rc32434_pci->pcilba[2].m = 0x18FFFFFF; ++ ++ /* setup PCILBA2 as IO Window*/ ++ rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG ); ++ dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */ ++ ++ /* Setup PCILBA3 as IO Window */ ++ rc32434_pci->pcilba[3].a = 0x18800000; ++ rc32434_pci->pcilba[3].m = 0x18800000; ++ rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG); ++ dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */ ++ ++ pciConfigAddr=(unsigned int)(0x80000004); ++ for(loopCount=0;loopCount<24;loopCount++){ ++ rc32434_pci->pcicfga=pciConfigAddr; ++ dummyRead=rc32434_pci->pcicfga; ++ rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount]; ++ dummyRead=rc32434_pci->pcicfgd; ++ pciConfigAddr += 4; ++ } ++ rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b) ++ | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b); ++ ++ pciCntlVal=rc32434_pci->pcic; ++ pciCntlVal &=~(PCIC_tnr_m); ++ rc32434_pci->pcic = pciCntlVal; ++ pciCntlVal=rc32434_pci->pcic; ++ return 0; ++} ++ ++/* Do platform specific device initialization at pci_enable_device() time */ ++int pcibios_plat_dev_init(struct pci_dev *dev) ++{ ++ if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) { ++ /* disable prefetched memory range */ ++ pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0); ++ pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10); ++ ++ pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4); ++ } ++ return 0; ++} ++ ++static int __init rc32434_pci_init(void) ++{ ++ printk("PCI: Initializing PCI\n"); ++ ++ ioport_resource.start = rc32434_res_pci_io1.start; ++ ioport_resource.end = rc32434_res_pci_io1.end; ++ ++ rc32434_pcibridge_init(); ++ ++ register_pci_controller(&rc32434_controller); ++ rc32434_sync(); ++} ++ ++arch_initcall(rc32434_pci_init); ++ +diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c +--- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/devices.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,211 @@ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/ctype.h> ++#include <linux/string.h> ++#include <linux/platform_device.h> ++#include <asm/unaligned.h> ++#include <asm/io.h> ++ ++#include <asm/rc32434/rc32434.h> ++#include <asm/rc32434/dma.h> ++#include <asm/rc32434/dma_v.h> ++#include <asm/rc32434/eth.h> ++#include <asm/rc32434/rb.h> ++ ++#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0 ++#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1 ++#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9 ++#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10 ++ ++#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET) ++#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET) ++ ++static struct resource korina_dev0_res[] = { ++ { ++ .name = "korina_regs", ++ .start = ETH0_PhysicalAddress, ++ .end = ETH0_PhysicalAddress + sizeof(ETH_t), ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "korina_rx", ++ .start = ETH0_DMA_RX_IRQ, ++ .end = ETH0_DMA_RX_IRQ, ++ .flags = IORESOURCE_IRQ ++ }, ++ { ++ .name = "korina_tx", ++ .start = ETH0_DMA_TX_IRQ, ++ .end = ETH0_DMA_TX_IRQ, ++ .flags = IORESOURCE_IRQ ++ }, ++ { ++ .name = "korina_ovr", ++ .start = ETH0_RX_OVR_IRQ, ++ .end = ETH0_RX_OVR_IRQ, ++ .flags = IORESOURCE_IRQ ++ }, ++ { ++ .name = "korina_und", ++ .start = ETH0_TX_UND_IRQ, ++ .end = ETH0_TX_UND_IRQ, ++ .flags = IORESOURCE_IRQ ++ }, ++ { ++ .name = "korina_dma_rx", ++ .start = ETH0_RX_DMA_ADDR, ++ .end = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ { ++ .name = "korina_dma_tx", ++ .start = ETH0_TX_DMA_ADDR, ++ .end = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct korina_device korina_dev0_data = { ++ .name = "korina0", ++ .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee } ++}; ++ ++static struct platform_device korina_dev0 = { ++ .id = 0, ++ .name = "korina", ++ .dev.platform_data = &korina_dev0_data, ++ .resource = korina_dev0_res, ++ .num_resources = ARRAY_SIZE(korina_dev0_res), ++}; ++ ++ ++#define CF_GPIO_NUM 13 ++ ++static struct resource cf_slot0_res[] = { ++ { ++ .name = "cf_membase", ++ .flags = IORESOURCE_MEM ++ }, ++ { ++ .name = "cf_irq", ++ .start = (8 + 4 * 32 + CF_GPIO_NUM), /* 149 */ ++ .end = (8 + 4 * 32 + CF_GPIO_NUM), ++ .flags = IORESOURCE_IRQ ++ } ++}; ++ ++static struct cf_device cf_slot0_data = { ++ .gpio_pin = 13 ++}; ++ ++static struct platform_device cf_slot0 = { ++ .id = 0, ++ .name = "rb500-cf", ++ .dev.platform_data = &cf_slot0_data, ++ .resource = cf_slot0_res, ++ .num_resources = ARRAY_SIZE(cf_slot0_res), ++}; ++ ++ ++ ++static struct platform_device *rb500_devs[] = { ++ &korina_dev0, ++ &cf_slot0 ++}; ++ ++static void __init parse_mac_addr(char* macstr) ++{ ++ int i, j; ++ unsigned char result, value; ++ ++ for (i=0; i<6; i++) { ++ result = 0; ++ if (i != 5 && *(macstr+2) != ':') { ++ return; ++ } ++ for (j=0; j<2; j++) { ++ if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' : ++ toupper(*macstr)-'A'+10) < 16) { ++ result = result*16 + value; ++ macstr++; ++ } ++ else return; ++ } ++ ++ macstr++; ++ korina_dev0_data.mac[i] = result; ++ } ++} ++ ++ ++/* DEVICE CONTROLLER 1 */ ++#define CFG_DC_DEV1 (void*)0xb8010010 ++#define CFG_DC_DEVBASE 0x0 ++#define CFG_DC_DEVMASK 0x4 ++#define CFG_DC_DEVC 0x8 ++#define CFG_DC_DEVTC 0xC ++ ++ ++static int __init plat_setup_devices(void) ++{ ++ /* Look for the CF card reader */ ++ if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK)) ++ rb500_devs[1] = NULL; ++ else { ++ cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE); ++ cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000; ++ } ++ ++ return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs)); ++} ++ ++static int __init setup_kmac(char *s) ++{ ++ printk("korina mac = %s\n",s); ++ parse_mac_addr(s); ++ return 0; ++} ++ ++__setup("kmac=", setup_kmac); ++arch_initcall(plat_setup_devices); ++ ++ ++#if defined(CONFIG_MTD_BLOCK2MTD) && defined(CONFIG_BLK_DEV_CF_MIPS) ++extern void block2mtd_setup(char *initstr); ++extern void mount_devfs_fs(void); ++ ++static int __init setup_mtd(void) ++{ ++ struct hd_struct **part; ++ int num = 0, i; ++ char initstr[64]; ++ ++ if (cf_slot0_data.gd == NULL) ++ return 0; ++ ++ /* count partitions */ ++ part = cf_slot0_data.gd->part; ++ while (part[num] != NULL) { ++ num++; ++ } ++ ++ if (num < 2) ++ return 0; ++ ++ mount_devfs_fs(); ++ printk("Setting up block2mtd devices\n"); ++ ++ block2mtd_setup("/dev/cf/card0/part1,131072,kernel"); ++ block2mtd_setup("/dev/cf/card0/part2,131072,rootfs"); ++ ++ for (i = 2; part[i]; i++) { ++ sprintf(initstr, "/dev/cf/card0/part%d,131072,part%d", i + 1, i + 1); ++ block2mtd_setup(initstr); ++ } ++ ++ return 0; ++} ++ ++late_initcall(setup_mtd); ++#endif +diff -urN linux.old/arch/mips/rb500/early_serial.c linux.dev/arch/mips/rb500/early_serial.c +--- linux.old/arch/mips/rb500/early_serial.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/early_serial.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,199 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * EB434 specific polling driver for 16550 UART. ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * Copyright (C) 2000 by Lineo, Inc. ++ * Written by Quinn Jensen (jensenq@lineo.com) ++ ************************************************************************** ++ * P. Sadik Oct 20, 2003 ++ * ++ * DIVISOR is made a function of idt_cpu_freq ++ ************************************************************************** ++ * P. Sadik Oct 30, 2003 ++ * ++ * added reset_cons_port ++ ************************************************************************** ++ */ ++ ++#include <linux/serial_reg.h> ++ ++/* turn this on to watch the debug protocol echoed on the console port */ ++#define DEBUG_REMOTE_DEBUG ++ ++#define CONS_BAUD 115200 ++ ++extern unsigned int idt_cpu_freq; ++ ++#define EXT_FREQ 24000000 ++#define INT_FREQ idt_cpu_freq ++ ++#define EXT_PORT 0xb9800000u ++#define EXT_SHIFT 0 ++ ++#ifdef __MIPSEB__ ++#define INT_PORT 0xb8058003u ++#else ++#define INT_PORT 0xb8058000u ++#endif ++#define INT_SHIFT 2 ++ ++#define INT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14 ++#define EXT_FCR UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT ++ ++typedef struct ++{ ++ volatile unsigned char *base; ++ unsigned int shift; ++ unsigned int freq; ++ unsigned int fcr; ++} ser_port; ++ ++ser_port ports[2] = ++{ ++ { (volatile unsigned char *)INT_PORT, INT_SHIFT, 0, INT_FCR}, ++ { (volatile unsigned char *)EXT_PORT, EXT_SHIFT, EXT_FREQ, EXT_FCR} ++}; ++ ++#define CONS_PORT 0 ++ ++void cons_putc(char c); ++int port_getc(int port); ++void port_putc(int port, char c); ++ ++int cons_getc(void) ++{ ++ return port_getc(CONS_PORT); ++} ++ ++void cons_putc(char c) ++{ ++ port_putc(CONS_PORT, c); ++} ++ ++void cons_puts(char *s) ++{ ++ while(*s) { ++ if(*s == '\n') cons_putc('\r'); ++ cons_putc(*s); ++ s++; ++ } ++} ++ ++void cons_do_putn(int n) ++{ ++ if(n) { ++ cons_do_putn(n / 10); ++ cons_putc(n % 10 + '0'); ++ } ++} ++ ++void cons_putn(int n) ++{ ++ if(n < 0) { ++ cons_putc('-'); ++ n = -n; ++ } ++ ++ if (n == 0) { ++ cons_putc('0'); ++ } else { ++ cons_do_putn(n); ++ } ++} ++ ++int port_getc(int p) ++{ ++ volatile unsigned char *port = ports[p].base; ++ int s = ports[p].shift; ++ int c; ++ ++ while((*(port + (UART_LSR << s)) & UART_LSR_DR) == 0) { ++ continue; ++ } ++ ++ c = *(port + (UART_RX << s)); ++ ++ return c; ++} ++ ++int port_getc_ready(int p) ++{ ++ volatile unsigned char *port = ports[p].base; ++ int s = ports[p].shift; ++ ++ return *(port + (UART_LSR << s)) & UART_LSR_DR; ++} ++ ++#define OK_TO_XMT (UART_LSR_TEMT | UART_LSR_THRE) ++ ++void port_putc(int p, char c) ++{ ++ volatile unsigned char *port = ports[p].base; ++ int s = ports[p].shift; ++ volatile unsigned char *lsr = port + (UART_LSR << s); ++ ++ while((*lsr & OK_TO_XMT) != OK_TO_XMT) { ++ continue; ++ } ++ ++ *(port + (UART_TX << s)) = c; ++} ++ ++void reset_cons_port(void) ++{ ++ volatile unsigned char *port = ports[CONS_PORT].base; ++ unsigned int s = ports[CONS_PORT].shift; ++ unsigned int DIVISOR; ++ ++ if (ports[CONS_PORT].freq) ++ DIVISOR = (ports[CONS_PORT].freq / 16 / CONS_BAUD); ++ else ++ DIVISOR = (idt_cpu_freq / 16 / CONS_BAUD); ++ ++ /* reset the port */ ++ *(port + (UART_CSR << s)) = 0; ++ ++ /* clear and enable the FIFOs */ ++ *(port + (UART_FCR << s)) = ports[CONS_PORT].fcr; ++ ++ /* set the baud rate */ ++ *(port + (UART_LCR << s)) = UART_LCR_DLAB; /* enable DLL, DLM registers */ ++ ++ *(port + (UART_DLL << s)) = DIVISOR; ++ *(port + (UART_DLM << s)) = DIVISOR >> 8; ++ /* set the line control stuff and disable DLL, DLM regs */ ++ ++ *(port + (UART_LCR << s)) = UART_LCR_STOP | /* 2 stop bits */ ++ UART_LCR_WLEN8; /* 8 bit word length */ ++ ++ /* leave interrupts off */ ++ *(port + (UART_IER << s)) = 0; ++ ++ /* the modem controls don't leave the chip on this port, so leave them alone */ ++ *(port + (UART_MCR << s)) = 0; ++} +diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c +--- linux.old/arch/mips/rb500/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/irq.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,264 @@ ++/* ++ * BRIEF MODULE DESCRIPTION ++ * RC32434 interrupt routines. ++ * ++ * Copyright 2002 MontaVista Software Inc. ++ * Author: MontaVista Software, Inc. ++ * stevel@mvista.com or source@mvista.com ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++#include <linux/errno.h> ++#include <linux/init.h> ++#include <linux/kernel_stat.h> ++#include <linux/module.h> ++#include <linux/signal.h> ++#include <linux/sched.h> ++#include <linux/types.h> ++#include <linux/interrupt.h> ++#include <linux/ioport.h> ++#include <linux/timex.h> ++#include <linux/slab.h> ++#include <linux/random.h> ++#include <linux/delay.h> ++ ++#include <asm/bitops.h> ++#include <asm/bootinfo.h> ++#include <asm/io.h> ++#include <asm/irq.h> ++#include <asm/time.h> ++#include <asm/mipsregs.h> ++#include <asm/system.h> ++#include <asm/rc32434/rc32434.h> ++#include <asm/rc32434/gpio.h> ++ ++extern void set_debug_traps(void); ++extern irq_cpustat_t irq_stat [NR_CPUS]; ++unsigned int local_bh_count[NR_CPUS]; ++unsigned int local_irq_count[NR_CPUS]; ++ ++static unsigned int startup_irq(unsigned int irq); ++static void rb500_end_irq(unsigned int irq_nr); ++static void mask_and_ack_irq(unsigned int irq_nr); ++static void rb500_enable_irq(unsigned int irq_nr); ++static void rb500_disable_irq(unsigned int irq_nr); ++ ++extern void __init init_generic_irq(void); ++ ++typedef struct { ++ u32 mask; /* mask of valid bits in pending/mask registers */ ++ volatile u32 *base_addr; ++} intr_group_t; ++ ++#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32) ++ ++#if (NR_IRQS < RC32434_NR_IRQS) ++#error Too little irqs defined. Did you override <asm/irq.h> ? ++#endif ++ ++static const intr_group_t intr_group[NUM_INTR_GROUPS] = { ++ { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) }, ++ { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) }, ++ { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) }, ++ { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) }, ++ { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) } ++}; ++ ++#define READ_PEND(base) (*(base)) ++#define READ_MASK(base) (*(base + 2)) ++#define WRITE_MASK(base, val) (*(base + 2) = (val)) ++ ++static inline int irq_to_group(unsigned int irq_nr) ++{ ++ return ((irq_nr - GROUP0_IRQ_BASE) >> 5); ++} ++ ++static inline int group_to_ip(unsigned int group) ++{ ++ return group + 2; ++} ++ ++static inline void enable_local_irq(unsigned int ip) ++{ ++ int ipnum = 0x100 << ip; ++ clear_c0_cause(ipnum); ++ set_c0_status(ipnum); ++} ++ ++static inline void disable_local_irq(unsigned int ip) ++{ ++ int ipnum = 0x100 << ip; ++ clear_c0_status(ipnum); ++} ++ ++static inline void ack_local_irq(unsigned int ip) ++{ ++ int ipnum = 0x100 << ip; ++ clear_c0_cause(ipnum); ++} ++ ++static void rb500_enable_irq(unsigned int irq_nr) ++{ ++ int ip = irq_nr - GROUP0_IRQ_BASE; ++ unsigned int group, intr_bit; ++ volatile unsigned int *addr; ++ ++ ++ if (ip < 0) ++ enable_local_irq(irq_nr); ++ else { ++ group = ip >> 5; ++ ++ ip &= (1<<5)-1; ++ intr_bit = 1 << ip; ++ ++ enable_local_irq(group_to_ip(group)); ++ ++ addr = intr_group[group].base_addr; ++ WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit); ++ } ++} ++ ++static void rb500_disable_irq(unsigned int irq_nr) ++{ ++ int ip = irq_nr - GROUP0_IRQ_BASE; ++ unsigned int group, intr_bit, mask; ++ volatile unsigned int *addr; ++ ++ if (ip < 0) { ++ disable_local_irq(irq_nr); ++ }else{ ++ group = ip >> 5; ++ ++ ip &= (1<<5) -1; ++ intr_bit = 1 << ip; ++ addr = intr_group[group].base_addr; ++ mask = READ_MASK(addr); ++ mask |= intr_bit; ++ WRITE_MASK(addr,mask); ++ ++ /* ++ * if there are no more interrupts enabled in this ++ * group, disable corresponding IP ++ */ ++ if (mask == intr_group[group].mask) ++ disable_local_irq(group_to_ip(group)); ++ } ++} ++ ++static unsigned int startup_irq(unsigned int irq_nr) ++{ ++ rb500_enable_irq(irq_nr); ++ return 0; ++} ++ ++static void shutdown_irq(unsigned int irq_nr) ++{ ++ rb500_disable_irq(irq_nr); ++ return; ++} ++ ++static void mask_and_ack_irq(unsigned int irq_nr) ++{ ++ rb500_disable_irq(irq_nr); ++ ack_local_irq(group_to_ip(irq_to_group(irq_nr))); ++} ++ ++static void rb500_end_irq(unsigned int irq_nr) ++{ ++ ++ int ip = irq_nr - GROUP0_IRQ_BASE; ++ unsigned int intr_bit, group; ++ volatile unsigned int *addr; ++ ++ if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { ++ printk("warning: end_irq %d did not enable (%x)\n", ++ irq_nr, irq_desc[irq_nr].status); ++ return; ++ } ++ ++ if (ip < 0) { ++ enable_local_irq(irq_nr); ++ } else { ++ group = ip >> 5; ++ ++ ip &= (1 << 5) - 1; ++ intr_bit = 1 << ip; ++ ++ if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) { ++ gpio->gpioistat = gpio->gpioistat & ~intr_bit; ++ } ++ ++ enable_local_irq(group_to_ip(group)); ++ ++ addr = intr_group[group].base_addr; ++ WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit); ++ } ++} ++ ++static struct hw_interrupt_type rc32434_irq_type = { ++ .typename = "RB500", ++ .startup = startup_irq, ++ .shutdown = shutdown_irq, ++ .enable = rb500_enable_irq, ++ .disable = rb500_disable_irq, ++ .ack = mask_and_ack_irq, ++ .end = rb500_end_irq, ++}; ++ ++ ++void __init arch_init_irq(void) ++{ ++ int i; ++ ++ printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS); ++ memset(irq_desc, 0, sizeof(irq_desc)); ++ ++ for (i = 0; i < RC32434_NR_IRQS; i++) { ++ irq_desc[i].status = IRQ_DISABLED; ++ irq_desc[i].action = NULL; ++ irq_desc[i].depth = 1; ++ irq_desc[i].handler = &rc32434_irq_type; ++ spin_lock_init(&irq_desc[i].lock); ++ } ++} ++ ++/* Main Interrupt dispatcher */ ++asmlinkage void plat_irq_dispatch(struct pt_regs *regs) ++{ ++ unsigned int ip, pend, group; ++ volatile unsigned int *addr; ++ unsigned int cp0_cause = read_c0_cause() & read_c0_status(); ++ ++ if (cp0_cause & CAUSEF_IP7) { ++ ll_timer_interrupt(7, regs); ++ } else if ((ip = (cp0_cause & 0x7c00))) { ++ group = 21 - rc32434_clz(ip); ++ ++ addr = intr_group[group].base_addr; ++ ++ pend = READ_PEND(addr); ++ pend &= ~READ_MASK(addr); // only unmasked interrupts ++ pend = 39 - rc32434_clz(pend); ++ do_IRQ((group << 5) + pend, regs); ++ } ++} +diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile +--- linux.old/arch/mips/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/Makefile 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,5 @@ ++# ++# Makefile for the RB500 board specific parts of the kernel ++# ++ ++obj-y += irq.o time.o setup.o serial.o early_serial.o prom.o misc.o devices.o +diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c +--- linux.old/arch/mips/rb500/misc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/misc.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,54 @@ ++#include <linux/module.h> ++#include <linux/kernel.h> /* printk() */ ++#include <linux/types.h> /* size_t */ ++#include <linux/pci.h> ++#include <linux/spinlock.h> ++#include <asm/rc32434/rb.h> ++ ++#define GPIO_BADDR 0xb8050000 ++ ++ ++static unsigned char *devCtl3Base = (unsigned char *) KSEG1ADDR(0x18010030); ++static unsigned char latchU5State = 0; ++static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED; ++ ++void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) { ++ unsigned flags, data; ++ unsigned i = 0; ++ spin_lock_irqsave(&clu5Lock, flags); ++ data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs); ++ for (i = 0; i != len; ++i) { ++ if (val & (1 << i)) data |= (1 << (i + bit)); ++ else data &= ~(1 << (i + bit)); ++ } ++ *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data; ++ spin_unlock_irqrestore(&clu5Lock, flags); ++} ++ ++void changeLatchU5(unsigned char orMask, unsigned char nandMask) { ++ unsigned flags; ++ spin_lock_irqsave(&clu5Lock, flags); ++ latchU5State = (latchU5State | orMask) & ~nandMask; ++ *devCtl3Base = latchU5State; ++ spin_unlock_irqrestore(&clu5Lock, flags); ++} ++ ++u32 gpio_get(gpio_func func) ++{ ++ return readl((void *) GPIO_BADDR + func); ++} ++ ++void gpio_set(gpio_func func, u32 mask, u32 value) ++{ ++ u32 val = readl((void *) GPIO_BADDR + func); ++ ++ val &= ~mask; ++ val |= value & mask; ++ ++ writel(val, (void *) GPIO_BADDR + func); ++} ++ ++EXPORT_SYMBOL(gpio_set); ++EXPORT_SYMBOL(gpio_get); ++EXPORT_SYMBOL(set434Reg); ++EXPORT_SYMBOL(changeLatchU5); +diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c +--- linux.old/arch/mips/rb500/prom.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/prom.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,181 @@ ++/* ++* prom.c ++********************************************************************** ++* P . Sadik Oct 10, 2003 ++* ++* Started change log ++* idt_cpu_freq is make a kernel configuration parameter ++* idt_cpu_freq is exported so that other modules can use it. ++* Code cleanup ++********************************************************************** ++* P. Sadik Oct 20, 2003 ++* ++* Removed NVRAM code from here, since they are already available under ++* nvram directory. ++* Added serial port initialisation. ++********************************************************************** ++********************************************************************** ++* P. Sadik Oct 30, 2003 ++* ++* Added reset_cons_port ++********************************************************************** ++ ++ P.Christeas, 2005-2006 ++ Port to 2.6, add 2.6 cmdline parsing ++ ++*/ ++ ++#include <linux/config.h> ++#include <linux/init.h> ++#include <linux/mm.h> ++#include <linux/module.h> ++#include <linux/string.h> ++#include <linux/console.h> ++#include <asm/bootinfo.h> ++#include <linux/bootmem.h> ++#include <linux/ioport.h> ++#include <linux/blkdev.h> ++#include <asm/rc32434/ddr.h> ++ ++#define PROM_ENTRY(x) (0xbfc00000+((x)*8)) ++extern void __init setup_serial_port(void); ++extern void cons_putc(char c); ++extern void cons_puts(char *s); ++ ++unsigned int idt_cpu_freq = 132000000; ++EXPORT_SYMBOL(idt_cpu_freq); ++unsigned int board_type = 500; ++EXPORT_SYMBOL(board_type); ++unsigned int gpio_bootup_state = 0; ++EXPORT_SYMBOL(gpio_bootup_state); ++ ++ ++char mips_mac_address[18] = "08:00:06:05:40:01"; ++EXPORT_SYMBOL(mips_mac_address); ++ ++/* what to append to cmdline when button is [not] pressed */ ++#define GPIO_INIT_NOBUTTON "" ++#define GPIO_INIT_BUTTON " 2" ++ ++#ifdef CONFIG_MIKROTIK_RB500 ++unsigned soft_reboot = 0; ++EXPORT_SYMBOL(soft_reboot); ++#endif ++ ++#define SR_NMI 0x00180000 /* NMI */ ++#define SERIAL_SPEED_ENTRY 0x00000001 ++ ++#ifdef CONFIG_REMOTE_DEBUG ++extern int remote_debug; ++#endif ++ ++extern unsigned long mips_machgroup; ++extern unsigned long mips_machtype; ++ ++#define FREQ_TAG "HZ=" ++#define GPIO_TAG "gpio=" ++#define KMAC_TAG "kmac=" ++#define MEM_TAG "mem=" ++#define BOARD_TAG "board=" ++#define IGNORE_CMDLINE_MEM 1 ++#define DEBUG_DDR ++ ++void parse_soft_settings(unsigned *ptr, unsigned size); ++void parse_hard_settings(unsigned *ptr, unsigned size); ++ ++void __init prom_setup_cmdline(void); ++ ++#ifdef DEBUG_DDR ++void cons_puthex4(u32 h){ ++ h&=0x0f; ++ if (h>=10) ++ cons_putc((h-10)+'a'); ++ else ++ cons_putc(h+'0'); ++} ++ ++void cons_putreg32(u32 reg){ ++ char c; ++ cons_putc('0'); ++ cons_putc('x'); ++ for (c=28;c>=0;c-=4) ++ cons_puthex4(reg>>c); ++} ++#endif ++ ++void __init prom_init(void) ++{ ++ DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */ ++ phys_t memsize = 0-ddr->ddrmask; ++ ++ /* this should be the very first message, even before serial is properly initialized */ ++ prom_setup_cmdline(); ++ setup_serial_port(); ++ ++ mips_machgroup = MACH_GROUP_MIKROTIK; ++ soft_reboot = read_c0_status() & SR_NMI; ++ pm_power_off = NULL; ++ ++ /* ++ * give all RAM to boot allocator, ++ * except for the first 0x400 and the last 0x200 bytes ++ */ ++ add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM); ++} ++ ++void prom_free_prom_memory(void) ++{ ++ /* FIXME: STUB */ ++} ++ ++void __init prom_setup_cmdline(void){ ++ char cmd_line[CL_SIZE]; ++ char *cp; ++ int prom_argc; ++ char **prom_argv, **prom_envp; ++ int i; ++ ++ prom_argc = fw_arg0; ++ prom_argv = (char **) fw_arg1; ++ prom_envp = (char **) fw_arg2; ++ ++ cp=cmd_line; ++ /* Note: it is common that parameters start at argv[1] and not argv[0], ++ however, our elf loader starts at [0] */ ++ for(i=0;i<prom_argc;i++){ ++ if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) { ++ idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10); ++ continue; ++ } ++#ifdef IGNORE_CMDLINE_MEM ++ /* parses out the "mem=xx" arg */ ++ if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) { ++ continue; ++ } ++#endif ++ if (i>0) *(cp++) = ' '; ++ if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) { ++ board_type = simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10); ++ } ++ if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) { ++ gpio_bootup_state = simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10); ++ } ++ strcpy(cp,prom_argv[i]); ++ cp+=strlen(prom_argv[i]); ++ } ++ ++ i=strlen(arcs_cmdline); ++ if (i>0){ ++ *(cp++) = ' '; ++ strcpy(cp,arcs_cmdline); ++ cp+=strlen(arcs_cmdline); ++ } ++ if (gpio_bootup_state&0x02) ++ strcpy(cp,GPIO_INIT_NOBUTTON); ++ else ++ strcpy(cp,GPIO_INIT_BUTTON); ++ cmd_line[CL_SIZE-1] = '\0'; ++ ++ strcpy(arcs_cmdline,cmd_line); ++} ++ +diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c +--- linux.old/arch/mips/rb500/serial.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/serial.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,79 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * Serial port initialisation. ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb ++ * ++ * Initial Release ++ * ++ * ++ * ++ ************************************************************************** ++ */ ++ ++ ++#include <linux/config.h> ++#include <linux/init.h> ++#include <linux/sched.h> ++#include <linux/pci.h> ++#include <linux/interrupt.h> ++#include <linux/tty.h> ++#include <linux/serial.h> ++#include <linux/serial_core.h> ++ ++#include <asm/time.h> ++#include <asm/cpu.h> ++#include <asm/bootinfo.h> ++#include <asm/irq.h> ++#include <asm/serial.h> ++#include <asm/rc32434/rc32434.h> ++ ++extern unsigned int idt_cpu_freq; ++ ++static struct uart_port serial_req = { ++ .type = PORT_16550A, ++ .line = 0, ++ .irq = RC32434_UART0_IRQ, ++ .flags = STD_COM_FLAGS, ++ .iotype = UPIO_MEM, ++ .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE), ++// .fifosize = 14 ++ .regshift = 2 ++}; ++ ++int __init setup_serial_port(void) ++{ ++ serial_req.uartclk = idt_cpu_freq; ++ ++ if (early_serial_setup(&serial_req)){ ++ cons_puts("Serial setup failed!\n"); ++ return -ENODEV; ++ } ++ ++ return(0); ++} +diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c +--- linux.old/arch/mips/rb500/setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/setup.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,84 @@ ++/* ++ * setup.c - boot time setup code ++ */ ++ ++#include <linux/init.h> ++#include <linux/mm.h> ++#include <linux/sched.h> ++#include <linux/irq.h> ++#include <asm/bootinfo.h> ++#include <asm/io.h> ++#include <linux/ioport.h> ++#include <asm/mipsregs.h> ++#include <asm/pgtable.h> ++#include <asm/reboot.h> ++#include <asm/addrspace.h> /* for KSEG1ADDR() */ ++#include <asm/rc32434/rc32434.h> ++#include <linux/pm.h> ++#include <asm/rc32434/pci.h> ++ ++extern void (*board_time_init)(void); ++extern void (*board_timer_setup)(struct irqaction *irq); ++extern void rc32434_time_init(void); ++extern void rc32434_timer_setup(struct irqaction *irq); ++#ifdef CONFIG_PCI ++extern int __init rc32434_pcibridge_init(void); ++#endif ++ ++#define epldMask ((volatile unsigned char *)0xB900000d) ++ ++static void rb_machine_restart(char *command) ++{ ++ /* just jump to the reset vector */ ++ * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001; ++ ((void (*)(void))KSEG1ADDR(0x1FC00000u))(); ++} ++ ++static void rb_machine_halt(void) ++{ ++ for(;;) continue; ++} ++ ++#ifdef CONFIG_CPU_HAS_WB ++void (*__wbflush) (void); ++ ++static void rb_write_buffer_flush(void) ++{ ++ __asm__ __volatile__ ++ ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t"); ++} ++#endif ++ ++void __init plat_setup(void) ++{ ++ unsigned int pciCntlVal; ++ ++ board_time_init = rc32434_time_init; ++ board_timer_setup = rc32434_timer_setup; ++ ++#ifdef CONFIG_CPU_HAS_WB ++ __wbflush = rb_write_buffer_flush; ++#endif ++ _machine_restart = rb_machine_restart; ++ _machine_halt = rb_machine_halt; ++ /*_machine_power_off = rb_machine_power_halt;*/ ++ pm_power_off = rb_machine_halt; ++ ++ set_io_port_base(KSEG1); ++ ++ pciCntlVal=rc32434_pci->pcic; ++ pciCntlVal &= 0xFFFFFF7; ++ rc32434_pci->pcic = pciCntlVal; ++ ++#ifdef CONFIG_PCI ++ /* Enable PCI interrupts in EPLD Mask register */ ++ *epldMask = 0x0; ++ *(epldMask + 1) = 0x0; ++#endif ++ write_c0_wired(0); ++} ++ ++const char *get_system_type(void) ++{ ++ return "MIPS RB500"; ++} +diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c +--- linux.old/arch/mips/rb500/time.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/rb500/time.c 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,94 @@ ++/* ++**************************************************************************** ++* Carsten Langgaard, carstenl@mips.com ++* Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. ++* ++*************************************************************************** ++* ++* This program is free software; you can distribute it and/or modify it ++* under the terms of the GNU General Public License (Version 2) as ++* published by the Free Software Foundation. ++* ++* This program is distributed in the hope it will be useful, but WITHOUT ++* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++* for more details. ++* ++* You should have received a copy of the GNU General Public License along ++* with this program; if not, write to the Free Software Foundation, Inc., ++* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++* ++**************************************************************************** ++* ++* Setting up the clock on the MIPS boards. ++* ++**************************************************************************** ++* P. Sadik Oct 10, 2003 ++* ++* Started change log. ++* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq. ++* Code cleanup ++**************************************************************************** ++*/ ++ ++#include <linux/config.h> ++#include <linux/init.h> ++#include <linux/kernel_stat.h> ++#include <linux/sched.h> ++#include <linux/spinlock.h> ++#include <linux/mc146818rtc.h> ++#include <linux/irq.h> ++#include <linux/timex.h> ++ ++#include <asm/mipsregs.h> ++#include <asm/ptrace.h> ++#include <asm/debug.h> ++#include <asm/rc32434/rc32434.h> ++ ++static unsigned long r4k_offset; /* Amount to incr compare reg each time */ ++static unsigned long r4k_cur; /* What counter should be at next timer irq */ ++extern void ll_timer_interrupt(int irq, struct pt_regs *regs); ++extern unsigned int mips_hpt_frequency; ++extern unsigned int idt_cpu_freq; ++ ++/* ++ * Figure out the r4k offset, the amount to increment the compare ++ * register for each time tick. There is no RTC available. ++ * ++ * The RC32434 counts at half the CPU *core* speed. ++ */ ++static unsigned long __init cal_r4koff(void) ++{ ++ mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2; ++ return (mips_hpt_frequency / HZ); ++} ++ ++ ++void __init rc32434_time_init(void) ++{ ++ unsigned int est_freq, flags; ++ ++ local_irq_save(flags); ++ ++ printk("calculating r4koff... "); ++ r4k_offset = cal_r4koff(); ++ printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset); ++ ++ est_freq = 2*r4k_offset*HZ; ++ est_freq += 5000; /* round */ ++ est_freq -= est_freq%10000; ++ printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, ++ (est_freq%1000000)*100/1000000); ++ local_irq_restore(flags); ++} ++ ++void __init rc32434_timer_setup(struct irqaction *irq) ++{ ++ /* we are using the cpu counter for timer interrupts */ ++ setup_irq(MIPS_CPU_TIMER_IRQ, irq); ++ ++ /* to generate the first timer interrupt */ ++ r4k_cur = (read_c0_count() + r4k_offset); ++ write_c0_compare(r4k_cur); ++} ++ +diff -urN linux.old/drivers/mtd/devices/block2mtd.c linux.dev/drivers/mtd/devices/block2mtd.c +--- linux.old/drivers/mtd/devices/block2mtd.c 2006-10-11 21:55:59.000000000 +0200 ++++ linux.dev/drivers/mtd/devices/block2mtd.c 2006-10-11 22:24:51.000000000 +0200 +@@ -26,7 +26,6 @@ + #define ERROR(fmt, args...) printk(KERN_ERR "block2mtd: " fmt "\n" , ## args) + #define INFO(fmt, args...) printk(KERN_INFO "block2mtd: " fmt "\n" , ## args) + +- + /* Info for the block device */ + struct block2mtd_dev { + struct list_head list; +@@ -104,7 +103,7 @@ + + while (pages) { + page = page_readahead(mapping, index); +- if (!page) ++ if (!page || !page_address(page)) + return -ENOMEM; + if (IS_ERR(page)) + return PTR_ERR(page); +@@ -285,7 +284,7 @@ + + + /* FIXME: ensure that mtd->size % erase_size == 0 */ +-static struct block2mtd_dev *add_device(char *devname, int erase_size) ++static struct block2mtd_dev *add_device(char *devname, int erase_size, char *alias) + { + struct block_device *bdev; + struct block2mtd_dev *dev; +@@ -328,14 +327,15 @@ + + /* Setup the MTD structure */ + /* make the name contain the block device in */ +- dev->mtd.name = kmalloc(sizeof("block2mtd: ") + strlen(devname), ++ dev->mtd.name = kmalloc(strlen((alias ?: devname)), + GFP_KERNEL); + if (!dev->mtd.name) + goto devinit_err; + +- sprintf(dev->mtd.name, "block2mtd: %s", devname); ++ strcpy(dev->mtd.name, (alias ?: devname)); + + dev->mtd.size = dev->blkdev->bd_inode->i_size & PAGE_MASK; ++ dev->mtd.size -= dev->mtd.size % erase_size; + dev->mtd.erasesize = erase_size; + dev->mtd.type = MTD_RAM; + dev->mtd.flags = MTD_CAP_RAM; +@@ -353,7 +353,7 @@ + } + list_add(&dev->list, &blkmtd_device_list); + INFO("mtd%d: [%s] erase_size = %dKiB [%d]", dev->mtd.index, +- dev->mtd.name + strlen("blkmtd: "), ++ dev->mtd.name, + dev->mtd.erasesize >> 10, dev->mtd.erasesize); + return dev; + +@@ -429,7 +429,7 @@ + { + char buf[80 + 12]; /* 80 for device, 12 for erase size */ + char *str = buf; +- char *token[2]; ++ char *token[3]; + char *name; + size_t erase_size = PAGE_SIZE; + int i, ret; +@@ -440,7 +440,7 @@ + strcpy(str, val); + kill_final_newline(str); + +- for (i = 0; i < 2; i++) ++ for (i = 0; i < 3; i++) + token[i] = strsep(&str, ","); + + if (str) +@@ -461,13 +461,13 @@ + } + } + +- add_device(name, erase_size); ++ add_device(name, erase_size, token[2]); + + return 0; + } + + +-static int block2mtd_setup(const char *val, struct kernel_param *kp) ++int block2mtd_setup(const char *val, struct kernel_param *kp) + { + #ifdef MODULE + return block2mtd_setup2(val); +@@ -496,6 +496,7 @@ + + module_param_call(block2mtd, block2mtd_setup, NULL, NULL, 0200); + MODULE_PARM_DESC(block2mtd, "Device to use. \"block2mtd=<dev>[,<erasesize>]\""); ++EXPORT_SYMBOL(block2mtd_setup); + + static int __init block2mtd_init(void) + { +diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile +--- linux.old/drivers/pci/Makefile 2006-06-18 03:49:35.000000000 +0200 ++++ linux.dev/drivers/pci/Makefile 2006-10-11 21:56:38.000000000 +0200 +@@ -27,6 +27,7 @@ + obj-$(CONFIG_MIPS) += setup-bus.o setup-irq.o + obj-$(CONFIG_X86_VISWS) += setup-irq.o + obj-$(CONFIG_PCI_MSI) += msi.o ++obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o + + # + # ACPI Related PCI FW Functions +diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h +--- linux.old/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200 ++++ linux.dev/include/asm-mips/bootinfo.h 2006-10-11 21:56:38.000000000 +0200 +@@ -218,6 +218,8 @@ + #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */ + #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */ + ++#define MACH_GROUP_MIKROTIK 24 /* Mikrotik Boards */ ++ + #define CL_SIZE COMMAND_LINE_SIZE + + const char *get_system_type(void); +diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h +--- linux.old/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200 ++++ linux.dev/include/asm-mips/cpu.h 2006-10-11 21:56:38.000000000 +0200 +@@ -200,7 +200,8 @@ + #define CPU_SB1A 62 + #define CPU_74K 63 + #define CPU_R14000 64 +-#define CPU_LAST 64 ++#define CPU_RC32300 65 ++#define CPU_LAST 65 + + /* + * ISA Level encodings +diff -urN linux.old/include/asm-mips/rc32434/crom.h linux.dev/include/asm-mips/rc32434/crom.h +--- linux.old/include/asm-mips/rc32434/crom.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/crom.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,98 @@ ++#ifndef __IDT_CROM_H__ ++#define __IDT_CROM_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Configuration ROM register definitions. ++ * ++ * File : $Id: crom.h,v 1.2 2002/06/06 18:34:03 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020118 ++ * Update : ++ * $Log: crom.h,v $ ++ * Revision 1.2 2002/06/06 18:34:03 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.1 2002/05/29 17:33:21 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ CROM0_PhysicalAddress = 0x100b8000, ++ CROM_PhysicalAddress = CROM0_PhysicalAddress, ++ ++ CROM0_VirtualAddress = 0xb00b8000, ++ CROM_VirtualAddress = CROM0_VirtualAddress, ++} ; ++ ++typedef struct CROM_s ++{ ++ U32 cromw0 ; // use CROMW0_ ++ U32 cromw1 ; // use CROMW1_ ++ U32 cromw2 ; // use CROMW2_ ++} volatile * CROM_t ; ++ ++enum ++{ ++ CROMW0_xloc_b = 0, ++ CROMW0_xloc_m = 0x0000003f, ++ CROMW0_yloc_b = 8, ++ CROMW0_yloc_m = 0x00003f00, ++ CROMW0_speed_b = 16, ++ CROMW0_speed_m = 0x01ff0000, ++ CROMW1_wafer_b = 0, ++ CROMW1_wafer_m = 0x0000001f, ++ CROMW1_lot_b = 8, ++ CROMW1_lot_m = 0x0fffff00, ++ CROMW1_fab_b = 28, ++ CROMW1_fab_m = 0xf0000000, ++ CROMW2_pci_b = 0, ++ CROMW2_pci_m = 0x00000001, ++ CROMW2_eth0_b = 1, ++ CROMW2_eth0_m = 0x00000002, ++ CROMW2_eth1_b = 2, ++ CROMW2_eth1_m = 0x00000004 ++ CROMW2_i2c_b = 3, ++ CROMW2_i2c_m = 0x00000008, ++ CROMW2_rng_b = 4, ++ CROMW2_rng_m = 0x00000010, ++ CROMW2_se_b = 5, ++ CROMW2_se_m = 0x00000020, ++ CROMW2_des_b = 6, ++ CROMW2_des_m = 0x00000040, ++ CROMW2_tdes_b = 7, ++ CROMW2_tdes_m = 0x00000080, ++ CROMW2_a128_b = 8, ++ CROMW2_a128_m = 0x00000100, ++ CROMW2_a192_b = 9, ++ CROMW2_a192_m = 0x00000200, ++ CROMW2_a256_b = 10, ++ CROMW2_a256_m = 0x00000400, ++ CROMW2_md5_b = 11, ++ CROMW2_md5_m = 0x00000800, ++ CROMW2_s1_b = 12, ++ CROMW2_s1_m = 0x00001000, ++ CROMW2_s256_b = 13, ++ CROMW2_s256_m = 0x00002000, ++ CROMW2_pka_b = 14, ++ CROMW2_pka_m = 0x00004000, ++ CROMW2_exp_b = 15, ++ CROMW2_exp_m = 0x00018000, ++ CROMW2_exp_8192_v = 0, ++ CROMW2_exp_1536_v = 1, ++ CROMW2_exp_1024_v = 2, ++ CROMW2_exp_512_v = 3, ++ CROMW2_rocfg_b = 17, ++ CROMW2_rocfg_m = 0x000e0000, ++} ; ++ ++#endif // __IDT_CROM_H__ +diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h +--- linux.old/include/asm-mips/rc32434/ddr.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/ddr.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,175 @@ ++#ifndef __IDT_DDR_H__ ++#define __IDT_DDR_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * DDR register definition. ++ * ++ * File : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $ ++ * ++ * Author : ryan.holmQVist@idt.com ++ * Date : 20011005 ++ * Update : ++ * $Log: ddr.h,v $ ++ * Revision 1.2 2002/06/06 18:34:03 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.1 2002/05/29 17:33:21 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ DDR0_PhysicalAddress = 0x18018000, ++ DDR_PhysicalAddress = DDR0_PhysicalAddress, // Default ++ ++ DDR0_VirtualAddress = 0xb8018000, ++ DDR_VirtualAddress = DDR0_VirtualAddress, // Default ++} ; ++ ++typedef struct DDR_s ++{ ++ U32 ddrbase ; ++ U32 ddrmask ; ++ U32 res1; ++ U32 res2; ++ U32 ddrc ; ++ U32 ddrabase ; ++ U32 ddramask ; ++ U32 ddramap ; ++ U32 ddrcust; ++ U32 ddrrdc; ++ U32 ddrspare; ++} volatile *DDR_t ; ++ ++enum ++{ ++ DDR0BASE_baseaddr_b = 16, ++ DDR0BASE_baseaddr_m = 0xffff0000, ++ ++ DDR0MASK_mask_b = 16, ++ DDR0MASK_mask_m = 0xffff0000, ++ ++ DDR1BASE_baseaddr_b = 16, ++ DDR1BASE_baseaddr_m = 0xffff0000, ++ ++ DDR1MASK_mask_b = 16, ++ DDR1MASK_mask_m = 0xffff0000, ++ ++ DDRC_ata_b = 5, ++ DDRC_ata_m = 0x000000E0, ++ DDRC_dbw_b = 8, ++ DDRC_dbw_m = 0x00000100, ++ DDRC_wr_b = 9, ++ DDRC_wr_m = 0x00000600, ++ DDRC_ps_b = 11, ++ DDRC_ps_m = 0x00001800, ++ DDRC_dtype_b = 13, ++ DDRC_dtype_m = 0x0000e000, ++ DDRC_rfc_b = 16, ++ DDRC_rfc_m = 0x000f0000, ++ DDRC_rp_b = 20, ++ DDRC_rp_m = 0x00300000, ++ DDRC_ap_b = 22, ++ DDRC_ap_m = 0x00400000, ++ DDRC_rcd_b = 23, ++ DDRC_rcd_m = 0x01800000, ++ DDRC_cl_b = 25, ++ DDRC_cl_m = 0x06000000, ++ DDRC_dbm_b = 27, ++ DDRC_dbm_m = 0x08000000, ++ DDRC_sds_b = 28, ++ DDRC_sds_m = 0x10000000, ++ DDRC_atp_b = 29, ++ DDRC_atp_m = 0x60000000, ++ DDRC_re_b = 31, ++ DDRC_re_m = 0x80000000, ++ ++ DDRRDC_ces_b = 0, ++ DDRRDC_ces_m = 0x00000001, ++ DDRRDC_ace_b = 1, ++ DDRRDC_ace_m = 0x00000002, ++ ++ DDRABASE_baseaddr_b = 16, ++ DDRABASE_baseaddr_m = 0xffff0000, ++ ++ DDRAMASK_mask_b = 16, ++ DDRAMASK_mask_m = 0xffff0000, ++ ++ DDRAMAP_map_b = 16, ++ DDRAMAP_map_m = 0xffff0000, ++ ++ DDRCUST_cs_b = 0, ++ DDRCUST_cs_m = 0x00000003, ++ DDRCUST_we_b = 2, ++ DDRCUST_we_m = 0x00000004, ++ DDRCUST_ras_b = 3, ++ DDRCUST_ras_m = 0x00000008, ++ DDRCUST_cas_b = 4, ++ DDRCUST_cas_m = 0x00000010, ++ DDRCUST_cke_b = 5, ++ DDRCUST_cke_m = 0x00000020, ++ DDRCUST_ba_b = 6, ++ DDRCUST_ba_m = 0x000000c0, ++ ++ RCOUNT_rcount_b = 0, ++ RCOUNT_rcount_m = 0x0000ffff, ++ ++ RCOMPARE_rcompare_b = 0, ++ RCOMPARE_rcompare_m = 0x0000ffff, ++ ++ RTC_ce_b = 0, ++ RTC_ce_m = 0x00000001, ++ RTC_to_b = 1, ++ RTC_to_m = 0x00000002, ++ RTC_rqe_b = 2, ++ RTC_rqe_m = 0x00000004, ++ ++ DDRDQSC_dm_b = 0, ++ DDRDQSC_dm_m = 0x00000003, ++ DDRDQSC_dqsbs_b = 2, ++ DDRDQSC_dqsbs_m = 0x000000fc, ++ DDRDQSC_db_b = 8, ++ DDRDQSC_db_m = 0x00000100, ++ DDRDQSC_dbsp_b = 9, ++ DDRDQSC_dbsp_m = 0x01fffe00, ++ DDRDQSC_bdp_b = 25, ++ DDRDQSC_bdp_m = 0x7e000000, ++ ++ DDRDLLC_eao_b = 0, ++ DDRDLLC_eao_m = 0x00000001, ++ DDRDLLC_eo_b = 1, ++ DDRDLLC_eo_m = 0x0000003e, ++ DDRDLLC_fs_b = 6, ++ DDRDLLC_fs_m = 0x000000c0, ++ DDRDLLC_as_b = 8, ++ DDRDLLC_as_m = 0x00000700, ++ DDRDLLC_sp_b = 11, ++ DDRDLLC_sp_m = 0x001ff800, ++ ++ DDRDLLFC_men_b = 0, ++ DDRDLLFC_men_m = 0x00000001, ++ DDRDLLFC_aen_b = 1, ++ DDRDLLFC_aen_m = 0x00000002, ++ DDRDLLFC_ff_b = 2, ++ DDRDLLFC_ff_m = 0x00000004, ++ ++ DDRDLLTA_addr_b = 2, ++ DDRDLLTA_addr_m = 0xfffffffc, ++ ++ DDRDLLED_dbe_b = 0, ++ DDRDLLED_dbe_m = 0x00000001, ++ DDRDLLED_dte_b = 1, ++ DDRDLLED_dte_m = 0x00000002, ++ ++ ++} ; ++ ++#endif // __IDT_DDR_H__ +diff -urN linux.old/include/asm-mips/rc32434/dev.h linux.dev/include/asm-mips/rc32434/dev.h +--- linux.old/include/asm-mips/rc32434/dev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/dev.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,134 @@ ++#ifndef __IDT_DEV_H__ ++#define __IDT_DEV_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Device Controller register definition. ++ * ++ * File : $Id: dev.h,v 1.2 2002/06/06 18:34:03 astichte Exp $ ++ * ++ * Author : John.Ahrens@idt.com ++ * Date : 200112013 ++ * Update : ++ * $Log: dev.h,v $ ++ * Revision 1.2 2002/06/06 18:34:03 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.1 2002/05/29 17:33:21 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ DEV0_PhysicalAddress = 0x18010000, ++ DEV_PhysicalAddress = DEV0_PhysicalAddress, // Default ++ ++ DEV0_VirtualAddress = 0xb8010000, ++ DEV_VirtualAddress = DEV0_VirtualAddress, // Default ++} ; ++ ++typedef struct DEVICE_s ++{ ++ U32 devbase ; // Device Base ++ U32 devmask ; // Device Mask ++ U32 devc ; // Device Control ++ U32 devtc ; // Device Timing Control ++} volatile *DEVICE_t ; ++ ++enum ++{ ++ DEV_Count = 3, ++} ; ++ ++typedef struct DEV_s ++{ ++ struct DEVICE_s dev [DEV_Count] ; ++ U32 btcs ; // Bus timeout control / status ++ U32 btcompare ; // Compare ++ U32 btaddr ; // Timeout address. ++ U32 devdacs ; // Decoupled access control. ++ U32 devdaa ; // Decoupled access address. ++ U32 devdad ; // Decoupled access address. ++ U32 devspare ; // spare. ++} volatile *DEV_t ; ++ ++enum ++{ ++ DEVBASE_baseaddr_b = 16, ++ DEVBASE_baseaddr_m = 0xffff0000, ++ DEVMASK_mask_b = 16, ++ DEVMASK_mask_m = 0xffff0000, ++ ++ DEVC_ds_b = 0, ++ DEVC_ds_m = 0x00000003, ++ DEVC_ds_8_v = 0, // 8-bit device. ++ DEVC_ds_16_v = 1, // reserved ++ DEVC_ds_res_v = 2, // reserved. ++ DEVC_ds_res2_v = 3, // reserved. ++ DEVC_be_b = 2, ++ DEVC_be_m = 0x00000004, ++ DEVC_wp_b = 3, ++ DEVC_wp_m = 0x00000008, ++ DEVC_csd_b = 4, ++ DEVC_csd_m = 0x000000f0, ++ DEVC_oed_b = 8, ++ DEVC_oed_m = 0x00000f00, ++ DEVC_bwd_b = 12, ++ DEVC_bwd_m = 0x0000f000, ++ DEVC_rws_b = 16, ++ DEVC_rws_m = 0x003f0000, ++ DEVC_wws_b = 22, ++ DEVC_wws_m = 0x0fc00000, ++ DEVC_bre_b = 28, ++ DEVC_bre_m = 0x10000000, ++ DEVC_bwe_b = 29, ++ DEVC_bwe_m = 0x20000000, ++ DEVC_wam_b = 30, ++ DEVC_wam_m = 0x40000000, ++ ++ DEVTC_prd_b = 0, ++ DEVTC_prd_m = 0x0000000f, ++ DEVTC_pwd_b = 4, ++ DEVTC_pwd_m = 0x000000f0, ++ DEVTC_wdh_b = 8, ++ DEVTC_wdh_m = 0x00000700, ++ DEVTC_csh_b = 11, ++ DEVTC_csh_m = 0x00001800, ++ ++ BTCS_tt_b = 0, ++ BTCS_tt_m = 0x00000001, ++ BTCS_tt_write = 0, ++ BTCS_tt_read = 1, ++ BTCS_bto_b = 1, // In btcs ++ BTCS_bto_m = 0x00000002, // In btcs ++ BTCS_bte_b = 2, // In btcs ++ BTCS_bte_m = 0x00000004, // In btcs ++ ++ BTCOMPARE_compare_b = 0, // In btcompare ++ BTCOMPARE_compare_m = 0x0000ffff, // In btcompare ++ ++ DEVDACS_op_b = 0, // In devdacs ++ DEVDACS_op_m = 0x00000001, // In devdacs ++ DEVDACS_op_write_v = 0, ++ DEVDACS_op_read_v = 1, ++ DEVDACS_size_b = 1, // In devdacs ++ DEVDACS_size_m = 0x00000006, // In devdacs ++ DEVDACS_size_byte_v = 0, ++ DEVDACS_size_halfword = 1, ++ DEVDACS_size_triplebyte = 2, ++ DEVDACS_size_word = 3, ++ DEVDACS_err_b = 3, // In devdacs ++ DEVDACS_err_m = 0x00000008, // In devdacs ++ DEVDACS_f_b = 4, // In devdacs ++ DEVDACS_f_m = 0x00000010, // In devdacs ++} ; ++ ++#endif //__IDT_DEV_H__ ++ +diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h +--- linux.old/include/asm-mips/rc32434/dma.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/dma.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,202 @@ ++#ifndef __IDT_DMA_H__ ++#define __IDT_DMA_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * DMA register definition. ++ * ++ * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $ ++ * ++ * Author : ryan.holmQVist@idt.com ++ * Date : 20011005 ++ * Update : ++ * $Log: dma.h,v $ ++ * Revision 1.3 2002/06/06 18:34:03 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.2 2002/06/05 18:30:46 astichte ++ * Removed IDTField ++ * ++ * Revision 1.1 2002/05/29 17:33:21 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++enum ++{ ++ DMA0_PhysicalAddress = 0x18040000, ++ DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default ++ ++ DMA0_VirtualAddress = 0xb8040000, ++ DMA_VirtualAddress = DMA0_VirtualAddress, // Default ++} ; ++ ++/* ++ * DMA descriptor (in physical memory). ++ */ ++ ++typedef struct DMAD_s ++{ ++ U32 control ; // Control. use DMAD_* ++ U32 ca ; // Current Address. ++ U32 devcs ; // Device control and status. ++ U32 link ; // Next descriptor in chain. ++} volatile *DMAD_t ; ++ ++enum ++{ ++ DMAD_size = sizeof (struct DMAD_s), ++ DMAD_count_b = 0, // in DMAD_t -> control ++ DMAD_count_m = 0x0003ffff, // in DMAD_t -> control ++ DMAD_ds_b = 20, // in DMAD_t -> control ++ DMAD_ds_m = 0x00300000, // in DMAD_t -> control ++ DMAD_ds_ethRcv_v = 0, ++ DMAD_ds_ethXmt_v = 0, ++ DMAD_ds_memToFifo_v = 0, ++ DMAD_ds_fifoToMem_v = 0, ++ DMAD_ds_pciToMem_v = 0, ++ DMAD_ds_memToPci_v = 0, ++ ++ DMAD_devcmd_b = 22, // in DMAD_t -> control ++ DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control ++ DMAD_devcmd_byte_v = 0, //memory-to-memory ++ DMAD_devcmd_halfword_v = 1, //memory-to-memory ++ DMAD_devcmd_word_v = 2, //memory-to-memory ++ DMAD_devcmd_2words_v = 3, //memory-to-memory ++ DMAD_devcmd_4words_v = 4, //memory-to-memory ++ DMAD_devcmd_6words_v = 5, //memory-to-memory ++ DMAD_devcmd_8words_v = 6, //memory-to-memory ++ DMAD_devcmd_16words_v = 7, //memory-to-memory ++ DMAD_cof_b = 25, // chain on finished ++ DMAD_cof_m = 0x02000000, // ++ DMAD_cod_b = 26, // chain on done ++ DMAD_cod_m = 0x04000000, // ++ DMAD_iof_b = 27, // interrupt on finished ++ DMAD_iof_m = 0x08000000, // ++ DMAD_iod_b = 28, // interrupt on done ++ DMAD_iod_m = 0x10000000, // ++ DMAD_t_b = 29, // terminated ++ DMAD_t_m = 0x20000000, // ++ DMAD_d_b = 30, // done ++ DMAD_d_m = 0x40000000, // ++ DMAD_f_b = 31, // finished ++ DMAD_f_m = 0x80000000, // ++} ; ++ ++/* ++ * DMA register (within Internal Register Map). ++ */ ++ ++struct DMA_Chan_s ++{ ++ U32 dmac ; // Control. ++ U32 dmas ; // Status. ++ U32 dmasm ; // Mask. ++ U32 dmadptr ; // Descriptor pointer. ++ U32 dmandptr ; // Next descriptor pointer. ++}; ++ ++typedef struct DMA_Chan_s volatile *DMA_Chan_t ; ++ ++//DMA_Channels use DMACH_count instead ++ ++enum ++{ ++ DMAC_run_b = 0, // ++ DMAC_run_m = 0x00000001, // ++ DMAC_dm_b = 1, // done mask ++ DMAC_dm_m = 0x00000002, // ++ DMAC_mode_b = 2, // ++ DMAC_mode_m = 0x0000000c, // ++ DMAC_mode_auto_v = 0, ++ DMAC_mode_burst_v = 1, ++ DMAC_mode_transfer_v = 2, //usually used ++ DMAC_mode_reserved_v = 3, ++ DMAC_a_b = 4, // ++ DMAC_a_m = 0x00000010, // ++ ++ DMAS_f_b = 0, // finished (sticky) ++ DMAS_f_m = 0x00000001, // ++ DMAS_d_b = 1, // done (sticky) ++ DMAS_d_m = 0x00000002, // ++ DMAS_c_b = 2, // chain (sticky) ++ DMAS_c_m = 0x00000004, // ++ DMAS_e_b = 3, // error (sticky) ++ DMAS_e_m = 0x00000008, // ++ DMAS_h_b = 4, // halt (sticky) ++ DMAS_h_m = 0x00000010, // ++ ++ DMASM_f_b = 0, // finished (1=mask) ++ DMASM_f_m = 0x00000001, // ++ DMASM_d_b = 1, // done (1=mask) ++ DMASM_d_m = 0x00000002, // ++ DMASM_c_b = 2, // chain (1=mask) ++ DMASM_c_m = 0x00000004, // ++ DMASM_e_b = 3, // error (1=mask) ++ DMASM_e_m = 0x00000008, // ++ DMASM_h_b = 4, // halt (1=mask) ++ DMASM_h_m = 0x00000010, // ++} ; ++ ++/* ++ * DMA channel definitions ++ */ ++ ++enum ++{ ++ DMACH_ethRcv = 0, ++ DMACH_ethXmt = 1, ++ DMACH_memToFifo = 2, ++ DMACH_fifoToMem = 3, ++ DMACH_pciToMem = 4, ++ DMACH_memToPci = 5, ++ ++ DMACH_count //must be last ++}; ++ ++ ++typedef struct DMAC_s ++{ ++ struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_] ++} volatile *DMA_t ; ++ ++ ++/* ++ * External DMA parameters ++*/ ++#if 0 ++enum ++{ ++ DMADEVCMD_ts_b = 0, // ts field in devcmd ++ DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd ++ DMADEVCMD_ts_byte_v = 0, ++ DMADEVCMD_ts_halfword_v = 1, ++ DMADEVCMD_ts_word_v = 2, ++ DMADEVCMD_ts_2word_v = 3, ++ DMADEVCMD_ts_4word_v = 4, ++ DMADEVCMD_ts_6word_v = 5, ++ DMADEVCMD_ts_8word_v = 6, ++ DMADEVCMD_ts_16word_v = 7 ++}; ++#endif ++ ++#if 1 // aws - Compatibility. ++# define EXTDMA_ts_b DMADEVCMD_ts_b ++# define EXTDMA_ts_m DMADEVCMD_ts_m ++# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v ++# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v ++# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v ++# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v ++# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v ++# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v ++# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v ++# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v ++#endif // aws - Compatibility. ++ ++#endif // __IDT_DMA_H__ ++ +diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h +--- linux.old/include/asm-mips/rc32434/dma_v.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/dma_v.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,73 @@ ++#ifndef __IDT_DMA_V_H__ ++#define __IDT_DMA_V_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * DMA register definition. ++ * ++ * File : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $ ++ * ++ * Author : ryan.holmQVist@idt.com ++ * Date : 20011005 ++ * Update : ++ * $Log: dma.h,v $ ++ * Revision 1.3 2002/06/06 18:34:03 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.2 2002/06/05 18:30:46 astichte ++ * Removed IDTField ++ * ++ * Revision 1.1 2002/05/29 17:33:21 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++#include <asm/rc32434/types.h> ++#include <asm/rc32434/dma.h> ++#include <asm/rc32434/rc32434.h> ++#define DMA_CHAN_OFFSET 0x14 ++#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0) ++#define DMA_COUNT(count) \ ++ ((count) & DMAD_count_m) ++ ++#define DMA_HALT_TIMEOUT 500 ++ ++ ++static inline int rc32434_halt_dma(DMA_Chan_t ch) ++{ ++ int timeout=1; ++ if (local_readl(&ch->dmac) & DMAC_run_m) { ++ local_writel(0, &ch->dmac); ++ for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) { ++ if (local_readl(&ch->dmas) & DMAS_h_m) { ++ local_writel(0, &ch->dmas); ++ break; ++ } ++ } ++ } ++ ++ return timeout ? 0 : 1; ++} ++ ++static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr) ++{ ++ local_writel(0, &ch->dmandptr); ++ local_writel(dma_addr, &ch->dmadptr); ++} ++ ++static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr) ++{ ++ local_writel(dma_addr, &ch->dmandptr); ++} ++ ++#endif // __IDT_DMA_V_H__ ++ ++ ++ ++ ++ ++ ++ +diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h +--- linux.old/include/asm-mips/rc32434/eth.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/eth.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,322 @@ ++#ifndef __IDT_ETH_H__ ++#define __IDT_ETH_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Ethernet register definition. ++ * ++ * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020605 ++ * Update : ++ * $Log: eth.h,v $ ++ * Revision 1.3 2002/06/06 18:34:04 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.2 2002/06/05 18:19:46 astichte ++ * Added ++ * ++ * Revision 1.1 2002/05/29 17:33:22 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ ETH0_PhysicalAddress = 0x18060000, ++ ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default ++ ++ ETH0_VirtualAddress = 0xb8060000, ++ ETH_VirtualAddress = ETH0_VirtualAddress, // Default ++} ; ++ ++typedef struct ++{ ++ U32 ethintfc ; ++ U32 ethfifott ; ++ U32 etharc ; ++ U32 ethhash0 ; ++ U32 ethhash1 ; ++ U32 ethu0 [4] ; // Reserved. ++ U32 ethpfs ; ++ U32 ethmcp ; ++ U32 eth_u1 [10] ; // Reserved. ++ U32 ethspare ; ++ U32 eth_u2 [42] ; // Reserved. ++ U32 ethsal0 ; ++ U32 ethsah0 ; ++ U32 ethsal1 ; ++ U32 ethsah1 ; ++ U32 ethsal2 ; ++ U32 ethsah2 ; ++ U32 ethsal3 ; ++ U32 ethsah3 ; ++ U32 ethrbc ; ++ U32 ethrpc ; ++ U32 ethrupc ; ++ U32 ethrfc ; ++ U32 ethtbc ; ++ U32 ethgpf ; ++ U32 eth_u9 [50] ; // Reserved. ++ U32 ethmac1 ; ++ U32 ethmac2 ; ++ U32 ethipgt ; ++ U32 ethipgr ; ++ U32 ethclrt ; ++ U32 ethmaxf ; ++ U32 eth_u10 ; // Reserved. ++ U32 ethmtest ; ++ U32 miimcfg ; ++ U32 miimcmd ; ++ U32 miimaddr ; ++ U32 miimwtd ; ++ U32 miimrdd ; ++ U32 miimind ; ++ U32 eth_u11 ; // Reserved. ++ U32 eth_u12 ; // Reserved. ++ U32 ethcfsa0 ; ++ U32 ethcfsa1 ; ++ U32 ethcfsa2 ; ++} volatile *ETH_t; ++ ++enum ++{ ++ ETHINTFC_en_b = 0, ++ ETHINTFC_en_m = 0x00000001, ++ ETHINTFC_its_b = 1, ++ ETHINTFC_its_m = 0x00000002, ++ ETHINTFC_rip_b = 2, ++ ETHINTFC_rip_m = 0x00000004, ++ ETHINTFC_jam_b = 3, ++ ETHINTFC_jam_m = 0x00000008, ++ ETHINTFC_ovr_b = 4, ++ ETHINTFC_ovr_m = 0x00000010, ++ ETHINTFC_und_b = 5, ++ ETHINTFC_und_m = 0x00000020, ++ ETHINTFC_iom_b = 6, ++ ETHINTFC_iom_m = 0x000000c0, ++ ++ ETHFIFOTT_tth_b = 0, ++ ETHFIFOTT_tth_m = 0x0000007f, ++ ++ ETHARC_pro_b = 0, ++ ETHARC_pro_m = 0x00000001, ++ ETHARC_am_b = 1, ++ ETHARC_am_m = 0x00000002, ++ ETHARC_afm_b = 2, ++ ETHARC_afm_m = 0x00000004, ++ ETHARC_ab_b = 3, ++ ETHARC_ab_m = 0x00000008, ++ ++ ETHSAL_byte5_b = 0, ++ ETHSAL_byte5_m = 0x000000ff, ++ ETHSAL_byte4_b = 8, ++ ETHSAL_byte4_m = 0x0000ff00, ++ ETHSAL_byte3_b = 16, ++ ETHSAL_byte3_m = 0x00ff0000, ++ ETHSAL_byte2_b = 24, ++ ETHSAL_byte2_m = 0xff000000, ++ ++ ETHSAH_byte1_b = 0, ++ ETHSAH_byte1_m = 0x000000ff, ++ ETHSAH_byte0_b = 8, ++ ETHSAH_byte0_m = 0x0000ff00, ++ ++ ETHGPF_ptv_b = 0, ++ ETHGPF_ptv_m = 0x0000ffff, ++ ++ ETHPFS_pfd_b = 0, ++ ETHPFS_pfd_m = 0x00000001, ++ ++ ETHCFSA0_cfsa4_b = 0, ++ ETHCFSA0_cfsa4_m = 0x000000ff, ++ ETHCFSA0_cfsa5_b = 8, ++ ETHCFSA0_cfsa5_m = 0x0000ff00, ++ ++ ETHCFSA1_cfsa2_b = 0, ++ ETHCFSA1_cfsa2_m = 0x000000ff, ++ ETHCFSA1_cfsa3_b = 8, ++ ETHCFSA1_cfsa3_m = 0x0000ff00, ++ ++ ETHCFSA2_cfsa0_b = 0, ++ ETHCFSA2_cfsa0_m = 0x000000ff, ++ ETHCFSA2_cfsa1_b = 8, ++ ETHCFSA2_cfsa1_m = 0x0000ff00, ++ ++ ETHMAC1_re_b = 0, ++ ETHMAC1_re_m = 0x00000001, ++ ETHMAC1_paf_b = 1, ++ ETHMAC1_paf_m = 0x00000002, ++ ETHMAC1_rfc_b = 2, ++ ETHMAC1_rfc_m = 0x00000004, ++ ETHMAC1_tfc_b = 3, ++ ETHMAC1_tfc_m = 0x00000008, ++ ETHMAC1_lb_b = 4, ++ ETHMAC1_lb_m = 0x00000010, ++ ETHMAC1_mr_b = 31, ++ ETHMAC1_mr_m = 0x80000000, ++ ++ ETHMAC2_fd_b = 0, ++ ETHMAC2_fd_m = 0x00000001, ++ ETHMAC2_flc_b = 1, ++ ETHMAC2_flc_m = 0x00000002, ++ ETHMAC2_hfe_b = 2, ++ ETHMAC2_hfe_m = 0x00000004, ++ ETHMAC2_dc_b = 3, ++ ETHMAC2_dc_m = 0x00000008, ++ ETHMAC2_cen_b = 4, ++ ETHMAC2_cen_m = 0x00000010, ++ ETHMAC2_pe_b = 5, ++ ETHMAC2_pe_m = 0x00000020, ++ ETHMAC2_vpe_b = 6, ++ ETHMAC2_vpe_m = 0x00000040, ++ ETHMAC2_ape_b = 7, ++ ETHMAC2_ape_m = 0x00000080, ++ ETHMAC2_ppe_b = 8, ++ ETHMAC2_ppe_m = 0x00000100, ++ ETHMAC2_lpe_b = 9, ++ ETHMAC2_lpe_m = 0x00000200, ++ ETHMAC2_nb_b = 12, ++ ETHMAC2_nb_m = 0x00001000, ++ ETHMAC2_bp_b = 13, ++ ETHMAC2_bp_m = 0x00002000, ++ ETHMAC2_ed_b = 14, ++ ETHMAC2_ed_m = 0x00004000, ++ ++ ETHIPGT_ipgt_b = 0, ++ ETHIPGT_ipgt_m = 0x0000007f, ++ ++ ETHIPGR_ipgr2_b = 0, ++ ETHIPGR_ipgr2_m = 0x0000007f, ++ ETHIPGR_ipgr1_b = 8, ++ ETHIPGR_ipgr1_m = 0x00007f00, ++ ++ ETHCLRT_maxret_b = 0, ++ ETHCLRT_maxret_m = 0x0000000f, ++ ETHCLRT_colwin_b = 8, ++ ETHCLRT_colwin_m = 0x00003f00, ++ ++ ETHMAXF_maxf_b = 0, ++ ETHMAXF_maxf_m = 0x0000ffff, ++ ++ ETHMTEST_tb_b = 2, ++ ETHMTEST_tb_m = 0x00000004, ++ ++ ETHMCP_div_b = 0, ++ ETHMCP_div_m = 0x000000ff, ++ ++ MIIMCFG_rsv_b = 0, ++ MIIMCFG_rsv_m = 0x0000000c, ++ ++ MIIMCMD_rd_b = 0, ++ MIIMCMD_rd_m = 0x00000001, ++ MIIMCMD_scn_b = 1, ++ MIIMCMD_scn_m = 0x00000002, ++ ++ MIIMADDR_regaddr_b = 0, ++ MIIMADDR_regaddr_m = 0x0000001f, ++ MIIMADDR_phyaddr_b = 8, ++ MIIMADDR_phyaddr_m = 0x00001f00, ++ ++ MIIMWTD_wdata_b = 0, ++ MIIMWTD_wdata_m = 0x0000ffff, ++ ++ MIIMRDD_rdata_b = 0, ++ MIIMRDD_rdata_m = 0x0000ffff, ++ ++ MIIMIND_bsy_b = 0, ++ MIIMIND_bsy_m = 0x00000001, ++ MIIMIND_scn_b = 1, ++ MIIMIND_scn_m = 0x00000002, ++ MIIMIND_nv_b = 2, ++ MIIMIND_nv_m = 0x00000004, ++ ++} ; ++ ++/* ++ * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors. ++ */ ++enum ++{ ++ ETHRX_fd_b = 0, ++ ETHRX_fd_m = 0x00000001, ++ ETHRX_ld_b = 1, ++ ETHRX_ld_m = 0x00000002, ++ ETHRX_rok_b = 2, ++ ETHRX_rok_m = 0x00000004, ++ ETHRX_fm_b = 3, ++ ETHRX_fm_m = 0x00000008, ++ ETHRX_mp_b = 4, ++ ETHRX_mp_m = 0x00000010, ++ ETHRX_bp_b = 5, ++ ETHRX_bp_m = 0x00000020, ++ ETHRX_vlt_b = 6, ++ ETHRX_vlt_m = 0x00000040, ++ ETHRX_cf_b = 7, ++ ETHRX_cf_m = 0x00000080, ++ ETHRX_ovr_b = 8, ++ ETHRX_ovr_m = 0x00000100, ++ ETHRX_crc_b = 9, ++ ETHRX_crc_m = 0x00000200, ++ ETHRX_cv_b = 10, ++ ETHRX_cv_m = 0x00000400, ++ ETHRX_db_b = 11, ++ ETHRX_db_m = 0x00000800, ++ ETHRX_le_b = 12, ++ ETHRX_le_m = 0x00001000, ++ ETHRX_lor_b = 13, ++ ETHRX_lor_m = 0x00002000, ++ ETHRX_ces_b = 14, ++ ETHRX_ces_m = 0x00004000, ++ ETHRX_length_b = 16, ++ ETHRX_length_m = 0xffff0000, ++ ++ ETHTX_fd_b = 0, ++ ETHTX_fd_m = 0x00000001, ++ ETHTX_ld_b = 1, ++ ETHTX_ld_m = 0x00000002, ++ ETHTX_oen_b = 2, ++ ETHTX_oen_m = 0x00000004, ++ ETHTX_pen_b = 3, ++ ETHTX_pen_m = 0x00000008, ++ ETHTX_cen_b = 4, ++ ETHTX_cen_m = 0x00000010, ++ ETHTX_hen_b = 5, ++ ETHTX_hen_m = 0x00000020, ++ ETHTX_tok_b = 6, ++ ETHTX_tok_m = 0x00000040, ++ ETHTX_mp_b = 7, ++ ETHTX_mp_m = 0x00000080, ++ ETHTX_bp_b = 8, ++ ETHTX_bp_m = 0x00000100, ++ ETHTX_und_b = 9, ++ ETHTX_und_m = 0x00000200, ++ ETHTX_of_b = 10, ++ ETHTX_of_m = 0x00000400, ++ ETHTX_ed_b = 11, ++ ETHTX_ed_m = 0x00000800, ++ ETHTX_ec_b = 12, ++ ETHTX_ec_m = 0x00001000, ++ ETHTX_lc_b = 13, ++ ETHTX_lc_m = 0x00002000, ++ ETHTX_td_b = 14, ++ ETHTX_td_m = 0x00004000, ++ ETHTX_crc_b = 15, ++ ETHTX_crc_m = 0x00008000, ++ ETHTX_le_b = 16, ++ ETHTX_le_m = 0x00010000, ++ ETHTX_cc_b = 17, ++ ETHTX_cc_m = 0x001E0000, ++} ; ++ ++#endif // __IDT_ETH_H__ ++ ++ ++ ++ +diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h +--- linux.old/include/asm-mips/rc32434/eth_v.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/eth_v.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,64 @@ ++#ifndef __IDT_ETH_V_H__ ++#define __IDT_ETH_V_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Ethernet register definition. ++ * ++ * File : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020605 ++ * Update : ++ * $Log: eth.h,v $ ++ * Revision 1.3 2002/06/06 18:34:04 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.2 2002/06/05 18:19:46 astichte ++ * Added ++ * ++ * Revision 1.1 2002/05/29 17:33:22 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++#include <asm/rc32434/eth.h> ++ ++#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */ ++#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */ ++#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */ ++#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */ ++#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */ ++#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */ ++#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */ ++#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */ ++#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/ ++#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */ ++#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */ ++ ++#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */ ++ ++#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */ ++#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */ ++#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */ ++#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */ ++#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */ ++#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */ ++#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */ ++#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */ ++#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */ ++#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */ ++#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */ ++#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */ ++#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */ ++#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */ ++#endif // __IDT_ETH_V_H__ ++ ++ ++ ++ ++ +diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h +--- linux.old/include/asm-mips/rc32434/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/gpio.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,182 @@ ++#ifndef __IDT_GPIO_H__ ++#define __IDT_GPIO_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * GPIO register definition. ++ * ++ * File : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $ ++ * ++ * Author : ryan.holmQVist@idt.com ++ * Date : 20011005 ++ * Update : ++ * $Log: gpio.h,v $ ++ * Revision 1.2 2002/06/06 18:34:04 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.1 2002/05/29 17:33:22 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++enum ++{ ++ GPIO0_PhysicalAddress = 0x18050000, ++ GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default ++ ++ GPIO0_VirtualAddress = 0xb8050000, ++ GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default ++} ; ++ ++typedef struct ++{ ++ U32 gpiofunc; /* GPIO Function Register ++ * gpiofunc[x]==0 bit = gpio ++ * func[x]==1 bit = altfunc ++ */ ++ U32 gpiocfg; /* GPIO Configuration Register ++ * gpiocfg[x]==0 bit = input ++ * gpiocfg[x]==1 bit = output ++ */ ++ U32 gpiod; /* GPIO Data Register ++ * gpiod[x] read/write gpio pinX status ++ */ ++ U32 gpioilevel; /* GPIO Interrupt Status Register ++ * interrupt level (see gpioistat) ++ */ ++ U32 gpioistat; /* Gpio Interrupt Status Register ++ * istat[x] = (gpiod[x] == level[x]) ++ * cleared in ISR (STICKY bits) ++ */ ++ U32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */ ++} volatile * GPIO_t ; ++ ++typedef enum ++{ ++ GPIO_gpio_v = 0, // gpiofunc use pin as GPIO. ++ GPIO_alt_v = 1, // gpiofunc use pin as alt. ++ GPIO_input_v = 0, // gpiocfg use pin as input. ++ GPIO_output_v = 1, // gpiocfg use pin as output. ++ GPIO_pin0_b = 0, ++ GPIO_pin0_m = 0x00000001, ++ GPIO_pin1_b = 1, ++ GPIO_pin1_m = 0x00000002, ++ GPIO_pin2_b = 2, ++ GPIO_pin2_m = 0x00000004, ++ GPIO_pin3_b = 3, ++ GPIO_pin3_m = 0x00000008, ++ GPIO_pin4_b = 4, ++ GPIO_pin4_m = 0x00000010, ++ GPIO_pin5_b = 5, ++ GPIO_pin5_m = 0x00000020, ++ GPIO_pin6_b = 6, ++ GPIO_pin6_m = 0x00000040, ++ GPIO_pin7_b = 7, ++ GPIO_pin7_m = 0x00000080, ++ GPIO_pin8_b = 8, ++ GPIO_pin8_m = 0x00000100, ++ GPIO_pin9_b = 9, ++ GPIO_pin9_m = 0x00000200, ++ GPIO_pin10_b = 10, ++ GPIO_pin10_m = 0x00000400, ++ GPIO_pin11_b = 11, ++ GPIO_pin11_m = 0x00000800, ++ GPIO_pin12_b = 12, ++ GPIO_pin12_m = 0x00001000, ++ GPIO_pin13_b = 13, ++ GPIO_pin13_m = 0x00002000, ++ GPIO_pin14_b = 14, ++ GPIO_pin14_m = 0x00004000, ++ GPIO_pin15_b = 15, ++ GPIO_pin15_m = 0x00008000, ++ GPIO_pin16_b = 16, ++ GPIO_pin16_m = 0x00010000, ++ GPIO_pin17_b = 17, ++ GPIO_pin17_m = 0x00020000, ++ GPIO_pin18_b = 18, ++ GPIO_pin18_m = 0x00040000, ++ GPIO_pin19_b = 19, ++ GPIO_pin19_m = 0x00080000, ++ GPIO_pin20_b = 20, ++ GPIO_pin20_m = 0x00100000, ++ GPIO_pin21_b = 21, ++ GPIO_pin21_m = 0x00200000, ++ GPIO_pin22_b = 22, ++ GPIO_pin22_m = 0x00400000, ++ GPIO_pin23_b = 23, ++ GPIO_pin23_m = 0x00800000, ++ GPIO_pin24_b = 24, ++ GPIO_pin24_m = 0x01000000, ++ GPIO_pin25_b = 25, ++ GPIO_pin25_m = 0x02000000, ++ GPIO_pin26_b = 26, ++ GPIO_pin26_m = 0x04000000, ++ GPIO_pin27_b = 27, ++ GPIO_pin27_m = 0x08000000, ++ GPIO_pin28_b = 28, ++ GPIO_pin28_m = 0x10000000, ++ GPIO_pin29_b = 29, ++ GPIO_pin29_m = 0x20000000, ++ GPIO_pin30_b = 30, ++ GPIO_pin30_m = 0x40000000, ++ GPIO_pin31_b = 31, ++ GPIO_pin31_m = 0x80000000, ++ ++// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v. ++ ++ GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out. ++ GPIO_u0sout_m = GPIO_pin0_m, ++ GPIO_u0sout_cfg_v = GPIO_output_v, ++ GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in. ++ GPIO_u0sinp_m = GPIO_pin1_m, ++ GPIO_u0sinp_cfg_v = GPIO_input_v, ++ GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send. ++ GPIO_u0rtsn_m = GPIO_pin2_m, ++ GPIO_u0rtsn_cfg_v = GPIO_output_v, ++ GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send. ++ GPIO_u0ctsn_m = GPIO_pin3_m, ++ GPIO_u0ctsn_cfg_v = GPIO_input_v, ++ GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22. ++ GPIO_maddr22_m = GPIO_pin4_m, ++ GPIO_maddr22_cfg_v = GPIO_output_v, ++ ++ GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23. ++ GPIO_maddr23_m = GPIO_pin5_m, ++ GPIO_maddr23_cfg_v = GPIO_output_v, ++ ++ GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24. ++ GPIO_maddr24_m = GPIO_pin6_m, ++ GPIO_maddr24_cfg_v = GPIO_output_v, ++ ++ GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25. ++ GPIO_maddr25_m = GPIO_pin7_m, ++ GPIO_maddr25_cfg_v = GPIO_output_v, ++ ++ GPIO_cpu_b = GPIO_pin8_b, // M&P bus bit 25. ++ GPIO_cpu_m = GPIO_pin8_m, ++ GPIO_cpu_cfg_v = GPIO_output_v, ++ GPIO_afspare6_b = GPIO_pin9_b, // reserved. ++ GPIO_afspare6_m = GPIO_pin9_m, ++ GPIO_afspare6_cfg_v = GPIO_input_v, ++ GPIO_afspare4_b = GPIO_pin10_b, // reserved. ++ GPIO_afspare4_m = GPIO_pin10_m, ++ GPIO_afspare4_cfg_v = GPIO_input_v, ++ GPIO_afspare3_b = GPIO_pin11_b, // reserved. ++ GPIO_afspare3_m = GPIO_pin11_m, ++ GPIO_afspare3_cfg_v = GPIO_input_v, ++ GPIO_afspare2_b = GPIO_pin12_b, // reserved. ++ GPIO_afspare2_m = GPIO_pin12_m, ++ GPIO_afspare2_cfg_v = GPIO_input_v, ++ GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int. ++ GPIO_pcimuintn_m = GPIO_pin13_m, ++ GPIO_pcimuintn_cfg_v = GPIO_output_v, ++ ++} GPIO_DEFS_t; ++ ++#endif // __IDT_GPIO_H__ ++ +diff -urN linux.old/include/asm-mips/rc32434/i2c.h linux.dev/include/asm-mips/rc32434/i2c.h +--- linux.old/include/asm-mips/rc32434/i2c.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/i2c.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,147 @@ ++#ifndef __IDT_I2C_H__ ++#define __IDT_I2C_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * I2C register definitions. ++ * ++ * File : $Id: i2c.h,v 1.2 2002/06/06 18:34:04 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020120 ++ * Update : ++ * $Log: i2c.h,v $ ++ * Revision 1.2 2002/06/06 18:34:04 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.1 2002/05/29 17:33:22 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ I2C0_PhysicalAddress = 0x18068000, ++ I2C_PhysicalAddress = I2C0_PhysicalAddress, ++ ++ I2C0_VirtualAddress = 0xb8068000, ++ I2C_VirtualAddress = I2C0_VirtualAddress, ++} ; ++ ++typedef struct ++{ ++ U32 i2cc ; ++ U32 i2cdi ; ++ U32 i2cdo ; ++ U32 i2ccp ; // I2C clk = ICLK / div / 8 ++ U32 i2cmcmd ; ++ U32 i2cms ; ++ U32 i2cmsm ; ++ U32 i2css ; ++ U32 i2cssm ; ++ U32 i2csaddr ; ++ U32 i2csack ; ++} volatile * I2C_t ; ++enum ++{ ++ I2CC_men_b = 0, // In I2C-> i2cc ++ I2CC_men_m = 0x00000001, ++ I2CC_sen_b = 1, // In I2C-> i2cc ++ I2CC_sen_m = 0x00000002, ++ I2CC_iom_b = 2, // In I2C-> i2cc ++ I2CC_iom_m = 0x00000004, ++ ++ I2CDI_data_b = 0, // In I2C-> i2cdi ++ I2CDI_data_m = 0x000000ff, ++ ++ I2CDO_data_b = 0, // In I2C-> i2cdo ++ I2CDO_data_m = 0x000000ff, ++ ++ I2CCP_div_b = 0, // In I2C-> i2ccp ++ I2CCP_div_m = 0x0000ffff, ++ ++ I2CMCMD_cmd_b = 0, // In I2C-> i2cmcmd ++ I2CMCMD_cmd_m = 0x0000000f, ++ I2CMCMD_cmd_nop_v = 0, ++ I2CMCMD_cmd_start_v = 1, ++ I2CMCMD_cmd_stop_v = 2, ++ I2CMCMD_cmd_res3_v = 3, ++ I2CMCMD_cmd_rd_v = 4, ++ I2CMCMD_cmd_rdack_v = 5, ++ I2CMCMD_cmd_wd_v = 6, ++ I2CMCMD_cmd_wdack_v = 7, ++ I2CMCMD_cmd_res8_v = 8, ++ I2CMCMD_cmd_res9_v = 9, ++ I2CMCMD_cmd_res10_v = 10, ++ I2CMCMD_cmd_res11_v = 11, ++ I2CMCMD_cmd_res12_v = 12, ++ I2CMCMD_cmd_res13_v = 13, ++ I2CMCMD_cmd_res14_v = 14, ++ I2CMCMD_cmd_res15_v = 15, ++ ++ I2CMS_d_b = 0, // In I2C-> i2cms ++ I2CMS_d_m = 0x00000001, ++ I2CMS_na_b = 1, // In I2C-> i2cms ++ I2CMS_na_m = 0x00000002, ++ I2CMS_la_b = 2, // In I2C-> i2cms ++ I2CMS_la_m = 0x00000004, ++ I2CMS_err_b = 3, // In I2C-> i2cms ++ I2CMS_err_m = 0x00000008, ++ ++ I2CMSM_d_b = 0, // In I2C-> i2cmsm ++ I2CMSM_d_m = 0x00000001, ++ I2CMSM_na_b = 1, // In I2C-> i2cmsm ++ I2CMSM_na_m = 0x00000002, ++ I2CMSM_la_b = 2, // In I2C-> i2cmsm ++ I2CMSM_la_m = 0x00000004, ++ I2CMSM_err_b = 3, // In I2C-> i2cmsm ++ I2CMSM_err_m = 0x00000008, ++ ++ I2CSS_rr_b = 0, // In I2C-> i2css ++ I2CSS_rr_m = 0x00000001, ++ I2CSS_wr_b = 1, // In I2C-> i2css ++ I2CSS_wr_m = 0x00000002, ++ I2CSS_sa_b = 2, // In I2C-> i2css ++ I2CSS_sa_m = 0x00000004, ++ I2CSS_tf_b = 3, // In I2C-> i2css ++ I2CSS_tf_m = 0x00000008, ++ I2CSS_gc_b = 4, // In I2C-> i2css ++ I2CSS_gc_m = 0x00000010, ++ I2CSS_na_b = 5, // In I2C-> i2css ++ I2CSS_na_m = 0x00000020, ++ I2CSS_err_b = 6, // In I2C-> i2css ++ I2CSS_err_m = 0x00000040, ++ ++ I2CSSM_rr_b = 0, // In I2C-> i2cssm ++ I2CSSM_rr_m = 0x00000001, ++ I2CSSM_wr_b = 1, // In I2C-> i2cssm ++ I2CSSM_wr_m = 0x00000002, ++ I2CSSM_sa_b = 2, // In I2C-> i2cssm ++ I2CSSM_sa_m = 0x00000004, ++ I2CSSM_tf_b = 3, // In I2C-> i2cssm ++ I2CSSM_tf_m = 0x00000008, ++ I2CSSM_gc_b = 4, // In I2C-> i2cssm ++ I2CSSM_gc_m = 0x00000010, ++ I2CSSM_na_b = 5, // In I2C-> i2cssm ++ I2CSSM_na_m = 0x00000020, ++ I2CSSM_err_b = 6, // In I2C-> i2cssm ++ I2CSSM_err_m = 0x00000040, ++ ++ I2CSADDR_addr_b = 0, // In I2C-> i2csaddr ++ I2CSADDR_addr_m = 0x000003ff, ++ I2CSADDR_a_gc_b = 10, // In I2C-> i2csaddr ++ I2CSADDR_a_gc_m = 0x00000400, ++ I2CSADDR_a10_b = 11, // In I2C-> i2csaddr ++ I2CSADDR_a10_m = 0x00000800, ++ ++ I2CSACK_ack_b = 0, // In I2C-> i2csack ++ I2CSACK_ack_m = 0x00000001, ++ ++} ; ++#endif // __IDT_I2C_H__ +diff -urN linux.old/include/asm-mips/rc32434/integ.h linux.dev/include/asm-mips/rc32434/integ.h +--- linux.old/include/asm-mips/rc32434/integ.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/integ.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,78 @@ ++#ifndef __IDT_INTEG_H__ ++#define __IDT_INTEG_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * System Integrity register definition. ++ * ++ * File : $Id: integ.h,v 1.3 2002/06/06 18:34:04 astichte Exp $ ++ * ++ * Author : ryan.holmQVist@idt.com ++ * Date : 20011005 ++ * Update : ++ * $Log: integ.h,v $ ++ * Revision 1.3 2002/06/06 18:34:04 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.2 2002/06/05 18:32:33 astichte ++ * Removed IDTField ++ * ++ * Revision 1.1 2002/05/29 17:33:22 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ INTEG0_PhysicalAddress = 0x18030000, ++ INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default ++ ++ INTEG0_VirtualAddress = 0xb8030000, ++ INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default ++} ; ++ ++// if you are looing for CEA, try rst.h ++typedef struct ++{ ++ U32 filler [0xc] ; // 0x30 bytes unused. ++ U32 errcs ; // sticky use ERRCS_ ++ U32 wtcount ; // Watchdog timer count reg. ++ U32 wtcompare ; // Watchdog timer timeout value. ++ U32 wtc ; // Watchdog timer control. use WTC_ ++} volatile *INTEG_t ; ++ ++enum ++{ ++ ERRCS_wto_b = 0, // In INTEG_t -> errcs ++ ERRCS_wto_m = 0x00000001, ++ ERRCS_wne_b = 1, // In INTEG_t -> errcs ++ ERRCS_wne_m = 0x00000002, ++ ERRCS_ucw_b = 2, // In INTEG_t -> errcs ++ ERRCS_ucw_m = 0x00000004, ++ ERRCS_ucr_b = 3, // In INTEG_t -> errcs ++ ERRCS_ucr_m = 0x00000008, ++ ERRCS_upw_b = 4, // In INTEG_t -> errcs ++ ERRCS_upw_m = 0x00000010, ++ ERRCS_upr_b = 5, // In INTEG_t -> errcs ++ ERRCS_upr_m = 0x00000020, ++ ERRCS_udw_b = 6, // In INTEG_t -> errcs ++ ERRCS_udw_m = 0x00000040, ++ ERRCS_udr_b = 7, // In INTEG_t -> errcs ++ ERRCS_udr_m = 0x00000080, ++ ERRCS_sae_b = 8, // In INTEG_t -> errcs ++ ERRCS_sae_m = 0x00000100, ++ ERRCS_wre_b = 9, // In INTEG_t -> errcs ++ ERRCS_wre_m = 0x00000200, ++ ++ WTC_en_b = 0, // In INTEG_t -> wtc ++ WTC_en_m = 0x00000001, ++ WTC_to_b = 1, // In INTEG_t -> wtc ++ WTC_to_m = 0x00000002, ++} ; ++ ++#endif // __IDT_INTEG_H__ +diff -urN linux.old/include/asm-mips/rc32434/int.h linux.dev/include/asm-mips/rc32434/int.h +--- linux.old/include/asm-mips/rc32434/int.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/int.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,167 @@ ++#ifndef __IDT_INT_H__ ++#define __IDT_INT_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Interrupt Controller register definition. ++ * ++ * File : $Id: int.h,v 1.3 2002/06/06 18:34:04 astichte Exp $ ++ * ++ * Author : ryan.holmqvist@idt.com ++ * Date : 20011005 ++ * Update : ++ * $Log: int.h,v $ ++ * Revision 1.3 2002/06/06 18:34:04 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.2 2002/06/05 18:47:33 astichte ++ * Removed IDTField ++ * ++ * Revision 1.1 2002/05/29 17:33:22 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ INT0_PhysicalAddress = 0x18038000, ++ INT_PhysicalAddress = INT0_PhysicalAddress, // Default ++ ++ INT0_VirtualAddress = 0xb8038000, ++ INT_VirtualAddress = INT0_VirtualAddress, // Default ++} ; ++ ++struct INT_s ++{ ++ U32 ipend ; //Pending interrupts. use INT?_ ++ U32 itest ; //Test bits. use INT?_ ++ U32 imask ; //Interrupt disabled when set. use INT?_ ++} ; ++ ++enum ++{ ++ IPEND2 = 0, // HW 2 interrupt to core. use INT2_ ++ IPEND3 = 1, // HW 3 interrupt to core. use INT3_ ++ IPEND4 = 2, // HW 4 interrupt to core. use INT4_ ++ IPEND5 = 3, // HW 5 interrupt to core. use INT5_ ++ IPEND6 = 4, // HW 6 interrupt to core. use INT6_ ++ ++ IPEND_count, // must be last (used in loops) ++ IPEND_min = IPEND2 // min IPEND (used in loops) ++}; ++ ++typedef struct INTC_s ++{ ++ struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_ ++ U32 nmips ; // use NMIPS_ ++} volatile *INT_t ; ++ ++enum ++{ ++ INT2_timer0_b = 0, ++ INT2_timer0_m = 0x00000001, ++ INT2_timer1_b = 1, ++ INT2_timer1_m = 0x00000002, ++ INT2_timer2_b = 2, ++ INT2_timer2_m = 0x00000004, ++ INT2_refresh_b = 3, ++ INT2_refresh_m = 0x00000008, ++ INT2_watchdogTimeout_b = 4, ++ INT2_watchdogTimeout_m = 0x00000010, ++ INT2_undecodedCpuWrite_b = 5, ++ INT2_undecodedCpuWrite_m = 0x00000020, ++ INT2_undecodedCpuRead_b = 6, ++ INT2_undecodedCpuRead_m = 0x00000040, ++ INT2_undecodedPciWrite_b = 7, ++ INT2_undecodedPciWrite_m = 0x00000080, ++ INT2_undecodedPciRead_b = 8, ++ INT2_undecodedPciRead_m = 0x00000100, ++ INT2_undecodedDmaWrite_b = 9, ++ INT2_undecodedDmaWrite_m = 0x00000200, ++ INT2_undecodedDmaRead_b = 10, ++ INT2_undecodedDmaRead_m = 0x00000400, ++ INT2_ipBusSlaveAckError_b = 11, ++ INT2_ipBusSlaveAckError_m = 0x00000800, ++ ++ INT3_dmaChannel0_b = 0, ++ INT3_dmaChannel0_m = 0x00000001, ++ INT3_dmaChannel1_b = 1, ++ INT3_dmaChannel1_m = 0x00000002, ++ INT3_dmaChannel2_b = 2, ++ INT3_dmaChannel2_m = 0x00000004, ++ INT3_dmaChannel3_b = 3, ++ INT3_dmaChannel3_m = 0x00000008, ++ INT3_dmaChannel4_b = 4, ++ INT3_dmaChannel4_m = 0x00000010, ++ INT3_dmaChannel5_b = 5, ++ INT3_dmaChannel5_m = 0x00000020, ++ ++ INT5_uartGeneral0_b = 0, ++ INT5_uartGeneral0_m = 0x00000001, ++ INT5_uartTxrdy0_b = 1, ++ INT5_uartTxrdy0_m = 0x00000002, ++ INT5_uartRxrdy0_b = 2, ++ INT5_uartRxrdy0_m = 0x00000004, ++ INT5_pci_b = 3, ++ INT5_pci_m = 0x00000008, ++ INT5_pciDecoupled_b = 4, ++ INT5_pciDecoupled_m = 0x00000010, ++ INT5_spi_b = 5, ++ INT5_spi_m = 0x00000020, ++ INT5_deviceDecoupled_b = 6, ++ INT5_deviceDecoupled_m = 0x00000040, ++ INT5_i2cMaster_b = 7, ++ INT5_i2cMaster_m = 0x00000080, ++ INT5_i2cSlave_b = 8, ++ INT5_i2cSlave_m = 0x00000100, ++ INT5_ethOvr_b = 9, ++ INT5_ethOvr_m = 0x00000200, ++ INT5_ethUnd_b = 10, ++ INT5_ethUnd_m = 0x00000400, ++ INT5_ethPfd_b = 11, ++ INT5_ethPfd_m = 0x00000800, ++ INT5_nvram_b = 12, ++ INT5_nvram_m = 0x00001000, ++ ++ INT6_gpio0_b = 0, ++ INT6_gpio0_m = 0x00000001, ++ INT6_gpio1_b = 1, ++ INT6_gpio1_m = 0x00000002, ++ INT6_gpio2_b = 2, ++ INT6_gpio2_m = 0x00000004, ++ INT6_gpio3_b = 3, ++ INT6_gpio3_m = 0x00000008, ++ INT6_gpio4_b = 4, ++ INT6_gpio4_m = 0x00000010, ++ INT6_gpio5_b = 5, ++ INT6_gpio5_m = 0x00000020, ++ INT6_gpio6_b = 6, ++ INT6_gpio6_m = 0x00000040, ++ INT6_gpio7_b = 7, ++ INT6_gpio7_m = 0x00000080, ++ INT6_gpio8_b = 8, ++ INT6_gpio8_m = 0x00000100, ++ INT6_gpio9_b = 9, ++ INT6_gpio9_m = 0x00000200, ++ INT6_gpio10_b = 10, ++ INT6_gpio10_m = 0x00000400, ++ INT6_gpio11_b = 11, ++ INT6_gpio11_m = 0x00000800, ++ INT6_gpio12_b = 12, ++ INT6_gpio12_m = 0x00001000, ++ INT6_gpio13_b = 13, ++ INT6_gpio13_m = 0x00002000, ++ ++ NMIPS_gpio_b = 0, ++ NMIPS_gpio_m = 0x00000001, ++} ; ++ ++#endif // __IDT_INT_H__ ++ ++ +diff -urN linux.old/include/asm-mips/rc32434/iparb.h linux.dev/include/asm-mips/rc32434/iparb.h +--- linux.old/include/asm-mips/rc32434/iparb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/iparb.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,95 @@ ++#ifndef __IDT_IPARB_H__ ++#define __IDT_IPARB_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * IP Arbiter register definitions. ++ * ++ * File : $Id: iparb.h,v 1.3 2002/06/06 18:34:04 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020120 ++ * Update : ++ * $Log: iparb.h,v $ ++ * Revision 1.3 2002/06/06 18:34:04 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.2 2002/06/05 19:01:42 astichte ++ * Removed IDTField ++ * ++ * Revision 1.1 2002/05/29 17:33:23 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ IPARB0_PhysicalAddress = 0x18048000, ++ IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default ++ ++ IPARB0_VirtualAddress = 0xb8048000, ++ IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default ++} ; ++ ++enum ++{ ++ IPABMXC_ethernetReceive = 0, ++ IPABMXC_ethernetTransmit = 1, ++ IPABMXC_memoryToHoldFifo = 2, ++ IPABMXC_holdFifoToMemory = 3, ++ IPABMXC_pciToMemory = 4, ++ IPABMXC_memoryToPci = 5, ++ IPABMXC_pciTarget = 6, ++ IPABMXC_pciTargetStart = 7, ++ IPABMXC_cpuToIpBus = 8, ++ ++ IPABMXC_Count, // Must be last in list ! ++ IPABMXC_Min = IPABMXC_ethernetReceive, ++ ++ IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest. ++} ; ++ ++typedef struct ++{ ++ U32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_ ++ U32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_ ++ U32 ipac ; // use IPAC_ ++ U32 ipaitcc; // use IPAITCC_ ++ U32 ipaspare ; ++} volatile * IPARB_t ; ++ ++enum ++{ ++ IPAC_dwm_b = 2, ++ IPAC_dwm_m = 0x00000004, ++ IPAC_drm_b = 3, ++ IPAC_drm_m = 0x00000008, ++ IPAC_msk_b = 4, ++ IPAC_msk_m = 0x00000010, ++ ++ IPAPC_ptc_b = 0, ++ IPAPC_ptc_m = 0x00003fff, ++ IPAPC_mf_b = 14, ++ IPAPC_mf_m = 0x00004000, ++ IPAPC_cptc_b = 16, ++ IPAPC_cptc_m = 0x3fff0000, ++ ++ IPAITCC_itcc = 0, ++ IPAITCC_itcc, = 0x000001ff, ++ ++ IPABMC_mtc_b = 0, ++ IPABMC_mtc_m = 0x00000fff, ++ IPABMC_p_b = 12, ++ IPABMC_p_m = 0x00003000, ++ IPABMC_msk_b = 14, ++ IPABMC_msk_m = 0x00004000, ++ IPABMC_cmtc_b = 16, ++ IPABMC_cmtc_m = 0x0fff0000, ++}; ++ ++#endif // __IDT_IPARB_H__ +diff -urN linux.old/include/asm-mips/rc32434/irm.h linux.dev/include/asm-mips/rc32434/irm.h +--- linux.old/include/asm-mips/rc32434/irm.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/irm.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,55 @@ ++#ifndef __IDT_IRM_H__ ++#define __IDT_IRM_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Internal Register Map ++ * ++ * File : $Id: irm.h,v 1.2 2002/06/05 14:51:06 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020605 ++ * Update : ++ * $Log: irm.h,v $ ++ * Revision 1.2 2002/06/05 14:51:06 astichte ++ * *** empty log message *** ++ * ++ * Revision 1.1 2002/05/29 17:33:23 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ ******************************************************************************/ ++ ++/* ++ * NOTE -- ++ * This file is here for backwards compatibility. ++ * DO NOT USE !!!! ++ */ ++ ++typedef enum ++{ ++ IRM_Physical = 0x18000000, // Internal Reg. map physical. ++ RST_Offset = 0x00000000, // Includes sysid and RST. ++ DEV_Offset = 0x00010000, // Device Controller 0. ++ DDR_Offset = 0x00018000, // Double-Data-Rate mem. controller. ++ PMARB_Offset = 0x00020000, // PM bus arbiter. ++ TIM_Offset = 0x00028000, // Counter / timer. ++ INTEG_Offset = 0x00030000, // System Integrity. ++ INT_Offset = 0x00038000, // Interrupt controller. ++ DMA_Offset = 0x00040000, // DMA. ++ IPARB_Offset = 0x00044000, // IP bus arbiter. ++ GPIO_Offset = 0x00050000, // GPIO. ++ UART_Offset = 0x00058000, // UART ++ ETH_Offset = 0x00060000, // Ethernet 1. ++ I2C_Offset = 0x00068000, // I2C interface. ++ SPI_Offset = 0x00070000, // Serial Peripheral Interface. ++ NVRAM_Offset = 0x00078000, // NVRAM interface ++ AUTH_Offset = 0x0007c000, // Authorization unit ++ PCI_Offset = 0x00080000, ++ CROM_Offset = 0x000b8000, // Configuration ROM. ++ IRM_Size = 0x00200000, // Internal Reg. map size. ++} IRM_Offset_t ; ++ ++#endif // __IDT_IRM_H__ +diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h +--- linux.old/include/asm-mips/rc32434/irq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/irq.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,8 @@ ++#ifndef __ASM_MACH_MIPS_IRQ_H ++#define __ASM_MACH_MIPS_IRQ_H ++ ++#include <linux/config.h> ++ ++#define NR_IRQS 256 ++ ++#endif /* __ASM_MACH_MIPS_IRQ_H */ +diff -urN linux.old/include/asm-mips/rc32434/nvram.h linux.dev/include/asm-mips/rc32434/nvram.h +--- linux.old/include/asm-mips/rc32434/nvram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/nvram.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,97 @@ ++#ifndef __IDT_NVRAM_H ++#define __IDT_NVRAM_H ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * IP Arbiter register definitions. ++ * ++ * File : $Id: nvram.h,v 1.3 2003/07/24 18:34:04 astichte Exp $ ++ * ++ * Author : kiran.rao@idt.com ++ * Date : 20030724 ++ * Update : ++ * $Log: nvram.h,v $ ++ * ++ * ++ ******************************************************************************/ ++#include <asm/rc32434/tpes.h> ++ ++ ++enum ++{ ++ NVRAM0_PhysicalAddress = 0xba000000, ++ NVRAM_PhysicalAddress = NVRAM0_PhysicalAddress, // Default ++ ++ NVRAM0_VirtualAddress = 0xba000000, ++ NVRAM_VirtualAddress = NVRAM0_VirtualAddress, // Default ++} ; ++ ++enum ++{ ++ NVRCMD_cmd_b = 0, ++ NVRCMD_cmd_m = 0x0000007f, ++ ++ NVRS_r_b = 0, ++ NVRS_r_m = 0x00000001, ++ NVRS_e_b = 1, ++ NVRS_e_m = 0x00000002, ++ NVRS_k_b = 2, ++ NVRS_k_m = 0x00000004, ++ ++ NVRSM_r_b = 0, ++ NVRSM_r_m = 0x00000001, ++ NVRSM_e_b = 1, ++ NVRSM_e_m = 0x00000002, ++ NVRSM_k_b = 2, ++ NVRSM_k_m = 0x00000004, ++ ++ NVRCFG0_pwidth_b = 0, ++ NVRCFG0_pwidth_m = 0x00000003, ++ NVRCFG0_nmax_b = 2, ++ NVRCFG0_nmax_m = 0x0000000C, ++ NVRCFG0_vppl_b = 4, ++ NVRCFG0_vppl_m = 0x000000f0, ++ NVRCFG0_vppm_b = 8, ++ NVRCFG0_vppm_m = 0x00000300, ++ NVRCFG0_dvpp_b = 10, ++ NVRCFG0_dvpp_m = 0x00000c00, ++ NVRCFG0_x_b = 12, ++ NVRCFG0_x_m = 0x00007000, ++ ++ NVRCFG1_t1tecc_b = 0, ++ NVRCFG1_t1tecc_m = 0x00000003, ++ NVRCFG1_t1mrcl_b = 2, ++ NVRCFG1_t1mrcl_m = 0x0000000c, ++ NVRCFG1_t1bias_b = 4, ++ NVRCFG1_t1bias_m = 0x00000030, ++ NVRCFG1_t2tecc_b = 6, ++ NVRCFG1_t2tecc_m = 0x000000c0, ++ NVRCFG1_t2mrcl_b = 8, ++ NVRCFG1_t2mrcl_m = 0x00000300, ++ NVRCFG1_t2bias_b = 10, ++ NVRCFG1_t2bias_m = 0x00000c00, ++ NVRCFG1_t3tecc_b = 12, ++ NVRCFG1_t3tecc_m = 0x00003000, ++ NVRCFG1_t3mrcl_b = 14, ++ NVRCFG1_t3mrcl_m = 0x0000c000, ++ NVRCFG1_t3bias_b = 16, ++ NVRCFG1_t3bias_m = 0x00030000, ++ NVRCFG1_t4tecc_b = 18, ++ NVRCFG1_t4tecc_m = 0x000c0000, ++ NVRCFG1_t4mrcl_b = 20, ++ NVRCFG1_t4mrcl_m = 0x00300000, ++ NVRCFG1_t4bias_b = 22, ++ NVRCFG1_t4bias_m = 0x00c00000, ++ NVRCFG1_t5tecc_b = 24, ++ NVRCFG1_t5tecc_m = 0x03000000, ++ NVRCFG1_t5mrcl_b = 26, ++ NVRCFG1_t5mrcl_m = 0x0c000000, ++ NVRCFG1_t5bias_b = 28, ++ NVRCFG1_t5bias_m = 0x30000000, ++} ++ ++#endif // __IDT_NVRAM_H__ ++ +diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h +--- linux.old/include/asm-mips/rc32434/pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/pci.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,695 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * PCI register definitio ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb. ++ * ++ * Initial Release ++ * ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#ifndef __IDT_PCI_H__ ++#define __IDT_PCI_H__ ++ ++enum ++{ ++ PCI0_PhysicalAddress = 0x18080000, ++ PCI_PhysicalAddress = PCI0_PhysicalAddress, ++ ++ PCI0_VirtualAddress = 0xB8080000, ++ PCI_VirtualAddress = PCI0_VirtualAddress, ++} ; ++ ++enum ++{ ++ PCI_LbaCount = 4, // Local base addresses. ++} ; ++ ++typedef struct ++{ ++ u32 a ; // Address. ++ u32 c ; // Control. ++ u32 m ; // mapping. ++} PCI_Map_s ; ++ ++typedef struct ++{ ++ u32 pcic ; ++ u32 pcis ; ++ u32 pcism ; ++ u32 pcicfga ; ++ u32 pcicfgd ; ++ PCI_Map_s pcilba [PCI_LbaCount] ; ++ u32 pcidac ; ++ u32 pcidas ; ++ u32 pcidasm ; ++ u32 pcidad ; ++ u32 pcidma8c ; ++ u32 pcidma9c ; ++ u32 pcitc ; ++} volatile *PCI_t ; ++ ++// PCI messaging unit. ++enum ++{ ++ PCIM_Count = 2, ++} ; ++typedef struct ++{ ++ u32 pciim [PCIM_Count] ; ++ u32 pciom [PCIM_Count] ; ++ u32 pciid ; ++ u32 pciiic ; ++ u32 pciiim ; ++ u32 pciiod ; ++ u32 pciioic ; ++ u32 pciioim ; ++} volatile *PCIM_t ; ++ ++/******************************************************************************* ++ * ++ * PCI Control Register ++ * ++ ******************************************************************************/ ++enum ++{ ++ PCIC_en_b = 0, ++ PCIC_en_m = 0x00000001, ++ PCIC_tnr_b = 1, ++ PCIC_tnr_m = 0x00000002, ++ PCIC_sce_b = 2, ++ PCIC_sce_m = 0x00000004, ++ PCIC_ien_b = 3, ++ PCIC_ien_m = 0x00000008, ++ PCIC_aaa_b = 4, ++ PCIC_aaa_m = 0x00000010, ++ PCIC_eap_b = 5, ++ PCIC_eap_m = 0x00000020, ++ PCIC_pcim_b = 6, ++ PCIC_pcim_m = 0x000001c0, ++ PCIC_pcim_disabled_v = 0, ++ PCIC_pcim_tnr_v = 1, // Satellite - target not ready ++ PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU. ++ PCIC_pcim_extern_v = 3, // Host - external arbiter. ++ PCIC_pcim_fixed_v = 4, // Host - fixed priority arb. ++ PCIC_pcim_roundrobin_v = 5, // Host - round robin priority. ++ PCIC_pcim_reserved6_v = 6, ++ PCIC_pcim_reserved7_v = 7, ++ PCIC_igm_b = 9, ++ PCIC_igm_m = 0x00000200, ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI Status Register ++ * ++ ******************************************************************************/ ++enum { ++ PCIS_eed_b = 0, ++ PCIS_eed_m = 0x00000001, ++ PCIS_wr_b = 1, ++ PCIS_wr_m = 0x00000002, ++ PCIS_nmi_b = 2, ++ PCIS_nmi_m = 0x00000004, ++ PCIS_ii_b = 3, ++ PCIS_ii_m = 0x00000008, ++ PCIS_cwe_b = 4, ++ PCIS_cwe_m = 0x00000010, ++ PCIS_cre_b = 5, ++ PCIS_cre_m = 0x00000020, ++ PCIS_mdpe_b = 6, ++ PCIS_mdpe_m = 0x00000040, ++ PCIS_sta_b = 7, ++ PCIS_sta_m = 0x00000080, ++ PCIS_rta_b = 8, ++ PCIS_rta_m = 0x00000100, ++ PCIS_rma_b = 9, ++ PCIS_rma_m = 0x00000200, ++ PCIS_sse_b = 10, ++ PCIS_sse_m = 0x00000400, ++ PCIS_ose_b = 11, ++ PCIS_ose_m = 0x00000800, ++ PCIS_pe_b = 12, ++ PCIS_pe_m = 0x00001000, ++ PCIS_tae_b = 13, ++ PCIS_tae_m = 0x00002000, ++ PCIS_rle_b = 14, ++ PCIS_rle_m = 0x00004000, ++ PCIS_bme_b = 15, ++ PCIS_bme_m = 0x00008000, ++ PCIS_prd_b = 16, ++ PCIS_prd_m = 0x00010000, ++ PCIS_rip_b = 17, ++ PCIS_rip_m = 0x00020000, ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI Status Mask Register ++ * ++ ******************************************************************************/ ++enum { ++ PCISM_eed_b = 0, ++ PCISM_eed_m = 0x00000001, ++ PCISM_wr_b = 1, ++ PCISM_wr_m = 0x00000002, ++ PCISM_nmi_b = 2, ++ PCISM_nmi_m = 0x00000004, ++ PCISM_ii_b = 3, ++ PCISM_ii_m = 0x00000008, ++ PCISM_cwe_b = 4, ++ PCISM_cwe_m = 0x00000010, ++ PCISM_cre_b = 5, ++ PCISM_cre_m = 0x00000020, ++ PCISM_mdpe_b = 6, ++ PCISM_mdpe_m = 0x00000040, ++ PCISM_sta_b = 7, ++ PCISM_sta_m = 0x00000080, ++ PCISM_rta_b = 8, ++ PCISM_rta_m = 0x00000100, ++ PCISM_rma_b = 9, ++ PCISM_rma_m = 0x00000200, ++ PCISM_sse_b = 10, ++ PCISM_sse_m = 0x00000400, ++ PCISM_ose_b = 11, ++ PCISM_ose_m = 0x00000800, ++ PCISM_pe_b = 12, ++ PCISM_pe_m = 0x00001000, ++ PCISM_tae_b = 13, ++ PCISM_tae_m = 0x00002000, ++ PCISM_rle_b = 14, ++ PCISM_rle_m = 0x00004000, ++ PCISM_bme_b = 15, ++ PCISM_bme_m = 0x00008000, ++ PCISM_prd_b = 16, ++ PCISM_prd_m = 0x00010000, ++ PCISM_rip_b = 17, ++ PCISM_rip_m = 0x00020000, ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI Configuration Address Register ++ * ++ ******************************************************************************/ ++enum { ++ PCICFGA_reg_b = 2, ++ PCICFGA_reg_m = 0x000000fc, ++ PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_ ++ PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_ ++ PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_ ++ PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_ ++ PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_ ++ PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_ ++ PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_ ++ PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_ ++ PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_ ++ PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_ ++ PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_ ++ PCICFGA_reg_pba0m_v = 0x48>>2, ++ PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_ ++ PCICFGA_reg_pba1m_v = 0x50>>2, ++ PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_ ++ PCICFGA_reg_pba2m_v = 0x58>>2, ++ PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_ ++ PCICFGA_reg_pba3m_v = 0x60>>2, ++ PCICFGA_reg_pmgt_v = 0x64>>2, ++ PCICFGA_func_b = 8, ++ PCICFGA_func_m = 0x00000700, ++ PCICFGA_dev_b = 11, ++ PCICFGA_dev_m = 0x0000f800, ++ PCICFGA_dev_internal_v = 0, ++ PCICFGA_bus_b = 16, ++ PCICFGA_bus_m = 0x00ff0000, ++ PCICFGA_bus_type0_v = 0, //local bus ++ PCICFGA_en_b = 31, // read only ++ PCICFGA_en_m = 0x80000000, ++} ; ++ ++enum { ++ PCFGID_vendor_b = 0, ++ PCFGID_vendor_m = 0x0000ffff, ++ PCFGID_vendor_IDT_v = 0x111d, ++ PCFGID_device_b = 16, ++ PCFGID_device_m = 0xffff0000, ++ PCFGID_device_Korinade_v = 0x0214, ++ ++ PCFG04_command_ioena_b = 1, ++ PCFG04_command_ioena_m = 0x00000001, ++ PCFG04_command_memena_b = 2, ++ PCFG04_command_memena_m = 0x00000002, ++ PCFG04_command_bmena_b = 3, ++ PCFG04_command_bmena_m = 0x00000004, ++ PCFG04_command_mwinv_b = 5, ++ PCFG04_command_mwinv_m = 0x00000010, ++ PCFG04_command_parena_b = 7, ++ PCFG04_command_parena_m = 0x00000040, ++ PCFG04_command_serrena_b = 9, ++ PCFG04_command_serrena_m = 0x00000100, ++ PCFG04_command_fastbbena_b = 10, ++ PCFG04_command_fastbbena_m = 0x00000200, ++ PCFG04_status_b = 16, ++ PCFG04_status_m = 0xffff0000, ++ PCFG04_status_66MHz_b = 21, // 66 MHz enable ++ PCFG04_status_66MHz_m = 0x00200000, ++ PCFG04_status_fbb_b = 23, ++ PCFG04_status_fbb_m = 0x00800000, ++ PCFG04_status_mdpe_b = 24, ++ PCFG04_status_mdpe_m = 0x01000000, ++ PCFG04_status_dst_b = 25, ++ PCFG04_status_dst_m = 0x06000000, ++ PCFG04_status_sta_b = 27, ++ PCFG04_status_sta_m = 0x08000000, ++ PCFG04_status_rta_b = 28, ++ PCFG04_status_rta_m = 0x10000000, ++ PCFG04_status_rma_b = 29, ++ PCFG04_status_rma_m = 0x20000000, ++ PCFG04_status_sse_b = 30, ++ PCFG04_status_sse_m = 0x40000000, ++ PCFG04_status_pe_b = 31, ++ PCFG04_status_pe_m = 0x40000000, ++ ++ PCFG08_revId_b = 0, ++ PCFG08_revId_m = 0x000000ff, ++ PCFG08_classCode_b = 0, ++ PCFG08_classCode_m = 0xffffff00, ++ PCFG08_classCode_bridge_v = 06, ++ PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS ++ PCFG0C_cacheline_b = 0, ++ PCFG0C_cacheline_m = 0x000000ff, ++ PCFG0C_masterLatency_b = 8, ++ PCFG0C_masterLatency_m = 0x0000ff00, ++ PCFG0C_headerType_b = 16, ++ PCFG0C_headerType_m = 0x00ff0000, ++ PCFG0C_bist_b = 24, ++ PCFG0C_bist_m = 0xff000000, ++ ++ PCIPBA_msi_b = 0, ++ PCIPBA_msi_m = 0x00000001, ++ PCIPBA_p_b = 3, ++ PCIPBA_p_m = 0x00000004, ++ PCIPBA_baddr_b = 8, ++ PCIPBA_baddr_m = 0xffffff00, ++ ++ PCFGSS_vendorId_b = 0, ++ PCFGSS_vendorId_m = 0x0000ffff, ++ PCFGSS_id_b = 16, ++ PCFGSS_id_m = 0xffff0000, ++ ++ PCFG3C_interruptLine_b = 0, ++ PCFG3C_interruptLine_m = 0x000000ff, ++ PCFG3C_interruptPin_b = 8, ++ PCFG3C_interruptPin_m = 0x0000ff00, ++ PCFG3C_minGrant_b = 16, ++ PCFG3C_minGrant_m = 0x00ff0000, ++ PCFG3C_maxLat_b = 24, ++ PCFG3C_maxLat_m = 0xff000000, ++ ++ PCIPBAC_msi_b = 0, ++ PCIPBAC_msi_m = 0x00000001, ++ PCIPBAC_p_b = 1, ++ PCIPBAC_p_m = 0x00000002, ++ PCIPBAC_size_b = 2, ++ PCIPBAC_size_m = 0x0000007c, ++ PCIPBAC_sb_b = 7, ++ PCIPBAC_sb_m = 0x00000080, ++ PCIPBAC_pp_b = 8, ++ PCIPBAC_pp_m = 0x00000100, ++ PCIPBAC_mr_b = 9, ++ PCIPBAC_mr_m = 0x00000600, ++ PCIPBAC_mr_read_v =0, //no prefetching ++ PCIPBAC_mr_readLine_v =1, ++ PCIPBAC_mr_readMult_v =2, ++ PCIPBAC_mrl_b = 11, ++ PCIPBAC_mrl_m = 0x00000800, ++ PCIPBAC_mrm_b = 12, ++ PCIPBAC_mrm_m = 0x00001000, ++ PCIPBAC_trp_b = 13, ++ PCIPBAC_trp_m = 0x00002000, ++ ++ PCFG40_trdyTimeout_b = 0, ++ PCFG40_trdyTimeout_m = 0x000000ff, ++ PCFG40_retryLim_b = 8, ++ PCFG40_retryLim_m = 0x0000ff00, ++}; ++ ++/******************************************************************************* ++ * ++ * PCI Local Base Address [0|1|2|3] Register ++ * ++ ******************************************************************************/ ++enum { ++ PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a ++ PCILBA_baddr_m = 0xffffff00, ++} ; ++/******************************************************************************* ++ * ++ * PCI Local Base Address Control Register ++ * ++ ******************************************************************************/ ++enum { ++ PCILBAC_msi_b = 0, // In pPci->pcilba[i].c ++ PCILBAC_msi_m = 0x00000001, ++ PCILBAC_msi_mem_v = 0, ++ PCILBAC_msi_io_v = 1, ++ PCILBAC_size_b = 2, // In pPci->pcilba[i].c ++ PCILBAC_size_m = 0x0000007c, ++ PCILBAC_sb_b = 7, // In pPci->pcilba[i].c ++ PCILBAC_sb_m = 0x00000080, ++ PCILBAC_rt_b = 8, // In pPci->pcilba[i].c ++ PCILBAC_rt_m = 0x00000100, ++ PCILBAC_rt_noprefetch_v = 0, // mem read ++ PCILBAC_rt_prefetch_v = 1, // mem readline ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI Local Base Address [0|1|2|3] Mapping Register ++ * ++ ******************************************************************************/ ++enum { ++ PCILBAM_maddr_b = 8, ++ PCILBAM_maddr_m = 0xffffff00, ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI Decoupled Access Control Register ++ * ++ ******************************************************************************/ ++enum { ++ PCIDAC_den_b = 0, ++ PCIDAC_den_m = 0x00000001, ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI Decoupled Access Status Register ++ * ++ ******************************************************************************/ ++enum { ++ PCIDAS_d_b = 0, ++ PCIDAS_d_m = 0x00000001, ++ PCIDAS_b_b = 1, ++ PCIDAS_b_m = 0x00000002, ++ PCIDAS_e_b = 2, ++ PCIDAS_e_m = 0x00000004, ++ PCIDAS_ofe_b = 3, ++ PCIDAS_ofe_m = 0x00000008, ++ PCIDAS_off_b = 4, ++ PCIDAS_off_m = 0x00000010, ++ PCIDAS_ife_b = 5, ++ PCIDAS_ife_m = 0x00000020, ++ PCIDAS_iff_b = 6, ++ PCIDAS_iff_m = 0x00000040, ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI DMA Channel 8 Configuration Register ++ * ++ ******************************************************************************/ ++enum ++{ ++ PCIDMA8C_mbs_b = 0, // Maximum Burst Size. ++ PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c } ++ PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads. ++ PCIDMA8C_our_m = 0x00001000, // { pcidma8c } ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI DMA Channel 9 Configuration Register ++ * ++ ******************************************************************************/ ++enum ++{ ++ PCIDMA9C_mbs_b = 0, // Maximum Burst Size. ++ PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c } ++} ; ++ ++/******************************************************************************* ++ * ++ * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors ++ * ++ ******************************************************************************/ ++enum { ++ PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor) ++ PCIDMAD_pt_m = 0x00c00000, // preferred transaction field ++ // These are for reads (DMA channel 8) ++ PCIDMAD_devcmd_mr_v = 0, //memory read ++ PCIDMAD_devcmd_mrl_v = 1, //memory read line ++ PCIDMAD_devcmd_mrm_v = 2, //memory read multiple ++ PCIDMAD_devcmd_ior_v = 3, //I/O read ++ // These are for writes (DMA channel 9) ++ PCIDMAD_devcmd_mw_v = 0, //memory write ++ PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate ++ PCIDMAD_devcmd_iow_v = 3, //I/O write ++ ++ // Swap byte field applies to both DMA channel 8 and 9 ++ PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor) ++ PCIDMAD_sb_m = 0x01000000, // swap byte field ++} ; ++ ++ ++/******************************************************************************* ++ * ++ * PCI Target Control Register ++ * ++ ******************************************************************************/ ++enum ++{ ++ PCITC_rtimer_b = 0, // In PCITC_t -> pcitc ++ PCITC_rtimer_m = 0x000000ff, ++ PCITC_dtimer_b = 8, // In PCITC_t -> pcitc ++ PCITC_dtimer_m = 0x0000ff00, ++ PCITC_rdr_b = 18, // In PCITC_t -> pcitc ++ PCITC_rdr_m = 0x00040000, ++ PCITC_ddt_b = 19, // In PCITC_t -> pcitc ++ PCITC_ddt_m = 0x00080000, ++} ; ++/******************************************************************************* ++ * ++ * PCI messaging unit [applies to both inbound and outbound registers ] ++ * ++ ******************************************************************************/ ++enum ++{ ++ PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}} ++ PCIM_m0_m = 0x00000001, // inbound or outbound message 0 ++ PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}} ++ PCIM_m1_m = 0x00000002, // inbound or outbound message 1 ++ PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}} ++ PCIM_db_m = 0x00000004, // inbound or outbound doorbell ++}; ++ ++ ++ ++ ++ ++ ++#define PCI_MSG_VirtualAddress 0xB8088010 ++#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress) ++#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress) ++ ++#define PCIM_SHFT 0x6 ++#define PCIM_BIT_LEN 0x7 ++#define PCIM_H_EA 0x3 ++#define PCIM_H_IA_FIX 0x4 ++#define PCIM_H_IA_RR 0x5 ++#if 0 ++#define PCI_ADDR_START 0x13000000 ++#endif ++ ++#define PCI_ADDR_START 0x50000000 ++ ++#define CPUTOPCI_MEM_WIN 0x02000000 ++#define CPUTOPCI_IO_WIN 0x00100000 ++#define PCILBA_SIZE_SHFT 2 ++#define PCILBA_SIZE_MASK 0x1F ++#define SIZE_256MB 0x1C ++#define SIZE_128MB 0x1B ++#define SIZE_64MB 0x1A ++#define SIZE_32MB 0x19 ++#define SIZE_16MB 0x18 ++#define SIZE_4MB 0x16 ++#define SIZE_2MB 0x15 ++#define SIZE_1MB 0x14 ++#define KORINA_CONFIG0_ADDR 0x80000000 ++#define KORINA_CONFIG1_ADDR 0x80000004 ++#define KORINA_CONFIG2_ADDR 0x80000008 ++#define KORINA_CONFIG3_ADDR 0x8000000C ++#define KORINA_CONFIG4_ADDR 0x80000010 ++#define KORINA_CONFIG5_ADDR 0x80000014 ++#define KORINA_CONFIG6_ADDR 0x80000018 ++#define KORINA_CONFIG7_ADDR 0x8000001C ++#define KORINA_CONFIG8_ADDR 0x80000020 ++#define KORINA_CONFIG9_ADDR 0x80000024 ++#define KORINA_CONFIG10_ADDR 0x80000028 ++#define KORINA_CONFIG11_ADDR 0x8000002C ++#define KORINA_CONFIG12_ADDR 0x80000030 ++#define KORINA_CONFIG13_ADDR 0x80000034 ++#define KORINA_CONFIG14_ADDR 0x80000038 ++#define KORINA_CONFIG15_ADDR 0x8000003C ++#define KORINA_CONFIG16_ADDR 0x80000040 ++#define KORINA_CONFIG17_ADDR 0x80000044 ++#define KORINA_CONFIG18_ADDR 0x80000048 ++#define KORINA_CONFIG19_ADDR 0x8000004C ++#define KORINA_CONFIG20_ADDR 0x80000050 ++#define KORINA_CONFIG21_ADDR 0x80000054 ++#define KORINA_CONFIG22_ADDR 0x80000058 ++#define KORINA_CONFIG23_ADDR 0x8000005C ++#define KORINA_CONFIG24_ADDR 0x80000060 ++#define KORINA_CONFIG25_ADDR 0x80000064 ++#define KORINA_CMD (PCFG04_command_ioena_m | \ ++ PCFG04_command_memena_m | \ ++ PCFG04_command_bmena_m | \ ++ PCFG04_command_mwinv_m | \ ++ PCFG04_command_parena_m | \ ++ PCFG04_command_serrena_m ) ++ ++#define KORINA_STAT (PCFG04_status_mdpe_m | \ ++ PCFG04_status_sta_m | \ ++ PCFG04_status_rta_m | \ ++ PCFG04_status_rma_m | \ ++ PCFG04_status_sse_m | \ ++ PCFG04_status_pe_m) ++ ++#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD) ++ ++#define KORINA_REVID 0 ++#define KORINA_CLASS_CODE 0 ++#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \ ++ KORINA_REVID) ++ ++#define KORINA_CACHE_LINE_SIZE 4 ++#define KORINA_MASTER_LAT 0x3c ++#define KORINA_HEADER_TYPE 0 ++#define KORINA_BIST 0 ++ ++#define KORINA_CNFG3 ((KORINA_BIST << 24) | \ ++ (KORINA_HEADER_TYPE<<16) | \ ++ (KORINA_MASTER_LAT<<8) | \ ++ KORINA_CACHE_LINE_SIZE ) ++ ++#define KORINA_BAR0 0x00000008 /* 128 MB Memory */ ++#define KORINA_BAR1 0x18800001 /* 1 MB IO */ ++#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina ++ internal Registers */ ++#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */ ++ ++#define KORINA_CNFG4 KORINA_BAR0 ++#define KORINA_CNFG5 KORINA_BAR1 ++#define KORINA_CNFG6 KORINA_BAR2 ++#define KORINA_CNFG7 KORINA_BAR3 ++ ++#define KORINA_SUBSYS_VENDOR_ID 0x011d ++#define KORINA_SUBSYSTEM_ID 0x0214 ++#define KORINA_CNFG8 0 ++#define KORINA_CNFG9 0 ++#define KORINA_CNFG10 0 ++#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ ++ KORINA_SUBSYSTEM_ID) ++#define KORINA_INT_LINE 1 ++#define KORINA_INT_PIN 1 ++#define KORINA_MIN_GNT 8 ++#define KORINA_MAX_LAT 0x38 ++#define KORINA_CNFG12 0 ++#define KORINA_CNFG13 0 ++#define KORINA_CNFG14 0 ++#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \ ++ (KORINA_MIN_GNT<<16) | \ ++ (KORINA_INT_PIN<<8) | \ ++ KORINA_INT_LINE) ++#define KORINA_RETRY_LIMIT 0x80 ++#define KORINA_TRDY_LIMIT 0x80 ++#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \ ++ KORINA_TRDY_LIMIT) ++#define PCI_PBAxC_R 0x0 ++#define PCI_PBAxC_RL 0x1 ++#define PCI_PBAxC_RM 0x2 ++#define SIZE_SHFT 2 ++ ++#if defined(__MIPSEB__) ++#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \ ++ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \ ++ PCIPBAC_pp_m | \ ++ (SIZE_128MB<<SIZE_SHFT) | \ ++ PCIPBAC_p_m) ++#else ++#define KORINA_PBA0C ( PCIPBAC_mrl_m | \ ++ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \ ++ PCIPBAC_pp_m | \ ++ (SIZE_128MB<<SIZE_SHFT) | \ ++ PCIPBAC_p_m) ++#endif ++#define KORINA_CNFG17 KORINA_PBA0C ++#define KORINA_PBA0M 0x0 ++#define KORINA_CNFG18 KORINA_PBA0M ++ ++#if defined(__MIPSEB__) ++#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \ ++ PCIPBAC_msi_m) ++#else ++#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \ ++ PCIPBAC_msi_m) ++#endif ++#define KORINA_CNFG19 KORINA_PBA1C ++#define KORINA_PBA1M 0x0 ++#define KORINA_CNFG20 KORINA_PBA1M ++ ++#if defined(__MIPSEB__) ++#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \ ++ PCIPBAC_msi_m) ++#else ++#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \ ++ PCIPBAC_msi_m) ++#endif ++#define KORINA_CNFG21 KORINA_PBA2C ++#define KORINA_PBA2M 0x18000000 ++#define KORINA_CNFG22 KORINA_PBA2M ++#define KORINA_PBA3C 0 ++#define KORINA_CNFG23 KORINA_PBA3C ++#define KORINA_PBA3M 0 ++#define KORINA_CNFG24 KORINA_PBA3M ++ ++ ++ ++#define PCITC_DTIMER_VAL 8 ++#define PCITC_RTIMER_VAL 0x10 ++ ++ ++ ++ ++#endif // __IDT_PCI_H__ ++ ++ ++ +diff -urN linux.old/include/asm-mips/rc32434/pcikorina.h linux.dev/include/asm-mips/rc32434/pcikorina.h +--- linux.old/include/asm-mips/rc32434/pcikorina.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/pcikorina.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,209 @@ ++/* $Id: pciacacia.h,v 1.5 2001/05/01 10:09:17 carstenl Exp $ ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ */ ++#ifndef _PCIKORINA_H ++#define _PCIKORINA_H ++ ++ ++#define PCI_MSG_VirtualAddress 0xB8088010 ++#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress) ++#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress) ++ ++#define PCIM_SHFT 0x6 ++#define PCIM_BIT_LEN 0x7 ++#define PCIM_H_EA 0x3 ++#define PCIM_H_IA_FIX 0x4 ++#define PCIM_H_IA_RR 0x5 ++#if 0 ++#define PCI_ADDR_START 0x13000000 ++#endif ++ ++#define PCI_ADDR_START 0x50000000 ++ ++#define CPUTOPCI_MEM_WIN 0x02000000 ++#define CPUTOPCI_IO_WIN 0x00100000 ++#define PCILBA_SIZE_SHFT 2 ++#define PCILBA_SIZE_MASK 0x1F ++#define SIZE_256MB 0x1C ++#define SIZE_128MB 0x1B ++#define SIZE_64MB 0x1A ++#define SIZE_32MB 0x19 ++#define SIZE_16MB 0x18 ++#define SIZE_4MB 0x16 ++#define SIZE_2MB 0x15 ++#define SIZE_1MB 0x14 ++#define KORINA_CONFIG0_ADDR 0x80000000 ++#define KORINA_CONFIG1_ADDR 0x80000004 ++#define KORINA_CONFIG2_ADDR 0x80000008 ++#define KORINA_CONFIG3_ADDR 0x8000000C ++#define KORINA_CONFIG4_ADDR 0x80000010 ++#define KORINA_CONFIG5_ADDR 0x80000014 ++#define KORINA_CONFIG6_ADDR 0x80000018 ++#define KORINA_CONFIG7_ADDR 0x8000001C ++#define KORINA_CONFIG8_ADDR 0x80000020 ++#define KORINA_CONFIG9_ADDR 0x80000024 ++#define KORINA_CONFIG10_ADDR 0x80000028 ++#define KORINA_CONFIG11_ADDR 0x8000002C ++#define KORINA_CONFIG12_ADDR 0x80000030 ++#define KORINA_CONFIG13_ADDR 0x80000034 ++#define KORINA_CONFIG14_ADDR 0x80000038 ++#define KORINA_CONFIG15_ADDR 0x8000003C ++#define KORINA_CONFIG16_ADDR 0x80000040 ++#define KORINA_CONFIG17_ADDR 0x80000044 ++#define KORINA_CONFIG18_ADDR 0x80000048 ++#define KORINA_CONFIG19_ADDR 0x8000004C ++#define KORINA_CONFIG20_ADDR 0x80000050 ++#define KORINA_CONFIG21_ADDR 0x80000054 ++#define KORINA_CONFIG22_ADDR 0x80000058 ++#define KORINA_CONFIG23_ADDR 0x8000005C ++#define KORINA_CONFIG24_ADDR 0x80000060 ++#define KORINA_CONFIG25_ADDR 0x80000064 ++#define KORINA_CMD (PCFG04_command_ioena_m | \ ++ PCFG04_command_memena_m | \ ++ PCFG04_command_bmena_m | \ ++ PCFG04_command_mwinv_m | \ ++ PCFG04_command_parena_m | \ ++ PCFG04_command_serrena_m ) ++ ++#define KORINA_STAT (PCFG04_status_mdpe_m | \ ++ PCFG04_status_sta_m | \ ++ PCFG04_status_rta_m | \ ++ PCFG04_status_rma_m | \ ++ PCFG04_status_sse_m | \ ++ PCFG04_status_pe_m) ++ ++#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD) ++ ++#define KORINA_REVID 0 ++#define KORINA_CLASS_CODE 0 ++#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \ ++ KORINA_REVID) ++ ++#define KORINA_CACHE_LINE_SIZE 4 ++#define KORINA_MASTER_LAT 0x3c ++#define KORINA_HEADER_TYPE 0 ++#define KORINA_BIST 0 ++ ++#define KORINA_CNFG3 ((KORINA_BIST << 24) | \ ++ (KORINA_HEADER_TYPE<<16) | \ ++ (KORINA_MASTER_LAT<<8) | \ ++ KORINA_CACHE_LINE_SIZE ) ++ ++#define KORINA_BAR0 0x00000008 /* 128 MB Memory */ ++#define KORINA_BAR1 0x18800001 /* 1 MB IO */ ++#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Acacia ++ internal Registers */ ++#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */ ++ ++#define KORINA_CNFG4 KORINA_BAR0 ++#define KORINA_CNFG5 KORINA_BAR1 ++#define KORINA_CNFG6 KORINA_BAR2 ++#define KORINA_CNFG7 KORINA_BAR3 ++ ++#define KORINA_SUBSYS_VENDOR_ID 0 ++#define KORINA_SUBSYSTEM_ID 0 ++#define KORINA_CNFG8 0 ++#define KORINA_CNFG9 0 ++#define KORINA_CNFG10 0 ++#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \ ++ KORINA_SUBSYSTEM_ID) ++#define KORINA_INT_LINE 1 ++#define KORINA_INT_PIN 1 ++#define KORINA_MIN_GNT 8 ++#define KORINA_MAX_LAT 0x38 ++#define KORINA_CNFG12 0 ++#define KORINA_CNFG13 0 ++#define KORINA_CNFG14 0 ++#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \ ++ (KORINA_MIN_GNT<<16) | \ ++ (KORINA_INT_PIN<<8) | \ ++ KORINA_INT_LINE) ++#define KORINA_RETRY_LIMIT 0x80 ++#define KORINA_TRDY_LIMIT 0x80 ++#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \ ++ KORINA_TRDY_LIMIT) ++#define PCI_PBAxC_R 0x0 ++#define PCI_PBAxC_RL 0x1 ++#define PCI_PBAxC_RM 0x2 ++#define SIZE_SHFT 2 ++ ++#ifdef __MIPSEB__ ++#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \ ++ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \ ++ PCIPBAC_pp_m | \ ++ (SIZE_32MB<<SIZE_SHFT) | \ ++ PCIPBAC_p_m) ++#else ++#define KORINA_PBA0C ( PCIPBAC_mrl_m | \ ++ ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \ ++ PCIPBAC_pp_m | \ ++ (SIZE_32MB<<SIZE_SHFT) | \ ++ PCIPBAC_p_m) ++#endif ++ ++#if 0 ++ ++#define KORINA_PBA0C ( PCIPBAC_sb_m | PCIPBAC_pp_m | \ ++ ((PCI_PBAxC_R &0x3) << PCIPBAC_mr_b) | \ ++ (SIZE_128MB<<SIZE_SHFT)) ++#endif ++#define KORINA_CNFG17 KORINA_PBA0C ++#define KORINA_PBA0M 0x0 ++#define KORINA_CNFG18 KORINA_PBA0M ++ ++#ifdef __MIPSEB__ ++#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \ ++ PCIPBAC_msi_m) ++#else ++#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \ ++ PCIPBAC_msi_m) ++ ++#endif ++ ++#define KORINA_CNFG19 KORINA_PBA1C ++#define KORINA_PBA1M 0x0 ++#define KORINA_CNFG20 KORINA_PBA1M ++ ++#ifdef __MIPSEB__ ++#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \ ++ PCIPBAC_msi_m) ++#else ++#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \ ++ PCIPBAC_msi_m) ++ ++#endif ++#define KORINA_CNFG21 KORINA_PBA2C ++#define KORINA_PBA2M 0x18000000 ++#define KORINA_CNFG22 KORINA_PBA2M ++#define KORINA_PBA3C 0 ++#define KORINA_CNFG23 KORINA_PBA3C ++#define KORINA_PBA3M 0 ++#define KORINA_CNFG24 KORINA_PBA3M ++ ++ ++ ++#define PCITC_DTIMER_VAL 8 ++#define PCITC_RTIMER_VAL 0x10 ++ ++ ++#endif /* _PCIKORINA_H */ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +diff -urN linux.old/include/asm-mips/rc32434/pci_regs.h linux.dev/include/asm-mips/rc32434/pci_regs.h +--- linux.old/include/asm-mips/rc32434/pci_regs.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/pci_regs.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,8 @@ ++/* Override the default address space for this arch ++*/ ++ ++#include <linux/pci_regs.h> ++ ++//#undef PCI_BASE_ADDRESS_SPACE ++//#define PCI_BASE_ADDRESS_SPACE PCI_BASE_ADDRESS_SPACE_MEMORY ++ +diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h +--- linux.old/include/asm-mips/rc32434/rb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/rb.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,69 @@ ++#ifndef __MIPS_RB_H__ ++#define __MIPS_RB_H__ ++#include <linux/genhd.h> ++ ++#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000)) ++#define DEV0BASE 0x010000 ++#define DEV0MASK 0x010004 ++#define DEV0C 0x010008 ++#define DEV0TC 0x01000C ++#define DEV1BASE 0x010010 ++#define DEV1MASK 0x010014 ++#define DEV1C 0x010018 ++#define DEV1TC 0x01001C ++#define DEV2BASE 0x010020 ++#define DEV2MASK 0x010024 ++#define DEV2C 0x010028 ++#define DEV2TC 0x01002C ++#define DEV3BASE 0x010030 ++#define DEV3MASK 0x010034 ++#define DEV3C 0x010038 ++#define DEV3TC 0x01003C ++#define BTCS 0x010040 ++#define BTCOMPARE 0x010044 ++#define GPIOFUNC 0x050000 ++#define GPIOCFG 0x050004 ++#define GPIOD 0x050008 ++#define GPIOILEVEL 0x05000C ++#define GPIOISTAT 0x050010 ++#define GPIONMIEN 0x050014 ++#define IMASK6 0x038038 ++ ++#define LO_WPX (1 << 0) ++#define LO_ALE (1 << 1) ++#define LO_CLE (1 << 2) ++#define LO_CEX (1 << 3) ++#define LO_FOFF (1 << 5) ++#define LO_SPICS (1 << 6) ++#define LO_ULED (1 << 7) ++ ++typedef enum { ++ FUNC = 0x00, ++ CFG = 0x04, ++ DATA = 0x08, ++ ILEVEL = 0x0c, ++ ISTAT = 0x10, ++ NMIEN = 0x14 ++} gpio_func; ++ ++extern void changeLatchU5(unsigned char orMask, unsigned char nandMask); ++extern unsigned get434Reg(unsigned regOffs); ++extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val); ++extern void gpio_set(gpio_func func, u32 mask, u32 value); ++extern u32 gpio_get(gpio_func func); ++ ++#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x))) ++ ++struct korina_device { ++ char *name; ++ unsigned char mac[6]; ++ struct net_device *dev; ++}; ++ ++struct cf_device { ++ int gpio_pin; ++ void *dev; ++ struct gendisk *gd; ++}; ++ ++#endif +diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h +--- linux.old/include/asm-mips/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/rc32434.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,126 @@ ++/* ++ *************************************************************************** ++ * Definitions for IDT RC323434 CPU. ++ * ++ **************************************************************************** ++ * Kiran Rao ++ * ++ * Original form ++ **************************************************************************** ++ * P. Sadik Oct 08, 2003 ++ * ++ * Started revision history ++ * Made IDT_BUS_FREQ a kernel configuration parameter ++ **************************************************************************** ++ * P. Sadik Oct 10, 2003 ++ * ++ * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead ++ * idt_cpu_freq is used everywhere ++ **************************************************************************** ++ * P. Sadik Oct 20, 2003 ++ * ++ * Removed RC32434_BASE_BAUD ++ **************************************************************************** ++*/ ++#ifndef _RC32434_H_ ++#define _RC32434_H_ ++ ++#include <linux/config.h> ++#include <linux/delay.h> ++#include <asm/io.h> ++#include <asm/rc32434/timer.h> ++ ++#define RC32434_REG_BASE 0x18000000 ++ ++#define interrupt ((volatile INT_t ) INT0_VirtualAddress) ++#define timer ((volatile TIM_t) TIM0_VirtualAddress) ++#define gpio ((volatile GPIO_t) GPIO0_VirtualAddress) ++ ++#define IDT_CLOCK_MULT 2 ++#define MIPS_CPU_TIMER_IRQ 7 ++/* Interrupt Controller */ ++#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000) ++#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008) ++#define IC_GROUP_OFFSET 0x0C ++ ++#define NUM_INTR_GROUPS 5 ++/* 16550 UARTs */ ++ ++#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */ ++#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */ ++#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */ ++#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */ ++#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) ++ ++ ++#ifdef __MIPSEB__ ++#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003) ++#else ++#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000) ++#endif ++ ++#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0 ++// #define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11 ++ ++#define local_readl(addr) __raw_readl(addr) ++#define local_writel(l,addr) __raw_writel(l,addr) ++ ++/* cpu pipeline flush */ ++static inline void rc32434_sync(void) ++{ ++ __asm__ volatile ("sync"); ++} ++ ++static inline void rc32434_sync_udelay(int us) ++{ ++ __asm__ volatile ("sync"); ++ udelay(us); ++} ++ ++static inline void rc32434_sync_delay(int ms) ++{ ++ __asm__ volatile ("sync"); ++ mdelay(ms); ++} ++ ++/* ++ * C access to CLZ and CLO instructions ++ * (count leading zeroes/ones). ++ */ ++static inline int rc32434_clz(unsigned long val) ++{ ++ int ret; ++ __asm__ volatile ( ++ ".set\tnoreorder\n\t" ++ ".set\tnoat\n\t" ++ ".set\tmips32\n\t" ++ "clz\t%0,%1\n\t" ++ ".set\tmips0\n\t" ++ ".set\tat\n\t" ++ ".set\treorder" ++ : "=r" (ret) ++ : "r" (val)); ++ ++ return ret; ++} ++static inline int rc32434_clo(unsigned long val) ++{ ++ int ret; ++ __asm__ volatile ( ++ ".set\tnoreorder\n\t" ++ ".set\tnoat\n\t" ++ ".set\tmips32\n\t" ++ "clo\t%0,%1\n\t" ++ ".set\tmips0\n\t" ++ ".set\tat\n\t" ++ ".set\treorder" ++ : "=r" (ret) ++ : "r" (val)); ++ ++ return ret; ++} ++ ++extern void cons_putc(char c); ++extern void cons_puts(char *s); ++ ++#endif /* _RC32434_H_ */ +diff -urN linux.old/include/asm-mips/rc32434/rst.h linux.dev/include/asm-mips/rc32434/rst.h +--- linux.old/include/asm-mips/rc32434/rst.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/rst.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,105 @@ ++#ifndef __IDT_RST_H__ ++#define __IDT_RST_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Reset register definitions. ++ * ++ * File : $Id: rst.h,v 1.2 2002/06/06 18:34:05 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020118 ++ * Update : ++ * $Log: rst.h,v $ ++ * Revision 1.2 2002/06/06 18:34:05 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.1 2002/05/29 17:33:24 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ RST0_PhysicalAddress = 0x18000000, ++ RST_PhysicalAddress = RST0_PhysicalAddress, // Default ++ ++ RST0_VirtualAddress = 0xb8000000, ++ RST_VirtualAddress = RST0_VirtualAddress, // Default ++} ; ++ ++typedef struct RST_s ++{ ++ U32 filler [0x0006] ; ++ U32 sysid ; ++ U32 filler2 [0x2000-8] ; // Pad out to offset 0x8000 ++ U32 reset ; ++ U32 bcv ; ++ U32 cea ; ++} volatile * RST_t ; ++ ++enum ++{ ++ SYSID_rev_b = 0, ++ SYSID_rev_m = 0x000000ff, ++ SYSID_imp_b = 8, ++ SYSID_imp_m = 0x000fff00, ++ SYSID_vendor_b = 20, ++ SYSID_vendor_m = 0xfff00000, ++ ++ BCV_pll_b = 0, ++ BCV_pll_m = 0x0000000f, ++ BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK. ++ BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK. ++ BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK. ++ BCV_pll_SlowMul5_v = 0x3, // PCLK=4*CLK. ++ BCV_pll_Mul5_v = 0x4, // PCLK=6*CLK. ++ BCV_pll_SlowMul6_v = 0x5, // PCLK=8*CLK. ++ BCV_pll_Mul6_v = 0x6, // PCLK=8*CLK. ++ BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK. ++ BCV_pll_Mul10_v = 0x8, // PCLK=8*CLK. ++ BCV_pll_Res5_v = 0x9, ++ BCV_pll_Res6_v = 0xa, ++ BCV_pll_Res7_v = 0xb, ++ BCV_pll_Res8_v = 0xc, ++ BCV_pll_Res13_v = 0xd, ++ BCV_pll_Res14_v = 0xe, ++ BCV_pll_Res15_v = 0xf, ++ BCV_clkDiv_b = 4, ++ BCV_clkDiv_m = 0x00000030, ++ BCV_clkDiv_Div1_v = 0x0, ++ BCV_clkDiv_Div2_v = 0x1, ++ BCV_clkDiv_Div4_v = 0x2, ++ BCV_clkDiv_Res3_v = 0x3, ++ BCV_bigEndian_b = 6, ++ BCV_bigEndian_m = 0x00000040, ++ BCV_resetFast_b = 7, ++ BCV_resetFast_m = 0x00000080, ++ BCV_pciMode_b = 8, ++ BCV_pciMode_m = 0x00000100, ++ BCV_pciMode_disabled_v = 0, // PCI is disabled. ++ BCV_pciMode_tnr_v = 1, // satellite Target Not Ready. ++ BCV_pciMode_suspended_v = 2, // satellite with suspended CPU. ++ BCV_pciMode_external_v = 3, // host, external arbiter. ++ BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter. ++ BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter. ++ BCV_pciMode_res6_v = 6, ++ BCV_pciMode_res7_v = 7, ++ BCV_watchDisable_b = 11, ++ BCV_watchDisable_m = 0x00000800, ++ BCV_pllTest_b = 12, ++ BCV_pllTest_m = 0x00001000, ++ BCV_nvramInit_b = 13, ++ BCV_nvramInit_m = 0x00002000, ++ BCV_clksyncTstMd_b = 14, ++ BCV_clksyncTstMd_m = 0x00004000, ++ BCV_delayBypass_b = 15, ++ BCV_delayByPass_m = 0x00008000, ++} ; ++#endif // __IDT_RST_H__ +diff -urN linux.old/include/asm-mips/rc32434/spi.h linux.dev/include/asm-mips/rc32434/spi.h +--- linux.old/include/asm-mips/rc32434/spi.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/spi.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,100 @@ ++#ifndef __IDT_SPI_H__ ++#define __IDT_SPI_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Serial Peripheral Interface register definitions. ++ * ++ * File : $Id: spi.h,v 1.2 2002/06/06 18:34:05 astichte Exp $ ++ * ++ * Author : ryan.holmQVist@idt.com ++ * Date : 20011005 ++ * Update : ++ * $Log: spi.h,v $ ++ * Revision 1.2 2002/06/06 18:34:05 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.1 2002/05/29 17:33:25 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ SPI0_PhysicalAddress = 0x18070000, ++ SPI_PhysicalAddress = SPI0_PhysicalAddress, ++ ++ SPI0_VirtualAddress = 0xb8070000, ++ SPI_VirtualAddress = SPI0_VirtualAddress, ++} ; ++ ++typedef struct ++{ ++ U32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR) ++ U32 spc ; // spi control reg use SPC_ ++ U32 sps ; // spi status reg use SPS_ ++ U32 spd ; // spi data reg use SPD_ ++ U32 siofunc ; // serial IO function use SIOFUNC_ ++ U32 siocfg ; // serial IO config use SIOCFG_ ++ U32 siod; // serial IO data use SIOD_ ++} volatile *SPI_t ; ++ ++enum ++{ ++ SPCP_div_b = 0, ++ SPCP_div_m = 0x000000ff, ++ SPC_spr_b = 0, ++ SPC_spr_m = 0x00000003, ++ SPC_spr_div2_v = 0, ++ SPC_spr_div4_v = 1, ++ SPC_spr_div16_v = 2, ++ SPC_spr_div32_v = 3, ++ SPC_cpha_b = 2, ++ SPC_cpha_m = 0x00000004, ++ SPC_cpol_b = 3, ++ SPC_cpol_m = 0x00000008, ++ SPC_mstr_b = 4, ++ SPC_mstr_m = 0x00000010, ++ SPC_spe_b = 6, ++ SPC_spe_m = 0x00000040, ++ SPC_spie_b = 7, ++ SPC_spie_m = 0x00000080, ++ ++ SPS_modf_b = 4, ++ SPS_modf_m = 0x00000010, ++ SPS_wcol_b = 6, ++ SPS_wcol_m = 0x00000040, ++ SPS_spif_b = 7, ++ SPS_spif_m = 0x00000070, ++ ++ SPD_data_b = 0, ++ SPD_data_m = 0x000000ff, ++ ++ SIOFUNC_sdo_b = 0, ++ SIOFUNC_sdo_m = 0x00000001, ++ SIOFUNC_sdi_b = 1, ++ SIOFUNC_sdi_m = 0x00000002, ++ SIOFUNC_sck_b = 2, ++ SIOFUNC_sck_m = 0x00000004, ++ ++ SIOCFG_sdo_b = 0, ++ SIOCFG_sdo_m = 0x00000001, ++ SIOCFG_sdi_b = 1, ++ SIOCFG_sdi_m = 0x00000002, ++ SIOCFG_sck_b = 2, ++ SIOCFG_sck_m = 0x00000004, ++ ++ SIOD_sdo_b = 0, ++ SIOD_sdo_m = 0x00000001, ++ SIOD_sdi_b = 1, ++ SIOD_sdi_m = 0x00000002, ++ SIOD_sck_b = 2, ++ SIOD_sck_m = 0x00000004, ++} ; ++#endif // __IDT_SPI_H__ +diff -urN linux.old/include/asm-mips/rc32434/timer.h linux.dev/include/asm-mips/rc32434/timer.h +--- linux.old/include/asm-mips/rc32434/timer.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/timer.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,91 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * Definitions for timer registers ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt,neb. ++ * ++ * Initial Release ++ * ++ * ++ * ++ ************************************************************************** ++ */ ++ ++#ifndef __IDT_TIM_H__ ++#define __IDT_TIM_H__ ++ ++enum ++{ ++ TIM0_PhysicalAddress = 0x18028000, ++ TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default ++ ++ TIM0_VirtualAddress = 0xb8028000, ++ TIM_VirtualAddress = TIM0_VirtualAddress, // Default ++} ; ++ ++enum ++{ ++ TIM_Count = 3, ++} ; ++ ++struct TIM_CNTR_s ++{ ++ u32 count ; ++ u32 compare ; ++ u32 ctc ; //use CTC_ ++} ; ++ ++typedef struct TIM_s ++{ ++ struct TIM_CNTR_s tim [TIM_Count] ; ++ u32 rcount ; //use RCOUNT_ ++ u32 rcompare ; //use RCOMPARE_ ++ u32 rtc ; //use RTC_ ++} volatile * TIM_t ; ++ ++enum ++{ ++ CTC_en_b = 0, ++ CTC_en_m = 0x00000001, ++ CTC_to_b = 1, ++ CTC_to_m = 0x00000002, ++ ++ RCOUNT_count_b = 0, ++ RCOUNT_count_m = 0x0000ffff, ++ RCOMPARE_compare_b = 0, ++ RCOMPARE_compare_m = 0x0000ffff, ++ RTC_ce_b = 0, ++ RTC_ce_m = 0x00000001, ++ RTC_to_b = 1, ++ RTC_to_m = 0x00000002, ++ RTC_rqe_b = 2, ++ RTC_rqe_m = 0x00000004, ++ ++} ; ++#endif // __IDT_TIM_H__ ++ +diff -urN linux.old/include/asm-mips/rc32434/tim.h linux.dev/include/asm-mips/rc32434/tim.h +--- linux.old/include/asm-mips/rc32434/tim.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/tim.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,78 @@ ++#ifndef __IDT_TIM_H__ ++#define __IDT_TIM_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Timer register definition. ++ * ++ * File : $Id: tim.h,v 1.2 2002/06/06 18:34:05 astichte Exp $ ++ * ++ * Author : ryan.holmQVist@idt.com ++ * Date : 20011005 ++ * Update : ++ * $Log: tim.h,v $ ++ * Revision 1.2 2002/06/06 18:34:05 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.1 2002/05/29 17:33:25 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ TIM0_PhysicalAddress = 0x18028000, ++ TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default ++ ++ TIM0_VirtualAddress = 0xb8028000, ++ TIM_VirtualAddress = TIM0_VirtualAddress, // Default ++} ; ++ ++enum ++{ ++ TIM_Count = 3, ++} ; ++ ++struct TIM_CNTR_s ++{ ++ U32 count ; ++ U32 compare ; ++ U32 ctc ; //use CTC_ ++} ; ++ ++typedef struct TIM_s ++{ ++ struct TIM_CNTR_s tim [TIM_Count] ; ++ U32 rcount ; //use RCOUNT_ ++ U32 rcompare ; //use RCOMPARE_ ++ U32 rtc ; //use RTC_ ++} volatile * TIM_t ; ++ ++enum ++{ ++ CTC_en_b = 0, ++ CTC_en_m = 0x00000001, ++ CTC_to_b = 1, ++ CTC_to_m = 0x00000002, ++ ++ RCOUNT_count_b = 0, ++ RCOUNT_count_m = 0x0000ffff, ++ RCOMPARE_compare_b = 0, ++ RCOMPARE_compare_m = 0x0000ffff, ++ RTC_ce_b = 0, ++ RTC_ce_m = 0x00000001, ++ RTC_to_b = 1, ++ RTC_to_m = 0x00000002, ++ RTC_rqe_b = 2, ++ RTC_rqe_m = 0x00000004, ++ ++} ; ++#endif // __IDT_TIM_H__ ++ +diff -urN linux.old/include/asm-mips/rc32434/types.h linux.dev/include/asm-mips/rc32434/types.h +--- linux.old/include/asm-mips/rc32434/types.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/types.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,39 @@ ++#ifndef __IDT_TYPES_H__ ++#define __IDT_TYPES_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * Common typedefs used in IDT-generated code. ++ * ++ * File : $Id: types.h,v 1.1 2002/06/06 16:16:56 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020606 ++ * Update : ++ * $Log: types.h,v $ ++ * Revision 1.1 2002/06/06 16:16:56 astichte ++ * Added ++ * ++ * ++ ******************************************************************************/ ++ ++typedef unsigned char U8 ; ++typedef signed char S8 ; ++ ++typedef unsigned short U16 ; ++typedef signed short S16 ; ++ ++typedef unsigned int U32 ; ++typedef signed int S32 ; ++ ++typedef unsigned long long U64 ; ++typedef signed long long S64 ; ++ ++#ifndef __cplusplus ++ typedef U32 bool ; // (false == 0), (true is != false) ++#endif // __cplusplus ++ ++#endif // __IDT_TYPES_H__ +diff -urN linux.old/include/asm-mips/rc32434/uart.h linux.dev/include/asm-mips/rc32434/uart.h +--- linux.old/include/asm-mips/rc32434/uart.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/rc32434/uart.h 2006-10-11 21:56:38.000000000 +0200 +@@ -0,0 +1,178 @@ ++#ifndef __IDT_UART_H__ ++#define __IDT_UART_H__ ++ ++/******************************************************************************* ++ * ++ * Copyright 2002 Integrated Device Technology, Inc. ++ * All rights reserved. ++ * ++ * UART register definitions. ++ * ++ * File : $Id: uart.h,v 1.3 2002/06/06 18:34:05 astichte Exp $ ++ * ++ * Author : Allen.Stichter@idt.com ++ * Date : 20020118 ++ * Update : ++ * $Log: uart.h,v $ ++ * Revision 1.3 2002/06/06 18:34:05 astichte ++ * Added XXX_PhysicalAddress and XXX_VirtualAddress ++ * ++ * Revision 1.2 2002/06/04 17:37:52 astichte ++ * Updated register definitions. ++ * ++ * Revision 1.1 2002/05/29 17:33:25 sysarch ++ * jba File moved from vcode/include/idt/acacia ++ * ++ * ++ ******************************************************************************/ ++ ++#include <asm/rc32434/types.h> ++ ++enum ++{ ++ UART_PhysicalAddress = 0x18058000, ++ UART_PhysicalAddress = UART_PhysicalAddress, // Default ++ ++ UART_VirtualAddress = 0xb8058000, ++ UART_VirtualAddress = UART_VirtualAddress, // Default ++} ; ++ ++/* ++ * Register definitions are in bytes so we can handle endian problems. ++ */ ++ ++typedef struct UART_s ++{ ++ union ++ { ++ U32 const uartrb ; // 0x00 - DLAB=0, read. ++ U32 uartth ; // 0x00 - DLAB=0, write. ++ U32 uartdll ; // 0x00 - DLAB=1, read/write. ++ } ; ++ ++ union ++ { ++ U32 uartie ; // 0x04 - DLAB=0, read/write. ++ U32 uartdlh ; // 0x04 - DLAB=1, read/write. ++ } ; ++ union ++ { ++ U32 const uartii ; // 0x08 - DLAB=0, read. ++ U32 uartfc ; // 0x08 - DLAB=0, write. ++ } ; ++ ++ U32 uartlc ; // 0x0c ++ U32 uartmc ; // 0x10 ++ U32 uartls ; // 0x14 ++ U32 uartms ; // 0x18 ++ U32 uarts ; // 0x1c ++} volatile *UART_t ; ++ ++// Reset registers. ++typedef U32 volatile *UARTRR_t ; ++ ++enum ++{ ++ UARTIE_rda_b = 0, ++ UARTIE_rda_m = 0x00000001, ++ UARTIE_the_b = 1, ++ UARTIE_the_m = 0x00000002, ++ UARTIE_rls_b = 2, ++ UARTIE_rls_m = 0x00000004, ++ UARTIE_ems_b = 3, ++ UARTIE_ems_m = 0x00000008, ++ ++ UARTII_pi_b = 0, ++ UARTII_pi_m = 0x00000001, ++ UARTII_iid_b = 1, ++ UARTII_iid_m = 0x0000000e, ++ UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD. ++ UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty. ++ UARTII_iid_rda_v = 2, // Receive data available ++ UARTII_iid_rls_v = 3, // Overrun, parity, etc, error. ++ UARTII_iid_res4_v = 4, // reserved. ++ UARTII_iid_res5_v = 5, // reserved. ++ UARTII_iid_cto_v = 6, // Character timeout. ++ UARTII_iid_res7_v = 7, // reserved. ++ ++ UARTFC_en_b = 0, ++ UARTFC_en_m = 0x00000001, ++ UARTFC_rr_b = 1, ++ UARTFC_rr_m = 0x00000002, ++ UARTFC_tr_b = 2, ++ UARTFC_tr_m = 0x00000004, ++ UARTFC_dms_b = 3, ++ UARTFC_dms_m = 0x00000008, ++ UARTFC_rt_b = 6, ++ UARTFC_rt_m = 0x000000c0, ++ UARTFC_rt_1Byte_v = 0, ++ UARTFC_rt_4Byte_v = 1, ++ UARTFC_rt_8Byte_v = 2, ++ UARTFC_rt_14Byte_v = 3, ++ ++ UARTLC_wls_b = 0, ++ UARTLC_wls_m = 0x00000003, ++ UARTLC_wls_5Bits_v = 0, ++ UARTLC_wls_6Bits_v = 1, ++ UARTLC_wls_7Bits_v = 2, ++ UARTLC_wls_8Bits_v = 3, ++ UARTLC_stb_b = 2, ++ UARTLC_stb_m = 0x00000004, ++ UARTLC_pen_b = 3, ++ UARTLC_pen_m = 0x00000008, ++ UARTLC_eps_b = 4, ++ UARTLC_eps_m = 0x00000010, ++ UARTLC_sp_b = 5, ++ UARTLC_sp_m = 0x00000020, ++ UARTLC_sb_b = 6, ++ UARTLC_sb_m = 0x00000040, ++ UARTLC_dlab_b = 7, ++ UARTLC_dlab_m = 0x00000080, ++ ++ UARTMC_dtr_b = 0, ++ UARTMC_dtr_m = 0x00000001, ++ UARTMC_rts_b = 1, ++ UARTMC_rts_m = 0x00000002, ++ UARTMC_o1_b = 2, ++ UARTMC_o1_m = 0x00000004, ++ UARTMC_o2_b = 3, ++ UARTMC_o2_m = 0x00000008, ++ UARTMC_lp_b = 4, ++ UARTMC_lp_m = 0x00000010, ++ ++ UARTLS_dr_b = 0, ++ UARTLS_dr_m = 0x00000001, ++ UARTLS_oe_b = 1, ++ UARTLS_oe_m = 0x00000002, ++ UARTLS_pe_b = 2, ++ UARTLS_pe_m = 0x00000004, ++ UARTLS_fe_b = 3, ++ UARTLS_fe_m = 0x00000008, ++ UARTLS_bi_b = 4, ++ UARTLS_bi_m = 0x00000010, ++ UARTLS_thr_b = 5, ++ UARTLS_thr_m = 0x00000020, ++ UARTLS_te_b = 6, ++ UARTLS_te_m = 0x00000040, ++ UARTLS_rfe_b = 7, ++ UARTLS_rfe_m = 0x00000080, ++ ++ UARTMS_dcts_b = 0, ++ UARTMS_dcts_m = 0x00000001, ++ UARTMS_ddsr_b = 1, ++ UARTMS_ddsr_m = 0x00000002, ++ UARTMS_teri_b = 2, ++ UARTMS_teri_m = 0x00000004, ++ UARTMS_ddcd_b = 3, ++ UARTMS_ddcd_m = 0x00000008, ++ UARTMS_cts_b = 4, ++ UARTMS_cts_m = 0x00000010, ++ UARTMS_dsr_b = 5, ++ UARTMS_dsr_m = 0x00000020, ++ UARTMS_ri_b = 6, ++ UARTMS_ri_m = 0x00000040, ++ UARTMS_dcd_b = 7, ++ UARTMS_dcd_m = 0x00000080, ++} ; ++ ++#endif // __IDT_UART_H__ diff --git a/target/linux/rb532-2.6/patches/110-korina_ethernet.patch b/target/linux/rb532-2.6/patches/110-korina_ethernet.patch new file mode 100644 index 0000000000..723bc4ff10 --- /dev/null +++ b/target/linux/rb532-2.6/patches/110-korina_ethernet.patch @@ -0,0 +1,1375 @@ +diff -urN linux.old/drivers/net/Kconfig linux.dev/drivers/net/Kconfig +--- linux.old/drivers/net/Kconfig 2006-06-08 20:21:20.000000000 +0200 ++++ linux.dev/drivers/net/Kconfig 2006-06-08 20:19:40.000000000 +0200 +@@ -310,6 +310,13 @@ + + source "drivers/net/arm/Kconfig" + ++config KORINA ++ tristate "Korina Local Ethernet support" ++ depends on NET_ETHERNET && ( IDT_EB434 || MIKROTIK_RB500) ++ help ++ IDT RC32434 has one local ethernet port. Say Y here to enable it. ++ To compile this driver as a module, choose M here. ++ + config MACE + tristate "MACE (Power Mac ethernet) support" + depends on NET_ETHERNET && PPC_PMAC && PPC32 +diff -urN linux.old/drivers/net/korina.c linux.dev/drivers/net/korina.c +--- linux.old/drivers/net/korina.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/drivers/net/korina.c 2006-06-09 00:48:40.000000000 +0200 +@@ -0,0 +1,1159 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * Driver for the IDT RC32434 on-chip ethernet controller. ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb ++ * ++ * Based on the driver developed by B. Maruthanayakam, H. Kou and others. ++ * ++ * Aug 2004 Sadik ++ * ++ * Added NAPI ++ * ++ ************************************************************************** ++ */ ++ ++#include <linux/config.h> ++#include <linux/module.h> ++#include <linux/kernel.h> ++#include <linux/moduleparam.h> ++#include <linux/sched.h> ++#include <linux/ctype.h> ++#include <linux/types.h> ++#include <linux/fcntl.h> ++#include <linux/interrupt.h> ++#include <linux/ptrace.h> ++#include <linux/init.h> ++#include <linux/ioport.h> ++#include <linux/proc_fs.h> ++#include <linux/in.h> ++#include <linux/slab.h> ++#include <linux/string.h> ++#include <linux/delay.h> ++#include <linux/netdevice.h> ++#include <linux/etherdevice.h> ++#include <linux/skbuff.h> ++#include <linux/errno.h> ++#include <linux/platform_device.h> ++#include <asm/bootinfo.h> ++#include <asm/system.h> ++#include <asm/bitops.h> ++#include <asm/pgtable.h> ++#include <asm/segment.h> ++#include <asm/io.h> ++#include <asm/dma.h> ++ ++#include <asm/rc32434/rb.h> ++#include "rc32434_eth.h" ++ ++#define DRIVER_VERSION "(mar2904)" ++ ++#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION ++ ++#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \ ++ ((dev)->dev_addr[1])) ++#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \ ++ ((dev)->dev_addr[3] << 16) | \ ++ ((dev)->dev_addr[4] << 8) | \ ++ ((dev)->dev_addr[5])) ++ ++#define MII_CLOCK 1250000 /* no more than 2.5MHz */ ++#define CONFIG_IDT_USE_NAPI 1 ++ ++ ++static inline void rc32434_abort_tx(struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ rc32434_abort_dma(dev, lp->tx_dma_regs); ++ ++} ++ ++static inline void rc32434_abort_rx(struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ rc32434_abort_dma(dev, lp->rx_dma_regs); ++ ++} ++ ++static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td) ++{ ++ rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td)); ++} ++ ++static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd) ++{ ++ rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd)); ++} ++ ++static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td) ++{ ++ rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td)); ++} ++ ++static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd) ++{ ++ rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd)); ++} ++ ++#ifdef RC32434_PROC_DEBUG ++static int rc32434_read_proc(char *buf, char **start, off_t fpos, ++ int length, int *eof, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ int len = 0; ++ ++ /* print out header */ ++ len += sprintf(buf + len, "\n\tKorina Ethernet Debug\n\n"); ++ len += sprintf (buf + len, ++ "DMA halt count = %10d, DMA run count = %10d\n", ++ lp->dma_halt_cnt, lp->dma_run_cnt); ++ ++ if (fpos >= len) { ++ *start = buf; ++ *eof = 1; ++ return 0; ++ } ++ *start = buf + fpos; ++ ++ if ((len -= fpos) > length) ++ return length; ++ *eof = 1; ++ ++ return len; ++ ++} ++#endif ++ ++ ++/* ++ * Restart the RC32434 ethernet controller. ++ */ ++static int rc32434_restart(struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ ++ /* ++ * Disable interrupts ++ */ ++ disable_irq(lp->rx_irq); ++ disable_irq(lp->tx_irq); ++#ifdef RC32434_REVISION ++ disable_irq(lp->ovr_irq); ++#endif ++ disable_irq(lp->und_irq); ++ ++ /* Mask F E bit in Tx DMA */ ++ __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm); ++ /* Mask D H E bit in Rx DMA */ ++ __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm); ++ ++ rc32434_init(dev); ++ rc32434_multicast_list(dev); ++ ++ enable_irq(lp->und_irq); ++#ifdef RC32434_REVISION ++ enable_irq(lp->ovr_irq); ++#endif ++ enable_irq(lp->tx_irq); ++ enable_irq(lp->rx_irq); ++ ++ return 0; ++} ++ ++static int rc32434_probe(struct platform_device *pdev) ++{ ++ struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data; ++ struct rc32434_local *lp = NULL; ++ struct net_device *dev = NULL; ++ struct resource *r; ++ int i, retval,err; ++ ++ dev = alloc_etherdev(sizeof(struct rc32434_local)); ++ if(!dev) { ++ ERR("Korina_eth: alloc_etherdev failed\n"); ++ return -1; ++ } ++ ++ platform_set_drvdata(pdev, dev); ++ SET_MODULE_OWNER(dev); ++ bif->dev = dev; ++ ++ memcpy(dev->dev_addr, bif->mac, 6); ++ ++ /* Initialize the device structure. */ ++ if (dev->priv == NULL) { ++ lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL); ++ memset(lp, 0, sizeof(struct rc32434_local)); ++ } ++ else { ++ lp = (struct rc32434_local *)dev->priv; ++ } ++ ++ lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx"); ++ lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx"); ++ lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr"); ++ lp->und_irq = platform_get_irq_byname(pdev, "korina_und"); ++ ++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs"); ++ dev->base_addr = r->start; ++ lp->eth_regs = ioremap_nocache(r->start, r->end - r->start); ++ if (!lp->eth_regs) { ++ ERR("Can't remap eth registers\n"); ++ retval = -ENXIO; ++ goto probe_err_out; ++ } ++ ++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx"); ++ lp->rx_dma_regs = ioremap_nocache(r->start, r->end - r->start); ++ if (!lp->rx_dma_regs) { ++ ERR("Can't remap Rx DMA registers\n"); ++ retval = -ENXIO; ++ goto probe_err_out; ++ } ++ ++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx"); ++ lp->tx_dma_regs = ioremap_nocache(r->start, r->end - r->start); ++ if (!lp->tx_dma_regs) { ++ ERR("Can't remap Tx DMA registers\n"); ++ retval = -ENXIO; ++ goto probe_err_out; ++ } ++ ++#ifdef RC32434_PROC_DEBUG ++ lp->ps = create_proc_read_entry (bif->name, 0, proc_net, ++ rc32434_read_proc, dev); ++#endif ++ ++ lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL); ++ if (!lp->td_ring) { ++ ERR("Can't allocate descriptors\n"); ++ retval = -ENOMEM; ++ goto probe_err_out; ++ } ++ ++ dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE); ++ ++ /* now convert TD_RING pointer to KSEG1 */ ++ lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring); ++ lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS]; ++ ++ ++ spin_lock_init(&lp->lock); ++ ++ /* just use the rx dma irq */ ++ dev->irq = lp->rx_irq; ++ ++ dev->priv = lp; ++ ++ dev->open = rc32434_open; ++ dev->stop = rc32434_close; ++ dev->hard_start_xmit = rc32434_send_packet; ++ dev->get_stats = rc32434_get_stats; ++ dev->set_multicast_list = &rc32434_multicast_list; ++ dev->tx_timeout = rc32434_tx_timeout; ++ dev->watchdog_timeo = RC32434_TX_TIMEOUT; ++ ++#ifdef CONFIG_IDT_USE_NAPI ++ dev->poll = rc32434_poll; ++ dev->weight = 64; ++ printk("Using NAPI with weight %d\n",dev->weight); ++#else ++ lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL); ++ tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev); ++#endif ++ lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL); ++ tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev); ++ ++ if ((err = register_netdev(dev))) { ++ printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err); ++ free_netdev(dev); ++ retval = -EINVAL; ++ goto probe_err_out; ++ } ++ ++ INFO("Rx IRQ %d, Tx IRQ %d, ", lp->rx_irq, lp->tx_irq); ++ for (i = 0; i < 6; i++) { ++ printk("%2.2x", dev->dev_addr[i]); ++ if (i<5) ++ printk(":"); ++ } ++ printk("\n"); ++ ++ return 0; ++ ++ probe_err_out: ++ rc32434_cleanup_module(); ++ ERR(" failed. Returns %d\n", retval); ++ return retval; ++ ++} ++ ++static int rc32434_remove(struct platform_device *pdev) ++{ ++ struct korina_device *bif = (struct korina_device *) pdev->dev.platform_data; ++ ++ if (bif->dev != NULL) { ++ struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv; ++ if (lp != NULL) { ++ if (lp->eth_regs) ++ iounmap((void*)lp->eth_regs); ++ if (lp->rx_dma_regs) ++ iounmap((void*)lp->rx_dma_regs); ++ if (lp->tx_dma_regs) ++ iounmap((void*)lp->tx_dma_regs); ++ if (lp->td_ring) ++ kfree((void*)KSEG0ADDR(lp->td_ring)); ++ ++#ifdef RC32434_PROC_DEBUG ++ if (lp->ps) { ++ remove_proc_entry(bif->name, proc_net); ++ } ++#endif ++ kfree(lp); ++ } ++ ++ platform_set_drvdata(pdev, NULL); ++ unregister_netdev(bif->dev); ++ free_netdev(bif->dev); ++ kfree(bif->dev); ++ } ++ return 0; ++} ++ ++ ++static int rc32434_open(struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ ++ /* Initialize */ ++ if (rc32434_init(dev)) { ++ ERR("Error: cannot open the Ethernet device\n"); ++ return -EAGAIN; ++ } ++ ++ /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */ ++ if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt, ++ SA_SHIRQ | SA_INTERRUPT, ++ "Korina ethernet Rx", dev)) { ++ ERR(": unable to get Rx DMA IRQ %d\n", ++ lp->rx_irq); ++ return -EAGAIN; ++ } ++ if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt, ++ SA_SHIRQ | SA_INTERRUPT, ++ "Korina ethernet Tx", dev)) { ++ ERR(": unable to get Tx DMA IRQ %d\n", ++ lp->tx_irq); ++ free_irq(lp->rx_irq, dev); ++ return -EAGAIN; ++ } ++ ++#ifdef RC32434_REVISION ++ /* Install handler for overrun error. */ ++ if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt, ++ SA_SHIRQ | SA_INTERRUPT, ++ "Ethernet Overflow", dev)) { ++ ERR(": unable to get OVR IRQ %d\n", ++ lp->ovr_irq); ++ free_irq(lp->rx_irq, dev); ++ free_irq(lp->tx_irq, dev); ++ return -EAGAIN; ++ } ++#endif ++ ++ /* Install handler for underflow error. */ ++ if (request_irq(lp->und_irq, &rc32434_und_interrupt, ++ SA_SHIRQ | SA_INTERRUPT, ++ "Ethernet Underflow", dev)) { ++ ERR(": unable to get UND IRQ %d\n", ++ lp->und_irq); ++ free_irq(lp->rx_irq, dev); ++ free_irq(lp->tx_irq, dev); ++#ifdef RC32434_REVISION ++ free_irq(lp->ovr_irq, dev); ++#endif ++ return -EAGAIN; ++ } ++ ++ ++ return 0; ++} ++ ++ ++ ++ ++static int rc32434_close(struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ u32 tmp; ++ ++ /* Disable interrupts */ ++ disable_irq(lp->rx_irq); ++ disable_irq(lp->tx_irq); ++#ifdef RC32434_REVISION ++ disable_irq(lp->ovr_irq); ++#endif ++ disable_irq(lp->und_irq); ++ ++ tmp = __raw_readl(&lp->tx_dma_regs->dmasm); ++ tmp = tmp | DMASM_f_m | DMASM_e_m; ++ __raw_writel(tmp, &lp->tx_dma_regs->dmasm); ++ ++ tmp = __raw_readl(&lp->rx_dma_regs->dmasm); ++ tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m; ++ __raw_writel(tmp, &lp->rx_dma_regs->dmasm); ++ ++ free_irq(lp->rx_irq, dev); ++ free_irq(lp->tx_irq, dev); ++#ifdef RC32434_REVISION ++ free_irq(lp->ovr_irq, dev); ++#endif ++ free_irq(lp->und_irq, dev); ++ return 0; ++} ++ ++ ++/* transmit packet */ ++static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ unsigned long flags; ++ u32 length; ++ DMAD_t td; ++ ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ ++ td = &lp->td_ring[lp->tx_chain_tail]; ++ ++ /* stop queue when full, drop pkts if queue already full */ ++ if(lp->tx_count >= (RC32434_NUM_TDS - 2)) { ++ lp->tx_full = 1; ++ ++ if(lp->tx_count == (RC32434_NUM_TDS - 2)) { ++ netif_stop_queue(dev); ++ } ++ else { ++ lp->stats.tx_dropped++; ++ dev_kfree_skb_any(skb); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ return 1; ++ } ++ } ++ ++ lp->tx_count ++; ++ ++ lp->tx_skb[lp->tx_chain_tail] = skb; ++ ++ length = skb->len; ++ ++ /* Setup the transmit descriptor. */ ++ td->ca = CPHYSADDR(skb->data); ++ ++ if(__raw_readl(&(lp->tx_dma_regs->dmandptr)) == 0) { ++ if( lp->tx_chain_status == empty ) { ++ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */ ++ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */ ++ __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */ ++ lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */ ++ } ++ else { ++ td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */ ++ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */ ++ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */ ++ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */ ++ __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */ ++ lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */ ++ lp->tx_chain_status = empty; ++ } ++ } ++ else { ++ if( lp->tx_chain_status == empty ) { ++ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */ ++ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */ ++ lp->tx_chain_status = filled; ++ } ++ else { ++ td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */ ++ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */ ++ lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */ ++ lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */ ++ } ++ } ++ ++ dev->trans_start = jiffies; ++ ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++ return 0; ++} ++ ++ ++/* Ethernet MII-PHY Handler */ ++static void rc32434_mii_handler(unsigned long data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ unsigned long flags; ++ unsigned long duplex_status; ++ int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ ++ /* Two ports are using the same MII, the difference is the PHY address */ ++ __raw_writel(0, &rc32434_eth0_regs->miimcfg); ++ __raw_writel(0, &rc32434_eth0_regs->miimcmd); ++ __raw_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr); ++ __raw_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd); ++ while(__raw_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m); ++ ++ ERR("irq:%x port_addr:%x RDD:%x\n", ++ lp->rx_irq, port_addr, __raw_readl(&rc32434_eth0_regs->miimrdd)); ++ duplex_status = (__raw_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0; ++ if(duplex_status != lp->duplex_mode) { ++ ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0); ++ lp->duplex_mode = duplex_status; ++ rc32434_restart(dev); ++ } ++ ++ lp->mii_phy_timer.expires = jiffies + 10 * HZ; ++ add_timer(&lp->mii_phy_timer); ++ ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++} ++ ++#ifdef RC32434_REVISION ++/* Ethernet Rx Overflow interrupt */ ++static irqreturn_t ++rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs) ++{ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct rc32434_local *lp; ++ unsigned int ovr; ++ irqreturn_t retval = IRQ_NONE; ++ ++ ASSERT(dev != NULL); ++ ++ lp = (struct rc32434_local *)dev->priv; ++ spin_lock(&lp->lock); ++ ovr = __raw_readl(&lp->eth_regs->ethintfc); ++ ++ if(ovr & ETHINTFC_ovr_m) { ++ netif_stop_queue(dev); ++ ++ /* clear OVR bit */ ++ __raw_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc); ++ ++ /* Restart interface */ ++ rc32434_restart(dev); ++ retval = IRQ_HANDLED; ++ } ++ spin_unlock(&lp->lock); ++ ++ return retval; ++} ++ ++#endif ++ ++ ++/* Ethernet Tx Underflow interrupt */ ++static irqreturn_t ++rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs) ++{ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct rc32434_local *lp; ++ unsigned int und; ++ irqreturn_t retval = IRQ_NONE; ++ ++ ASSERT(dev != NULL); ++ ++ lp = (struct rc32434_local *)dev->priv; ++ ++ spin_lock(&lp->lock); ++ ++ und = __raw_readl(&lp->eth_regs->ethintfc); ++ ++ if(und & ETHINTFC_und_m) { ++ netif_stop_queue(dev); ++ ++ __raw_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc); ++ ++ /* Restart interface */ ++ rc32434_restart(dev); ++ retval = IRQ_HANDLED; ++ } ++ ++ spin_unlock(&lp->lock); ++ ++ return retval; ++} ++ ++ ++/* Ethernet Rx DMA interrupt */ ++static irqreturn_t ++rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs) ++{ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct rc32434_local* lp; ++ volatile u32 dmas,dmasm; ++ irqreturn_t retval; ++ ++ ASSERT(dev != NULL); ++ ++ lp = (struct rc32434_local *)dev->priv; ++ ++ spin_lock(&lp->lock); ++ dmas = __raw_readl(&lp->rx_dma_regs->dmas); ++ if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) { ++ /* Mask D H E bit in Rx DMA */ ++ dmasm = __raw_readl(&lp->rx_dma_regs->dmasm); ++ __raw_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm); ++#ifdef CONFIG_IDT_USE_NAPI ++ if(netif_rx_schedule_prep(dev)) ++ __netif_rx_schedule(dev); ++#else ++ tasklet_hi_schedule(lp->rx_tasklet); ++#endif ++ ++ if (dmas & DMAS_e_m) ++ ERR(": DMA error\n"); ++ ++ retval = IRQ_HANDLED; ++ } ++ else ++ retval = IRQ_NONE; ++ ++ spin_unlock(&lp->lock); ++ return retval; ++} ++ ++#ifdef CONFIG_IDT_USE_NAPI ++static int rc32434_poll(struct net_device *rx_data_dev, int *budget) ++#else ++static void rc32434_rx_tasklet(unsigned long rx_data_dev) ++#endif ++{ ++ struct net_device *dev = (struct net_device *)rx_data_dev; ++ struct rc32434_local* lp = netdev_priv(dev); ++ volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done]; ++ struct sk_buff *skb, *skb_new; ++ u8* pkt_buf; ++ u32 devcs, count, pkt_len, pktuncrc_len; ++ volatile u32 dmas; ++#ifdef CONFIG_IDT_USE_NAPI ++ u32 received = 0; ++ int rx_work_limit = min(*budget,dev->quota); ++#else ++ unsigned long flags; ++ spin_lock_irqsave(&lp->lock, flags); ++#endif ++ ++ while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) { ++#ifdef CONFIG_IDT_USE_NAPI ++ if(--rx_work_limit <0) ++ { ++ break; ++ } ++#endif ++ /* init the var. used for the later operations within the while loop */ ++ skb_new = NULL; ++ devcs = rd->devcs; ++ pkt_len = RCVPKT_LENGTH(devcs); ++ skb = lp->rx_skb[lp->rx_next_done]; ++ ++ if (count < 64) { ++ lp->stats.rx_errors++; ++ lp->stats.rx_dropped++; ++ } ++ else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) { ++ /* check that this is a whole packet */ ++ /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */ ++ lp->stats.rx_errors++; ++ lp->stats.rx_dropped++; ++ } ++ else if ( (devcs & ETHRX_rok_m) ) { ++ ++ { ++ /* must be the (first and) last descriptor then */ ++ pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data; ++ ++ pktuncrc_len = pkt_len - 4; ++ /* invalidate the cache */ ++ dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len); ++ ++ /* Malloc up new buffer. */ ++ skb_new = dev_alloc_skb(RC32434_RBSIZE + 2); ++ ++ if (skb_new != NULL){ ++ /* Make room */ ++ skb_put(skb, pktuncrc_len); ++ ++ skb->protocol = eth_type_trans(skb, dev); ++ ++ /* pass the packet to upper layers */ ++#ifdef CONFIG_IDT_USE_NAPI ++ netif_receive_skb(skb); ++#else ++ netif_rx(skb); ++#endif ++ ++ dev->last_rx = jiffies; ++ lp->stats.rx_packets++; ++ lp->stats.rx_bytes += pktuncrc_len; ++ ++ if (IS_RCV_MP(devcs)) ++ lp->stats.multicast++; ++ ++ /* 16 bit align */ ++ skb_reserve(skb_new, 2); ++ ++ skb_new->dev = dev; ++ lp->rx_skb[lp->rx_next_done] = skb_new; ++ } ++ else { ++ ERR("no memory, dropping rx packet.\n"); ++ lp->stats.rx_errors++; ++ lp->stats.rx_dropped++; ++ } ++ } ++ ++ } ++ else { ++ /* This should only happen if we enable accepting broken packets */ ++ lp->stats.rx_errors++; ++ lp->stats.rx_dropped++; ++ ++ /* add statistics counters */ ++ if (IS_RCV_CRC_ERR(devcs)) { ++ DBG(2, "RX CRC error\n"); ++ lp->stats.rx_crc_errors++; ++ } ++ else if (IS_RCV_LOR_ERR(devcs)) { ++ DBG(2, "RX LOR error\n"); ++ lp->stats.rx_length_errors++; ++ } ++ else if (IS_RCV_LE_ERR(devcs)) { ++ DBG(2, "RX LE error\n"); ++ lp->stats.rx_length_errors++; ++ } ++ else if (IS_RCV_OVR_ERR(devcs)) { ++ lp->stats.rx_over_errors++; ++ } ++ else if (IS_RCV_CV_ERR(devcs)) { ++ /* code violation */ ++ DBG(2, "RX CV error\n"); ++ lp->stats.rx_frame_errors++; ++ } ++ else if (IS_RCV_CES_ERR(devcs)) { ++ DBG(2, "RX Preamble error\n"); ++ } ++ } ++ ++ rd->devcs = 0; ++ ++ /* restore descriptor's curr_addr */ ++ if(skb_new) ++ rd->ca = CPHYSADDR(skb_new->data); ++ else ++ rd->ca = CPHYSADDR(skb->data); ++ ++ rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m; ++ lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m); ++ ++ lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK; ++ rd = &lp->rd_ring[lp->rx_next_done]; ++ __raw_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas); ++ } ++#ifdef CONFIG_IDT_USE_NAPI ++ dev->quota -= received; ++ *budget =- received; ++ if(rx_work_limit < 0) ++ goto not_done; ++#endif ++ ++ dmas = __raw_readl(&lp->rx_dma_regs->dmas); ++ ++ if(dmas & DMAS_h_m) { ++ __raw_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas); ++#ifdef RC32434_PROC_DEBUG ++ lp->dma_halt_cnt++; ++#endif ++ rd->devcs = 0; ++ skb = lp->rx_skb[lp->rx_next_done]; ++ rd->ca = CPHYSADDR(skb->data); ++ rc32434_chain_rx(lp,rd); ++ } ++ ++#ifdef CONFIG_IDT_USE_NAPI ++ netif_rx_complete(dev); ++#endif ++ /* Enable D H E bit in Rx DMA */ ++ __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm); ++#ifdef CONFIG_IDT_USE_NAPI ++ return 0; ++ not_done: ++ return 1; ++#else ++ spin_unlock_irqrestore(&lp->lock, flags); ++ return; ++#endif ++ ++ ++} ++ ++ ++ ++/* Ethernet Tx DMA interrupt */ ++static irqreturn_t ++rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs) ++{ ++ struct net_device *dev = (struct net_device *)dev_id; ++ struct rc32434_local *lp; ++ volatile u32 dmas,dmasm; ++ irqreturn_t retval; ++ ++ ASSERT(dev != NULL); ++ ++ lp = (struct rc32434_local *)dev->priv; ++ ++ spin_lock(&lp->lock); ++ ++ dmas = __raw_readl(&lp->tx_dma_regs->dmas); ++ ++ if (dmas & (DMAS_f_m | DMAS_e_m)) { ++ dmasm = __raw_readl(&lp->tx_dma_regs->dmasm); ++ /* Mask F E bit in Tx DMA */ ++ __raw_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); ++ ++ tasklet_hi_schedule(lp->tx_tasklet); ++ ++ if(lp->tx_chain_status == filled && (__raw_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) { ++ __raw_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); ++ lp->tx_chain_status = empty; ++ lp->tx_chain_head = lp->tx_chain_tail; ++ dev->trans_start = jiffies; ++ } ++ ++ if (dmas & DMAS_e_m) ++ ERR(": DMA error\n"); ++ ++ retval = IRQ_HANDLED; ++ } ++ else ++ retval = IRQ_NONE; ++ ++ spin_unlock(&lp->lock); ++ ++ return retval; ++} ++ ++ ++static void rc32434_tx_tasklet(unsigned long tx_data_dev) ++{ ++ struct net_device *dev = (struct net_device *)tx_data_dev; ++ struct rc32434_local* lp = (struct rc32434_local *)dev->priv; ++ volatile DMAD_t td = &lp->td_ring[lp->tx_next_done]; ++ u32 devcs; ++ unsigned long flags; ++ volatile u32 dmas; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ ++ /* process all desc that are done */ ++ while(IS_DMA_FINISHED(td->control)) { ++ if(lp->tx_full == 1) { ++ netif_wake_queue(dev); ++ lp->tx_full = 0; ++ } ++ ++ devcs = lp->td_ring[lp->tx_next_done].devcs; ++ if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) { ++ lp->stats.tx_errors++; ++ lp->stats.tx_dropped++; ++ ++ /* should never happen */ ++ DBG(1, __FUNCTION__ ": split tx ignored\n"); ++ } ++ else if (IS_TX_TOK(devcs)) { ++ lp->stats.tx_packets++; ++ } ++ else { ++ lp->stats.tx_errors++; ++ lp->stats.tx_dropped++; ++ ++ /* underflow */ ++ if (IS_TX_UND_ERR(devcs)) ++ lp->stats.tx_fifo_errors++; ++ ++ /* oversized frame */ ++ if (IS_TX_OF_ERR(devcs)) ++ lp->stats.tx_aborted_errors++; ++ ++ /* excessive deferrals */ ++ if (IS_TX_ED_ERR(devcs)) ++ lp->stats.tx_carrier_errors++; ++ ++ /* collisions: medium busy */ ++ if (IS_TX_EC_ERR(devcs)) ++ lp->stats.collisions++; ++ ++ /* late collision */ ++ if (IS_TX_LC_ERR(devcs)) ++ lp->stats.tx_window_errors++; ++ ++ } ++ ++ /* We must always free the original skb */ ++ if (lp->tx_skb[lp->tx_next_done] != NULL) { ++ dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]); ++ lp->tx_skb[lp->tx_next_done] = NULL; ++ } ++ ++ lp->td_ring[lp->tx_next_done].control = DMAD_iof_m; ++ lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m; ++ lp->td_ring[lp->tx_next_done].link = 0; ++ lp->td_ring[lp->tx_next_done].ca = 0; ++ lp->tx_count --; ++ ++ /* go on to next transmission */ ++ lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK; ++ td = &lp->td_ring[lp->tx_next_done]; ++ ++ } ++ ++ dmas = __raw_readl(&lp->tx_dma_regs->dmas); ++ __raw_writel( ~dmas, &lp->tx_dma_regs->dmas); ++ ++ /* Enable F E bit in Tx DMA */ ++ __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++} ++ ++ ++static struct net_device_stats * rc32434_get_stats(struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ return &lp->stats; ++} ++ ++ ++/* ++ * Set or clear the multicast filter for this adaptor. ++ */ ++static void rc32434_multicast_list(struct net_device *dev) ++{ ++ /* listen to broadcasts always and to treat */ ++ /* IFF bits independantly */ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ unsigned long flags; ++ u32 recognise = ETHARC_ab_m; /* always accept broadcasts */ ++ ++ if (dev->flags & IFF_PROMISC) /* set promiscuous mode */ ++ recognise |= ETHARC_pro_m; ++ ++ if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15)) ++ recognise |= ETHARC_am_m; /* all multicast & bcast */ ++ else if (dev->mc_count > 0) { ++ DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count); ++ recognise |= ETHARC_am_m; /* for the time being */ ++ } ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ __raw_writel(recognise, &lp->eth_regs->etharc); ++ spin_unlock_irqrestore(&lp->lock, flags); ++} ++ ++ ++static void rc32434_tx_timeout(struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&lp->lock, flags); ++ rc32434_restart(dev); ++ spin_unlock_irqrestore(&lp->lock, flags); ++ ++} ++ ++ ++/* ++ * Initialize the RC32434 ethernet controller. ++ */ ++static int rc32434_init(struct net_device *dev) ++{ ++ struct rc32434_local *lp = (struct rc32434_local *)dev->priv; ++ int i, j; ++ ++ /* Disable DMA */ ++ rc32434_abort_tx(dev); ++ rc32434_abort_rx(dev); ++ ++ /* reset ethernet logic */ ++ __raw_writel(0, &lp->eth_regs->ethintfc); ++ while((__raw_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m)) ++ dev->trans_start = jiffies; ++ ++ /* Enable Ethernet Interface */ ++ __raw_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc); ++ ++#ifndef CONFIG_IDT_USE_NAPI ++ tasklet_disable(lp->rx_tasklet); ++#endif ++ tasklet_disable(lp->tx_tasklet); ++ ++ /* Initialize the transmit Descriptors */ ++ for (i = 0; i < RC32434_NUM_TDS; i++) { ++ lp->td_ring[i].control = DMAD_iof_m; ++ lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m; ++ lp->td_ring[i].ca = 0; ++ lp->td_ring[i].link = 0; ++ if (lp->tx_skb[i] != NULL) { ++ dev_kfree_skb_any(lp->tx_skb[i]); ++ lp->tx_skb[i] = NULL; ++ } ++ } ++ lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0; ++ lp-> tx_chain_status = empty; ++ ++ /* ++ * Initialize the receive descriptors so that they ++ * become a circular linked list, ie. let the last ++ * descriptor point to the first again. ++ */ ++ for (i=0; i<RC32434_NUM_RDS; i++) { ++ struct sk_buff *skb = lp->rx_skb[i]; ++ ++ if (lp->rx_skb[i] == NULL) { ++ skb = dev_alloc_skb(RC32434_RBSIZE + 2); ++ if (skb == NULL) { ++ ERR("No memory in the system\n"); ++ for (j = 0; j < RC32434_NUM_RDS; j ++) ++ if (lp->rx_skb[j] != NULL) ++ dev_kfree_skb_any(lp->rx_skb[j]); ++ ++ return 1; ++ } ++ else { ++ skb->dev = dev; ++ skb_reserve(skb, 2); ++ lp->rx_skb[i] = skb; ++ lp->rd_ring[i].ca = CPHYSADDR(skb->data); ++ ++ } ++ } ++ lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE); ++ lp->rd_ring[i].devcs = 0; ++ lp->rd_ring[i].ca = CPHYSADDR(skb->data); ++ lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]); ++ ++ } ++ /* loop back */ ++ lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]); ++ lp->rx_next_done = 0; ++ ++ lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m; ++ lp->rx_chain_head = 0; ++ lp->rx_chain_tail = 0; ++ lp->rx_chain_status = empty; ++ ++ __raw_writel(0, &lp->rx_dma_regs->dmas); ++ /* Start Rx DMA */ ++ rc32434_start_rx(lp, &lp->rd_ring[0]); ++ ++ /* Enable F E bit in Tx DMA */ ++ __raw_writel(__raw_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm); ++ /* Enable D H E bit in Rx DMA */ ++ __raw_writel(__raw_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm); ++ ++ /* Accept only packets destined for this Ethernet device address */ ++ __raw_writel(ETHARC_ab_m, &lp->eth_regs->etharc); ++ ++ /* Set all Ether station address registers to their initial values */ ++ __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); ++ __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0); ++ ++ __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); ++ __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1); ++ ++ __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); ++ __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2); ++ ++ __raw_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); ++ __raw_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); ++ ++ ++ /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */ ++ __raw_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2); ++ //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode ++ ++ /* Back to back inter-packet-gap */ ++ __raw_writel(0x15, &lp->eth_regs->ethipgt); ++ /* Non - Back to back inter-packet-gap */ ++ __raw_writel(0x12, &lp->eth_regs->ethipgr); ++ ++ /* Management Clock Prescaler Divisor */ ++ /* Clock independent setting */ ++ __raw_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1, ++ &lp->eth_regs->ethmcp); ++ ++ /* don't transmit until fifo contains 48b */ ++ __raw_writel(48, &lp->eth_regs->ethfifott); ++ ++ __raw_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1); ++ ++#ifndef CONFIG_IDT_USE_NAPI ++ tasklet_enable(lp->rx_tasklet); ++#endif ++ tasklet_enable(lp->tx_tasklet); ++ ++ netif_start_queue(dev); ++ ++ return 0; ++} ++ ++static struct platform_driver korina_driver = { ++ .driver.name = "korina", ++ .probe = rc32434_probe, ++ .remove = rc32434_remove, ++}; ++ ++static int __init rc32434_init_module(void) ++{ ++ return platform_driver_register(&korina_driver); ++} ++ ++static void rc32434_cleanup_module(void) ++{ ++ return platform_driver_unregister(&korina_driver); ++} ++ ++module_init(rc32434_init_module); ++module_exit(rc32434_cleanup_module); +diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile +--- linux.old/drivers/net/Makefile 2006-06-08 20:21:20.000000000 +0200 ++++ linux.dev/drivers/net/Makefile 2006-06-08 20:19:40.000000000 +0200 +@@ -23,6 +23,8 @@ + # + obj-$(CONFIG_PLIP) += plip.o + ++obj-$(CONFIG_KORINA) += korina.o ++ + obj-$(CONFIG_ROADRUNNER) += rrunner.o + + obj-$(CONFIG_HAPPYMEAL) += sunhme.o +diff -urN linux.old/drivers/net/rc32434_eth.h linux.dev/drivers/net/rc32434_eth.h +--- linux.old/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/drivers/net/rc32434_eth.h 2006-06-08 21:57:12.000000000 +0200 +@@ -0,0 +1,178 @@ ++/************************************************************************** ++ * ++ * BRIEF MODULE DESCRIPTION ++ * Definitions for IDT RC32434 on-chip ethernet controller. ++ * ++ * Copyright 2004 IDT Inc. (rischelp@idt.com) ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License as published by the ++ * Free Software Foundation; either version 2 of the License, or (at your ++ * option) any later version. ++ * ++ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED ++ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN ++ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, ++ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT ++ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF ++ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ++ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF ++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 675 Mass Ave, Cambridge, MA 02139, USA. ++ * ++ * ++ ************************************************************************** ++ * May 2004 rkt, neb ++ * ++ * Initial Release ++ * ++ * Aug 2004 ++ * ++ * Added NAPI ++ * ++ ************************************************************************** ++ */ ++ ++ ++#include <asm/rc32434/rc32434.h> ++#include <asm/rc32434/dma_v.h> ++#include <asm/rc32434/eth_v.h> ++ ++#define CONFIG_IDT_USE_NAPI 1 ++#define RC32434_DEBUG 2 ++//#define RC32434_PROC_DEBUG ++#undef RC32434_DEBUG ++ ++#ifdef RC32434_DEBUG ++ ++/* use 0 for production, 1 for verification, >2 for debug */ ++static int rc32434_debug = RC32434_DEBUG; ++#define ASSERT(expr) \ ++ if(!(expr)) { \ ++ printk( "Assertion failed! %s,%s,%s,line=%d\n", \ ++ #expr,__FILE__,__FUNCTION__,__LINE__); } ++#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg) ++#else ++#define ASSERT(expr) do {} while (0) ++#define DBG(lvl, format, arg...) do {} while (0) ++#endif ++ ++#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg) ++#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg) ++#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg) ++ ++/* the following must be powers of two */ ++#ifdef CONFIG_IDT_USE_NAPI ++#define RC32434_NUM_RDS 64 /* number of receive descriptors */ ++#define RC32434_NUM_TDS 64 /* number of transmit descriptors */ ++#else ++#define RC32434_NUM_RDS 128 /* number of receive descriptors */ ++#define RC32434_NUM_TDS 128 /* number of transmit descriptors */ ++#endif ++ ++#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */ ++#define RC32434_RDS_MASK (RC32434_NUM_RDS-1) ++#define RC32434_TDS_MASK (RC32434_NUM_TDS-1) ++#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s)) ++#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s)) ++ ++#define RC32434_TX_TIMEOUT HZ * 100 ++ ++#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress)) ++#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress)) ++ ++enum status { filled, empty}; ++#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0) ++#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0) ++ ++ ++/* Information that need to be kept for each board. */ ++struct rc32434_local { ++ ETH_t eth_regs; ++ DMA_Chan_t rx_dma_regs; ++ DMA_Chan_t tx_dma_regs; ++ volatile DMAD_t td_ring; /* transmit descriptor ring */ ++ volatile DMAD_t rd_ring; /* receive descriptor ring */ ++ ++ struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */ ++ struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */ ++ ++#ifndef CONFIG_IDT_USE_NAPI ++ struct tasklet_struct * rx_tasklet; ++#endif ++ struct tasklet_struct * tx_tasklet; ++ ++ int rx_next_done; ++ int rx_chain_head; ++ int rx_chain_tail; ++ enum status rx_chain_status; ++ ++ int tx_next_done; ++ int tx_chain_head; ++ int tx_chain_tail; ++ enum status tx_chain_status; ++ int tx_count; ++ int tx_full; ++ ++ struct timer_list mii_phy_timer; ++ unsigned long duplex_mode; ++ ++ int rx_irq; ++ int tx_irq; ++ int ovr_irq; ++ int und_irq; ++ ++ struct net_device_stats stats; ++ spinlock_t lock; ++ ++ /* debug /proc entry */ ++ struct proc_dir_entry *ps; ++ int dma_halt_cnt; int dma_run_cnt; ++}; ++ ++extern unsigned int idt_cpu_freq; ++ ++/* Index to functions, as function prototypes. */ ++static int rc32434_open(struct net_device *dev); ++static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev); ++static void rc32434_mii_handler(unsigned long data); ++static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs); ++static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs); ++static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs); ++#ifdef RC32434_REVISION ++static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs); ++#endif ++static int rc32434_close(struct net_device *dev); ++static struct net_device_stats *rc32434_get_stats(struct net_device *dev); ++static void rc32434_multicast_list(struct net_device *dev); ++static int rc32434_init(struct net_device *dev); ++static void rc32434_tx_timeout(struct net_device *dev); ++ ++static void rc32434_tx_tasklet(unsigned long tx_data_dev); ++#ifdef CONFIG_IDT_USE_NAPI ++static int rc32434_poll(struct net_device *rx_data_dev, int *budget); ++#else ++static void rc32434_rx_tasklet(unsigned long rx_data_dev); ++#endif ++static void rc32434_cleanup_module(void); ++ ++ ++static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch) ++{ ++ if (__raw_readl(&ch->dmac) & DMAC_run_m) { ++ __raw_writel(0x10, &ch->dmac); ++ ++ while (!(__raw_readl(&ch->dmas) & DMAS_h_m)) ++ dev->trans_start = jiffies; ++ ++ __raw_writel(0, &ch->dmas); ++ } ++ ++ __raw_writel(0, &ch->dmadptr); ++ __raw_writel(0, &ch->dmandptr); ++} + diff --git a/target/linux/rb532-2.6/patches/120-cf.patch b/target/linux/rb532-2.6/patches/120-cf.patch new file mode 100644 index 0000000000..657d8157d0 --- /dev/null +++ b/target/linux/rb532-2.6/patches/120-cf.patch @@ -0,0 +1,990 @@ +diff -urN linux.old/drivers/block/Kconfig linux.dev/drivers/block/Kconfig +--- linux.old/drivers/block/Kconfig 2006-06-08 20:20:52.000000000 +0200 ++++ linux.dev/drivers/block/Kconfig 2006-06-08 22:14:58.000000000 +0200 +@@ -453,4 +453,12 @@ + This driver provides Support for ATA over Ethernet block + devices like the Coraid EtherDrive (R) Storage Blade. + ++config BLK_DEV_CF_MIPS ++ bool "CF slot of RB532 board" ++ depends on MIKROTIK_RB500 ++ default y ++ help ++ The Routerboard 532 has a CF slot on it. Enable the special block ++ device driver for it. ++ + endmenu +diff -urN linux.old/drivers/block/rb500/ata.c linux.dev/drivers/block/rb500/ata.c +--- linux.old/drivers/block/rb500/ata.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/drivers/block/rb500/ata.c 2006-06-09 01:58:40.000000000 +0200 +@@ -0,0 +1,474 @@ ++#include <linux/kernel.h> /* printk() */ ++#include <linux/module.h> /* module to be loadable */ ++#include <linux/delay.h> ++#include <linux/sched.h> ++#include <linux/pci.h> ++#include <linux/ioport.h> /* request_mem_region() */ ++#include <asm/unaligned.h> /* ioremap() */ ++#include <asm/io.h> /* ioremap() */ ++#include <asm/rc32434/rb.h> ++ ++#include "ata.h" ++ ++#define REQUEST_MEM_REGION 0 ++#define DEBUG 1 ++ ++#if DEBUG ++#define DEBUGP printk ++#else ++#define DEBUGP(format, args...) ++#endif ++ ++#define SECS 1000000 /* unit for wait_not_busy() is 1us */ ++ ++unsigned cf_head = 0; ++unsigned cf_cyl = 0; ++unsigned cf_spt = 0; ++unsigned cf_sectors = 0; ++static unsigned cf_block_size = 1; ++static void *baddr = 0; ++ ++#define DBUF32 ((volatile u32 *)((unsigned long)dev->baddr | ATA_DBUF_OFFSET)) ++ ++ ++static void cf_do_tasklet(unsigned long dev_l); ++ ++ ++static inline void wareg(u8 val, unsigned reg, struct cf_mips_dev* dev) ++{ ++ writeb(val, dev->baddr + ATA_REG_OFFSET + reg); ++} ++ ++static inline u8 rareg(unsigned reg, struct cf_mips_dev* dev) ++{ ++ return readb(dev->baddr + ATA_REG_OFFSET + reg); ++} ++ ++static inline int get_gpio_bit(gpio_func ofs, struct cf_mips_dev *dev) ++{ ++ return (gpio_get(ofs) >> dev->pin) & 1; ++} ++ ++static inline void set_gpio_bit(int bit, gpio_func ofs, struct cf_mips_dev *dev) ++{ ++ gpio_set(ofs, (1 << dev->pin), ((bit & 1) << dev->pin)); ++} ++ ++static inline int cfrdy(struct cf_mips_dev *dev) ++{ ++ return get_gpio_bit(DATA, dev); ++} ++ ++static inline void prepare_cf_irq(struct cf_mips_dev *dev) ++{ ++ set_gpio_bit(1, ILEVEL, dev); /* interrupt on cf ready (not busy) */ ++ set_gpio_bit(0, ISTAT, dev); /* clear interrupt status */ ++} ++ ++static inline int cf_present(struct cf_mips_dev* dev) ++{ ++ /* TODO: read and configure CIS into memory mapped mode ++ * TODO: parse CISTPL_CONFIG on CF+ cards to get base address (0x200) ++ * TODO: maybe adjust power saving setting for Hitachi Microdrive ++ */ ++ int i; ++ ++ /* setup CFRDY GPIO as input */ ++ set_gpio_bit(0, FUNC, dev); ++ set_gpio_bit(0, CFG, dev); ++ ++ for (i = 0; i < 0x10; ++i) { ++ if (rareg(i,dev) != 0xff) ++ return 1; ++ } ++ return 0; ++} ++ ++static inline int is_busy(struct cf_mips_dev *dev) ++{ ++ return !cfrdy(dev); ++} ++ ++static int wait_not_busy(int to_us, int wait_for_busy,struct cf_mips_dev *dev) ++{ ++ int us_passed = 0; ++ if (wait_for_busy && !is_busy(dev)) { ++ /* busy must appear within 400ns, ++ * but it may dissapear before we see it ++ * => must not wait for busy in a loop ++ */ ++ ndelay(400); ++ } ++ ++ do { ++ if (us_passed) ++ udelay(1); /* never reached in async mode */ ++ if (!is_busy(dev)) { ++ if (us_passed > 1 * SECS) { ++ printk(KERN_WARNING "cf-mips: not busy ok (after %dus)" ++ ", status 0x%02x\n", us_passed, (unsigned) rareg(ATA_REG_ST,dev)); ++ } ++ return CF_TRANS_OK; ++ } ++ if (us_passed == 1 * SECS) { ++ printk(KERN_WARNING "cf-mips: wait not busy %dus..\n", to_us); ++ } ++ if (dev->async_mode) { ++ dev->to_timer.expires = jiffies + (to_us * HZ / SECS); ++ dev->irq_enable_time = jiffies; ++ prepare_cf_irq(dev); ++ if (is_busy(dev)) { ++ add_timer(&dev->to_timer); ++ enable_irq(dev->irq); ++ return CF_TRANS_IN_PROGRESS; ++ } ++ continue; ++ } ++ ++us_passed; ++ } while (us_passed < to_us); ++ ++ printk(KERN_ERR "cf-mips: wait not busy timeout (%dus)" ++ ", status 0x%02x, state %d\n", ++ to_us, (unsigned) rareg(ATA_REG_ST,dev), dev->tstate); ++ return CF_TRANS_FAILED; ++} ++ ++static irqreturn_t cf_irq_handler(int irq, void *dev_id, struct pt_regs *regs) ++{ ++ /* While tasklet has not disabled irq, irq will be retried all the time ++ * because of ILEVEL matching GPIO pin status => deadlock. ++ * To avoid this, we change ILEVEL to 0. ++ */ ++ struct cf_mips_dev *dev=dev_id; ++ ++ set_gpio_bit(0, ILEVEL, dev); ++ set_gpio_bit(0, ISTAT, dev); ++ ++ del_timer(&dev->to_timer); ++ tasklet_schedule(&dev->tasklet); ++ return IRQ_HANDLED; ++} ++ ++static int do_reset(struct cf_mips_dev *dev) ++{ ++ printk(KERN_INFO "cf-mips: resetting..\n"); ++ ++ wareg(ATA_REG_DC_SRST, ATA_REG_DC,dev); ++ udelay(1); /* FIXME: how long should we wait here? */ ++ wareg(0, ATA_REG_DC,dev); ++ ++ return wait_not_busy(30 * SECS, 1,dev); ++} ++ ++static int set_multiple(struct cf_mips_dev *dev) ++{ ++ if (dev->block_size <= 1) ++ return CF_TRANS_OK; ++ ++ wareg(dev->block_size, ATA_REG_SC,dev); ++ wareg(ATA_REG_DH_BASE | ATA_REG_DH_LBA, ATA_REG_DH,dev); ++ wareg(ATA_CMD_SET_MULTIPLE, ATA_REG_CMD,dev); ++ ++ return wait_not_busy(10 * SECS, 1,dev); ++} ++ ++static int set_cmd(struct cf_mips_dev *dev) ++{ ++ //DEBUGP(KERN_INFO "cf-mips: ata cmd 0x%02x\n", dev->tcmd); ++ // sector_count should be <=24 bits.. ++ BUG_ON(dev->tsect_start>=0x10000000); ++ // This way, it addresses 2^24 * 512 = 128G ++ ++ if (dev->tsector_count) { ++ wareg(dev->tsector_count & 0xff, ATA_REG_SC,dev); ++ wareg(dev->tsect_start & 0xff, ATA_REG_SN,dev); ++ wareg((dev->tsect_start >> 8) & 0xff, ATA_REG_CL,dev); ++ wareg((dev->tsect_start >> 16) & 0xff, ATA_REG_CH,dev); ++ } ++ wareg(((dev->tsect_start >> 24) & 0x0f) | ATA_REG_DH_BASE | ATA_REG_DH_LBA, ++ ATA_REG_DH,dev); /* select drive on all commands */ ++ wareg(dev->tcmd, ATA_REG_CMD,dev); ++ return wait_not_busy(10 * SECS, 1,dev); ++} ++ ++static int do_trans(struct cf_mips_dev *dev) ++{ ++ int res; ++ unsigned st; ++ int transfered; ++ ++ //printk("do_trans: %d sectors left\n",dev->tsectors_left); ++ while (dev->tsectors_left) { ++ transfered = 0; ++ ++ st = rareg(ATA_REG_ST,dev); ++ if (!(st & ATA_REG_ST_DRQ)) { ++ printk(KERN_ERR "cf-mips: do_trans without DRQ (status 0x%x)!\n", st); ++ if (st & ATA_REG_ST_ERR) { ++ int errId = rareg(ATA_REG_ERR,dev); ++ printk(KERN_ERR "cf-mips: %s error, status 0x%x, errid 0x%x\n", ++ (dev->tread ? "read" : "write"), st, errId); ++ } ++ return CF_TRANS_FAILED; ++ } ++ do { /* Fill/read the buffer one block */ ++ u32 *qbuf, *qend; ++ qbuf = (u32 *)dev->tbuf; ++ qend = qbuf + CF_SECT_SIZE / sizeof(u32); ++ if (dev->tread) { ++ while (qbuf!=qend) ++ put_unaligned(*DBUF32,qbuf++); ++ //*(qbuf++) = *DBUF32; ++ } ++ else { ++ while(qbuf!=qend) ++ *DBUF32 = get_unaligned(qbuf++); ++ } ++ ++ dev->tsectors_left--; ++ dev->tbuf += CF_SECT_SIZE; ++ dev->tbuf_size -= CF_SECT_SIZE; ++ transfered++; ++ } while (transfered != dev->block_size && dev->tsectors_left > 0); ++ ++ res = wait_not_busy(10 * SECS, 1,dev); ++ if (res != CF_TRANS_OK) ++ return res; ++ }; ++ ++ st = rareg(ATA_REG_ST,dev); ++ if (st & (ATA_REG_ST_DRQ | ATA_REG_ST_DWF | ATA_REG_ST_ERR)) { ++ if (st & ATA_REG_ST_DRQ) { ++ printk(KERN_ERR "cf-mips: DRQ after all %d sectors are %s" ++ ", status 0x%x\n", dev->tsector_count, (dev->tread ? "read" : "written"), st); ++ } else if (st & ATA_REG_ST_DWF) { ++ printk(KERN_ERR "cf-mips: write fault, status 0x%x\n", st); ++ } else { ++ int errId = rareg(ATA_REG_ERR,dev); ++ printk(KERN_ERR "cf-mips: %s error, status 0x%x, errid 0x%x\n", ++ (dev->tread ? "read" : "write"), st, errId); ++ } ++ return CF_TRANS_FAILED; ++ } ++ return CF_TRANS_OK; ++} ++ ++static int cf_do_state(struct cf_mips_dev *dev) ++{ ++ int res; ++ switch (dev->tstate) { /* fall through everywhere */ ++ case TS_IDLE: ++ dev->tstate = TS_READY; ++ if (is_busy(dev)) { ++ dev->tstate = TS_AFTER_RESET; ++ res = do_reset(dev); ++ if (res != CF_TRANS_OK) ++ break; ++ } ++ case TS_AFTER_RESET: ++ if (dev->tstate == TS_AFTER_RESET) { ++ dev->tstate = TS_READY; ++ res = set_multiple(dev); ++ if (res != CF_TRANS_OK) ++ break; ++ } ++ case TS_READY: ++ dev->tstate = TS_CMD; ++ res = set_cmd(dev); ++ if (res != CF_TRANS_OK) ++ break;; ++ case TS_CMD: ++ dev->tstate = TS_TRANS; ++ case TS_TRANS: ++ res = do_trans(dev); ++ break; ++ default: ++ printk(KERN_ERR "cf-mips: BUG: unknown tstate %d\n", dev->tstate); ++ return CF_TRANS_FAILED; ++ } ++ if (res != CF_TRANS_IN_PROGRESS) ++ dev->tstate = TS_IDLE; ++ return res; ++} ++ ++static void cf_do_tasklet(unsigned long dev_l) ++{ ++ struct cf_mips_dev* dev=(struct cf_mips_dev*) dev_l; ++ int res; ++ ++ disable_irq(dev->irq); ++ ++ if (dev->tstate == TS_IDLE) ++ return; /* can happen when irq is first registered */ ++ ++#if 0 ++ DEBUGP(KERN_WARNING "cf-mips: not busy ok (tasklet) status 0x%02x\n", ++ (unsigned) rareg(ATA_REG_ST,dev)); ++#endif ++ ++ res = cf_do_state(dev); ++ if (res == CF_TRANS_IN_PROGRESS) ++ return; ++ cf_async_trans_done(dev,res); ++} ++ ++static void cf_async_timeout(unsigned long dev_l) ++{ ++ struct cf_mips_dev* dev=(struct cf_mips_dev*) dev_l; ++ disable_irq(dev->irq); ++ /* Perhaps send abort to the device? */ ++ printk(KERN_ERR "cf-mips: wait not busy timeout (%lus)" ++ ", status 0x%02x, state %d\n", ++ jiffies - dev->irq_enable_time, (unsigned) rareg(ATA_REG_ST,dev), dev->tstate); ++ dev->tstate = TS_IDLE; ++ cf_async_trans_done(dev,CF_TRANS_FAILED); ++} ++ ++int cf_do_transfer(struct cf_mips_dev* dev,sector_t sector, unsigned long nsect, ++ char* buffer, int is_write) ++{ ++ BUG_ON(dev->tstate!=TS_IDLE); ++ if (nsect > ATA_MAX_SECT_PER_CMD) { ++ printk(KERN_WARNING "cf-mips: sector count %lu out of range\n",nsect); ++ return CF_TRANS_FAILED; ++ } ++ if (sector + nsect > dev->sectors) { ++ printk(KERN_WARNING "cf-mips: sector %lu out of range\n",sector); ++ return CF_TRANS_FAILED; ++ } ++ dev->tbuf = buffer; ++ dev->tbuf_size = nsect*512; ++ dev->tsect_start = sector; ++ dev->tsector_count = nsect; ++ dev->tsectors_left = dev->tsector_count; ++ dev->tread = (is_write)?0:1; ++ ++ dev->tcmd = (dev->block_size == 1 ? ++ (is_write ? ATA_CMD_WRITE_SECTORS : ATA_CMD_READ_SECTORS) : ++ (is_write ? ATA_CMD_WRITE_MULTIPLE : ATA_CMD_READ_MULTIPLE)); ++ ++ return cf_do_state(dev); ++} ++ ++static int do_identify(struct cf_mips_dev *dev) ++{ ++ u16 sbuf[CF_SECT_SIZE >> 1]; ++ int res; ++ char tstr[17]; //serial ++ BUG_ON(dev->tstate!=TS_IDLE); ++ dev->tbuf = (char *) sbuf; ++ dev->tbuf_size = CF_SECT_SIZE; ++ dev->tsect_start = 0; ++ dev->tsector_count = 0; ++ dev->tsectors_left = 1; ++ dev->tread = 1; ++ dev->tcmd = ATA_CMD_IDENTIFY_DRIVE; ++ ++ DEBUGP(KERN_INFO "cf-mips: identify drive..\n"); ++ res = cf_do_state(dev); ++ if (res == CF_TRANS_IN_PROGRESS) { ++ printk(KERN_ERR "cf-mips: BUG: async identify cmd\n"); ++ return CF_TRANS_FAILED; ++ } ++ if (res != CF_TRANS_OK) ++ return 0; ++ ++ dev->head = sbuf[3]; ++ dev->cyl = sbuf[1]; ++ dev->spt = sbuf[6]; ++ dev->sectors = ((unsigned long) sbuf[7] << 16) | sbuf[8]; ++ dev->dtype=sbuf[0]; ++ memcpy(tstr,&sbuf[12],16); ++ tstr[16]=0; ++ printk(KERN_INFO "cf-mips: %s detected, C/H/S=%d/%d/%d sectors=%u (%uMB) Serial=%s\n", ++ (sbuf[0] == 0x848A ? "CF card" : "ATA drive"), dev->cyl, dev->head, ++ dev->spt, dev->sectors, dev->sectors >> 11,tstr); ++ return 1; ++} ++ ++static void init_multiple(struct cf_mips_dev * dev) ++{ ++ int res; ++ DEBUGP(KERN_INFO "cf-mips: detecting block size\n"); ++ ++ dev->block_size = 128; /* max block size = 128 sectors (64KB) */ ++ do { ++ wareg(dev->block_size, ATA_REG_SC,dev); ++ wareg(ATA_REG_DH_BASE | ATA_REG_DH_LBA, ATA_REG_DH,dev); ++ wareg(ATA_CMD_SET_MULTIPLE, ATA_REG_CMD,dev); ++ ++ res = wait_not_busy(10 * SECS, 1,dev); ++ if (res != CF_TRANS_OK) { ++ printk(KERN_ERR "cf-mips: failed to detect block size: busy!\n"); ++ dev->block_size = 1; ++ return; ++ } ++ if ((rareg(ATA_REG_ST,dev) & ATA_REG_ST_ERR) == 0) ++ break; ++ dev->block_size /= 2; ++ } while (dev->block_size > 1); ++ ++ printk(KERN_INFO "cf-mips: multiple sectors = %d\n", dev->block_size); ++} ++ ++int cf_init(struct cf_mips_dev *dev) ++{ ++ tasklet_init(&dev->tasklet,cf_do_tasklet,(unsigned long)dev); ++ dev->baddr = ioremap_nocache((unsigned long)dev->base, CFDEV_BUF_SIZE); ++ if (!dev->baddr) { ++ printk(KERN_ERR "cf-mips: cf_init: ioremap for (%lx,%x) failed\n", ++ (unsigned long) dev->base, CFDEV_BUF_SIZE); ++ return -EBUSY; ++ } ++ ++ if (!cf_present(dev)) { ++ printk(KERN_WARNING "cf-mips: cf card not present\n"); ++ iounmap(dev->baddr); ++ return -ENODEV; ++ } ++ ++ if (do_reset(dev) != CF_TRANS_OK) { ++ printk(KERN_ERR "cf-mips: cf reset failed\n"); ++ iounmap(dev->baddr); ++ return -EBUSY; ++ } ++ ++ if (!do_identify(dev)) { ++ printk(KERN_ERR "cf-mips: cf identify failed\n"); ++ iounmap(dev->baddr); ++ return -EBUSY; ++ } ++ ++/* set_apm_level(ATA_APM_WITH_STANDBY); */ ++ init_multiple(dev); ++ ++ init_timer(&dev->to_timer); ++ dev->to_timer.function = cf_async_timeout; ++ dev->to_timer.data = (unsigned long)dev; ++ ++ prepare_cf_irq(dev); ++ if (request_irq(dev->irq, cf_irq_handler, 0, "CF Mips", dev)) { ++ printk(KERN_ERR "cf-mips: failed to get irq\n"); ++ iounmap(dev->baddr); ++ return -EBUSY; ++ } ++ /* Disable below would be odd, because request will enable, and the tasklet ++ will disable it itself */ ++ //disable_irq(dev->irq); ++ ++ dev->async_mode = 1; ++ ++ return 0; ++} ++ ++void cf_cleanup(struct cf_mips_dev *dev) ++{ ++ iounmap(dev->baddr); ++ free_irq(dev->irq, NULL); ++#if REQUEST_MEM_REGION ++ release_mem_region((unsigned long)dev->base, CFDEV_BUF_SIZE); ++#endif ++} ++ ++ ++/*eof*/ +diff -urN linux.old/drivers/block/rb500/ata.h linux.dev/drivers/block/rb500/ata.h +--- linux.old/drivers/block/rb500/ata.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/drivers/block/rb500/ata.h 2006-06-09 00:15:23.000000000 +0200 +@@ -0,0 +1,132 @@ ++#ifndef __CFMIPS_ATA_H__ ++#define __CFMIPS_ATA_H__ ++ ++#include <linux/interrupt.h> ++ ++#define CFG_DC_DEV1 (void*)0xb8010010 ++#define CFG_DC_DEVBASE 0x0 ++#define CFG_DC_DEVMASK 0x4 ++#define CFG_DC_DEVC 0x8 ++#define CFG_DC_DEVTC 0xC ++ ++#define CFDEV_BUF_SIZE 0x1000 ++#define ATA_CIS_OFFSET 0x200 ++#define ATA_REG_OFFSET 0x800 ++#define ATA_DBUF_OFFSET 0xC00 ++ ++#define ATA_REG_FEAT 0x1 ++#define ATA_REG_SC 0x2 ++#define ATA_REG_SN 0x3 ++#define ATA_REG_CL 0x4 ++#define ATA_REG_CH 0x5 ++#define ATA_REG_DH 0x6 ++#define ATA_REG_DH_BASE 0xa0 ++#define ATA_REG_DH_LBA 0x40 ++#define ATA_REG_DH_DRV 0x10 ++#define ATA_REG_CMD 0x7 ++#define ATA_REG_ST 0x7 ++#define ATA_REG_ST_BUSY 0x80 ++#define ATA_REG_ST_RDY 0x40 ++#define ATA_REG_ST_DWF 0x20 ++#define ATA_REG_ST_DSC 0x10 ++#define ATA_REG_ST_DRQ 0x08 ++#define ATA_REG_ST_CORR 0x04 ++#define ATA_REG_ST_ERR 0x01 ++#define ATA_REG_ERR 0xd ++#define ATA_REG_DC 0xe ++#define ATA_REG_DC_IEN 0x02 ++#define ATA_REG_DC_SRST 0x04 ++ ++#define ATA_CMD_READ_SECTORS 0x20 ++#define ATA_CMD_WRITE_SECTORS 0x30 ++#define ATA_CMD_EXEC_DRIVE_DIAG 0x90 ++#define ATA_CMD_READ_MULTIPLE 0xC4 ++#define ATA_CMD_WRITE_MULTIPLE 0xC5 ++#define ATA_CMD_SET_MULTIPLE 0xC6 ++#define ATA_CMD_IDENTIFY_DRIVE 0xEC ++#define ATA_CMD_SET_FEATURES 0xEF ++ ++#define ATA_FEATURE_ENABLE_APM 0x05 ++#define ATA_FEATURE_DISABLE_APM 0x85 ++#define ATA_APM_DISABLED 0x00 ++#define ATA_APM_MIN_POWER 0x01 ++#define ATA_APM_WITH_STANDBY 0x7f ++#define ATA_APM_WITHOUT_STANDBY 0x80 ++#define ATA_APM_MAX_PERFORMANCE 0xfe ++ ++#define CF_SECT_SIZE 0x200 ++/* That is the ratio CF_SECT_SIZE/512 (the kernel sector size) */ ++#define CF_KERNEL_MUL 1 ++#define ATA_MAX_SECT_PER_CMD 0x100 ++ ++#define CF_TRANS_FAILED 0 ++#define CF_TRANS_OK 1 ++#define CF_TRANS_IN_PROGRESS 2 ++ ++ ++enum trans_state { ++ TS_IDLE = 0, ++ TS_AFTER_RESET, ++ TS_READY, ++ TS_CMD, ++ TS_TRANS ++}; ++ ++// ++// #if DEBUG ++// static unsigned long busy_time; ++// #endif ++ ++/** Struct to hold the cfdev ++Actually, all the data here only has one instance. However, for ++reasons of programming conformity, it is passed around as a pointer ++*/ ++struct cf_mips_dev { ++ void *base; /* base address for I/O */ ++ void *baddr; /* remapped address */ ++ ++ int pin; /* gpio pin */ ++ int irq; /* gpio irq */ ++ ++ unsigned head; ++ unsigned cyl; ++ unsigned spt; ++ unsigned sectors; ++ ++ unsigned short block_size; ++ unsigned dtype ; // ATA or CF ++ struct request_queue *queue; ++ struct gendisk *gd; ++ ++ /* Transaction state */ ++ enum trans_state tstate; ++ char *tbuf; ++ unsigned long tbuf_size; ++ sector_t tsect_start; ++ unsigned tsector_count; ++ unsigned tsectors_left; ++ int tread; ++ unsigned tcmd; ++ int async_mode; ++ unsigned long irq_enable_time; ++ ++ struct request *active_req; /* A request is being carried out. Is that different from tstate? */ ++ int users; ++ struct timer_list to_timer; ++ struct tasklet_struct tasklet; ++ ++ /** This lock ensures that the requests to this device are all done ++ atomically. Transfers can run in parallel, requests are all queued ++ one-by-one */ ++ spinlock_t lock; ++}; ++ ++int cf_do_transfer(struct cf_mips_dev* dev,sector_t sector, unsigned long nsect, ++ char* buffer, int is_write); ++int cf_init(struct cf_mips_dev* dev); ++void cf_cleanup(struct cf_mips_dev* dev); ++ ++void cf_async_trans_done(struct cf_mips_dev* dev, int result); ++// void *cf_get_next_buf(unsigned long *buf_size); ++ ++#endif +diff -urN linux.old/drivers/block/rb500/bdev.c linux.dev/drivers/block/rb500/bdev.c +--- linux.old/drivers/block/rb500/bdev.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/drivers/block/rb500/bdev.c 2006-06-15 16:29:04.000000000 +0200 +@@ -0,0 +1,340 @@ ++/* CF-mips driver ++ This is a block driver for the direct (mmaped) interface to the CF-slot, ++ found in Routerboard.com's RB532 board ++ See SDK provided from routerboard.com. ++ ++ Module adapted By P.Christeas <p_christeas@yahoo.com>, 2005-6. ++ Cleaned up and adapted to platform_device by Felix Fietkau <nbd@openwrt.org> ++ ++ This work is redistributed under the terms of the GNU General Public License. ++*/ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/time.h> ++#include <linux/wait.h> ++#include <linux/fs.h> ++#include <linux/genhd.h> ++#include <linux/blkdev.h> ++#include <linux/blkpg.h> ++#include <linux/hdreg.h> ++#include <linux/platform_device.h> ++ ++#include <asm/uaccess.h> ++#include <asm/io.h> ++ ++#include <asm/rc32434/rb.h> ++ ++#ifdef DEBUG ++#define DEBUGP printk ++#define DLEVEL 1 ++#else ++#define DEBUGP(format, args...) ++#define DLEVEL 0 ++#endif ++ ++#define CF_MIPS_MAJOR 13 ++#define MAJOR_NR CF_MIPS_MAJOR ++#define CF_MAX_PART 16 /* max 15 partitions */ ++ ++#include "ata.h" ++ ++//extern struct block_device_operations cf_bdops; ++ ++// static struct hd_struct cf_parts[CF_MAX_PART]; ++// static int cf_part_sizes[CF_MAX_PART]; ++// static int cf_hsect_sizes[CF_MAX_PART]; ++// static int cf_max_sectors[CF_MAX_PART]; ++// static int cf_blksize_sizes[CF_MAX_PART]; ++ ++// static spinlock_t lock = SPIN_LOCK_UNLOCKED; ++ ++// volatile int cf_busy = 0; ++ ++static struct request *active_req = NULL; ++ ++static int cf_open (struct inode *, struct file *); ++static int cf_release (struct inode *, struct file *); ++static int cf_ioctl (struct inode *, struct file *, unsigned, unsigned long); ++ ++static void cf_request(request_queue_t * q); ++static int cf_transfer(const struct request *req); ++ ++/*long (*unlocked_ioctl) (struct file *, unsigned, unsigned long); ++long (*compat_ioctl) (struct file *, unsigned, unsigned long);*/ ++// int (*direct_access) (struct block_device *, sector_t, unsigned long *); ++// int (*media_changed) (struct gendisk *); ++// int (*revalidate_disk) (struct gendisk *); ++ ++static struct block_device_operations cf_bdops = { ++ .owner = THIS_MODULE, ++ .open = cf_open, ++ .release = cf_release, ++ .ioctl = cf_ioctl, ++ .media_changed = NULL, ++ .unlocked_ioctl = NULL, ++ .revalidate_disk = NULL, ++ .compat_ioctl = NULL, ++ .direct_access = NULL ++}; ++ ++ ++int cf_mips_probe(struct platform_device *pdev) ++{ ++ struct gendisk* cf_gendisk=NULL; ++ struct cf_device *cdev = (struct cf_device *) pdev->dev.platform_data; ++ struct cf_mips_dev *dev; ++ struct resource *r; ++ int reg_result; ++ ++ reg_result = register_blkdev(MAJOR_NR, "cf-mips"); ++ if (reg_result < 0) { ++ printk(KERN_WARNING "cf-mips: can't get major %d\n", MAJOR_NR); ++ return reg_result; ++ } ++ ++ dev = (struct cf_mips_dev *)kmalloc(sizeof(struct cf_mips_dev),GFP_KERNEL); ++ if (!dev) ++ goto out_err; ++ memset(dev, 0, sizeof(struct cf_mips_dev)); ++ cdev->dev = dev; ++ ++ dev->pin = cdev->gpio_pin; ++ dev->irq = platform_get_irq_byname(pdev, "cf_irq"); ++ r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cf_membase"); ++ dev->base = (void *) r->start; ++ ++ if (cf_init(dev)) goto out_err; ++ printk("init done"); ++ ++ spin_lock_init(&dev->lock); ++ dev->queue = blk_init_queue(cf_request,&dev->lock); ++ if (!dev->queue){ ++ printk(KERN_ERR "cf-mips: no mem for queue\n"); ++ goto out_err; ++ } ++ blk_queue_max_sectors(dev->queue,ATA_MAX_SECT_PER_CMD); ++ ++ /* For memory devices, it is always better to avoid crossing segments ++ inside the same request. */ ++/* if (dev->dtype==0x848A){ ++ printk(KERN_INFO "Setting boundary for cf to 0x%x",(dev->block_size*512)-1); ++ blk_queue_segment_boundary(dev->queue, (dev->block_size*512)-1); ++ }*/ ++ ++ dev->gd = alloc_disk(CF_MAX_PART); ++ cf_gendisk = dev->gd; ++ cdev->gd = dev->gd; ++ if (!cf_gendisk) goto out_err; /* Last of these goto's */ ++ ++ cf_gendisk->major = MAJOR_NR; ++ cf_gendisk->first_minor = 0; ++ cf_gendisk->queue=dev->queue; ++ BUG_ON(cf_gendisk->minors != CF_MAX_PART); ++ strcpy(cf_gendisk->disk_name,"cfa"); ++ strcpy(cf_gendisk->devfs_name,"cf/card0"); ++ cf_gendisk->fops = &cf_bdops; ++ cf_gendisk->flags = 0 ; /* is not yet GENHD_FL_REMOVABLE */ ++ cf_gendisk->private_data=dev; ++ ++ set_capacity(cf_gendisk,dev->sectors * CF_KERNEL_MUL); ++ ++ /* Let the disk go live */ ++ add_disk(cf_gendisk); ++#if 0 ++ result = cf_init(); ++ ++ /* default cfg for all partitions */ ++ memset(cf_parts, 0, sizeof (cf_parts[0]) * CF_MAX_PART); ++ memset(cf_part_sizes, 0, sizeof (cf_part_sizes[0]) * CF_MAX_PART); ++ for (i = 0; i < CF_MAX_PART; ++i) { ++ cf_hsect_sizes[i] = CF_SECT_SIZE; ++ cf_max_sectors[i] = ATA_MAX_SECT_PER_CMD; ++ cf_blksize_sizes[i] = BLOCK_SIZE; ++ } ++ ++ /* setup info for whole disk (partition 0) */ ++ cf_part_sizes[0] = cf_sectors / 2; ++ cf_parts[0].nr_sects = cf_sectors; ++ ++ blk_size[MAJOR_NR] = cf_part_sizes; ++ blksize_size[MAJOR_NR] = cf_blksize_sizes; ++ max_sectors[MAJOR_NR] = cf_max_sectors; ++ hardsect_size[MAJOR_NR] = cf_hsect_sizes; ++ read_ahead[MAJOR_NR] = 8; /* (4kB) */ ++ ++ blk_init_queue(BLK_DEFAULT_QUEUE(MAJOR_NR), DEVICE_REQUEST); ++ ++ add_gendisk(&cf_gendisk); ++#endif ++// printk(KERN_INFO "cf-mips partition check: \n"); ++// register_disk(cf_gendisk, MKDEV(MAJOR_NR, 0), CF_MAX_PART, ++// &cf_bdops, dev->sectors); ++ return 0; ++ ++out_err: ++ if (dev->queue){ ++ blk_cleanup_queue(dev->queue); ++ } ++ if (reg_result) { ++ unregister_blkdev(MAJOR_NR, "cf-mips"); ++ return reg_result; ++ } ++ if (dev){ ++ cf_cleanup(dev); ++ kfree(dev); ++ } ++ return 1; ++} ++ ++static int ++cf_mips_remove(struct platform_device *pdev) ++{ ++ struct cf_device *cdev = (struct cf_device *) pdev->dev.platform_data; ++ struct cf_mips_dev *dev = (struct cf_mips_dev *) cdev->dev; ++ ++ unregister_blkdev(MAJOR_NR, "cf-mips"); ++ blk_cleanup_queue(dev->queue); ++ ++ del_gendisk(dev->gd); ++ cf_cleanup(dev); ++ return 0; ++} ++ ++ ++static struct platform_driver cf_driver = { ++ .driver.name = "rb500-cf", ++ .probe = cf_mips_probe, ++ .remove = cf_mips_remove, ++}; ++ ++static int __init cf_mips_init(void) ++{ ++ printk(KERN_INFO "cf-mips module loaded\n"); ++ return platform_driver_register(&cf_driver); ++} ++ ++static void cf_mips_cleanup(void) ++{ ++ platform_driver_unregister(&cf_driver); ++ printk(KERN_INFO "cf-mips module removed\n"); ++} ++ ++module_init(cf_mips_init); ++module_exit(cf_mips_cleanup); ++ ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS_BLOCKDEV_MAJOR(CF_MIPS_MAJOR); ++ ++ ++static int cf_open(struct inode *inode, struct file *filp) ++{ ++ struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data; ++ int minor = MINOR(inode->i_rdev); ++ ++ if (minor >= CF_MAX_PART) ++ return -ENODEV; ++ //DEBUGP(KERN_INFO "cf-mips module opened, minor %d\n", minor); ++ spin_lock(&dev->lock); ++ dev->users++; ++ spin_unlock(&dev->lock); ++ filp->private_data=dev; ++ ++ /* dirty workaround to set CFRDY GPIO as an input when some other ++ program sets it as an output */ ++ gpio_set(CFG, (1 << dev->pin), 0); ++ return 0; /* success */ ++} ++ ++static int cf_release(struct inode *inode, struct file *filp) ++{ ++ int minor = MINOR(inode->i_rdev); ++ struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data; ++ spin_lock(&dev->lock); ++ dev->users--; ++ spin_unlock(&dev->lock); ++ return 0; ++} ++ ++static int cf_ioctl(struct inode *inode, struct file *filp, ++ unsigned int cmd, unsigned long arg) ++{ ++ unsigned minor = MINOR(inode->i_rdev); ++ struct cf_mips_dev *dev=inode->i_bdev->bd_disk->private_data; ++ ++ DEBUGP(KERN_INFO "cf_ioctl cmd %u\n", cmd); ++ switch (cmd) { ++ case BLKRRPART: /* re-read partition table */ ++ if (!capable(CAP_SYS_ADMIN)) ++ return -EACCES; ++ printk(KERN_INFO "cf-mips partition check: \n"); ++ register_disk(dev->gd); ++ return 0; ++ ++ case HDIO_GETGEO: ++ { ++ struct hd_geometry geo; ++ geo.cylinders = dev->cyl; ++ geo.heads = dev->head; ++ geo.sectors = dev->spt; ++ geo.start = (*dev->gd->part)[minor].start_sect; ++ if (copy_to_user((void *) arg, &geo, sizeof (geo))) ++ return -EFAULT; ++ } ++ return 0; ++ } ++ ++ return -EINVAL; /* unknown command */ ++} ++ ++static void cf_request(request_queue_t * q) ++{ ++ struct cf_mips_dev* dev; ++ ++ struct request * req; ++ int status; ++ ++ /* We could have q->queuedata = dev , but haven't yet. */ ++ if (active_req) ++ return; ++ ++ while ((req=elv_next_request(q))!=NULL){ ++ dev=req->rq_disk->private_data; ++ status=cf_transfer(req); ++ if (status==CF_TRANS_IN_PROGRESS){ ++ active_req=req; ++ return; ++ } ++ end_request(req,status); ++ } ++} ++ ++static int cf_transfer(const struct request *req) ++{ ++ struct cf_mips_dev* dev=req->rq_disk->private_data; ++ ++ if (!blk_fs_request(req)){ ++ if (printk_ratelimit()) ++ printk(KERN_WARNING "cf-mips: skipping non-fs request 0x%x\n",req->cmd[0]); ++ return CF_TRANS_FAILED; ++ } ++ ++ return cf_do_transfer(dev,req->sector,req->current_nr_sectors,req->buffer,rq_data_dir(req)); ++} ++ ++void cf_async_trans_done(struct cf_mips_dev * dev,int result) ++{ ++ struct request *req; ++ ++ spin_lock(&dev->lock); ++ req=active_req; ++ active_req=NULL; ++ end_request(req,result); ++ spin_unlock(&dev->lock); ++ ++ spin_lock(&dev->lock); ++ cf_request(dev->queue); ++ spin_unlock(&dev->lock); ++} ++ +diff -urN linux.old/drivers/block/rb500/Makefile linux.dev/drivers/block/rb500/Makefile +--- linux.old/drivers/block/rb500/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/drivers/block/rb500/Makefile 2006-06-08 22:14:58.000000000 +0200 +@@ -0,0 +1,3 @@ ++## Makefile for the RB532 CF port ++ ++obj-y += bdev.o ata.o +diff -urN linux.old/drivers/Makefile linux.dev/drivers/Makefile +--- linux.old/drivers/Makefile 2006-06-08 20:20:52.000000000 +0200 ++++ linux.dev/drivers/Makefile 2006-06-08 22:14:58.000000000 +0200 +@@ -73,3 +73,4 @@ + obj-y += firmware/ + obj-$(CONFIG_CRYPTO) += crypto/ + obj-$(CONFIG_SUPERH) += sh/ ++obj-$(CONFIG_BLK_DEV_CF_MIPS) += block/rb500/ +\ No newline at end of file diff --git a/target/linux/rb532-2.6/patches/130-custom_partitions.patch b/target/linux/rb532-2.6/patches/130-custom_partitions.patch new file mode 100644 index 0000000000..e4b332703a --- /dev/null +++ b/target/linux/rb532-2.6/patches/130-custom_partitions.patch @@ -0,0 +1,311 @@ +diff -urN linux.old/fs/partitions/check.c linux.dev/fs/partitions/check.c +--- linux.old/fs/partitions/check.c 2006-05-31 02:31:44.000000000 +0200 ++++ linux.dev/fs/partitions/check.c 2006-06-15 01:27:17.000000000 +0200 +@@ -29,6 +29,7 @@ + #include "ldm.h" + #include "mac.h" + #include "msdos.h" ++#include "openwrt.h" + #include "osf.h" + #include "sgi.h" + #include "sun.h" +@@ -48,6 +49,9 @@ + * Probe partition formats with tables at disk address 0 + * that also have an ADFS boot block at 0xdc0. + */ ++#ifdef CONFIG_OPENWRT_PARTITION ++ openwrt_partition, ++#endif + #ifdef CONFIG_ACORN_PARTITION_ICS + adfspart_check_ICS, + #endif +diff -urN linux.old/fs/partitions/Kconfig linux.dev/fs/partitions/Kconfig +--- linux.old/fs/partitions/Kconfig 2006-05-31 02:31:44.000000000 +0200 ++++ linux.dev/fs/partitions/Kconfig 2006-06-15 01:27:17.000000000 +0200 +@@ -14,6 +14,12 @@ + + If unsure, say N. + ++config OPENWRT_PARTITION ++ bool "OpenWrt partition support" if PARTITION_ADVANCED ++ default y ++ help ++ Support the custom OpenWrt partition map ++ + config ACORN_PARTITION + bool "Acorn partition support" if PARTITION_ADVANCED + default y if ARCH_ACORN +diff -urN linux.old/fs/partitions/Makefile linux.dev/fs/partitions/Makefile +--- linux.old/fs/partitions/Makefile 2006-05-31 02:31:44.000000000 +0200 ++++ linux.dev/fs/partitions/Makefile 2006-06-15 01:27:17.000000000 +0200 +@@ -11,6 +11,7 @@ + obj-$(CONFIG_MAC_PARTITION) += mac.o + obj-$(CONFIG_LDM_PARTITION) += ldm.o + obj-$(CONFIG_MSDOS_PARTITION) += msdos.o ++obj-$(CONFIG_OPENWRT_PARTITION) += openwrt.o + obj-$(CONFIG_OSF_PARTITION) += osf.o + obj-$(CONFIG_SGI_PARTITION) += sgi.o + obj-$(CONFIG_SUN_PARTITION) += sun.o +diff -urN linux.old/fs/partitions/openwrt.c linux.dev/fs/partitions/openwrt.c +--- linux.old/fs/partitions/openwrt.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/fs/partitions/openwrt.c 2006-06-15 01:27:17.000000000 +0200 +@@ -0,0 +1,249 @@ ++/* ++ * fs/partitions/openwrt.c ++ * ++ * Code extracted from drivers/block/genhd.c ++ * and fs/partitions/msdos.c ++ * ++ * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org> ++ * Copyright (C) 1991-1998 Linus Torvalds ++ * ++ * Thanks to Branko Lankester, lankeste@fwi.uva.nl, who found a bug ++ * in the early extended-partition checks and added DM partitions ++ * ++ * Support for DiskManager v6.0x added by Mark Lord, ++ * with information provided by OnTrack. This now works for linux fdisk ++ * and LILO, as well as loadlin and bootln. Note that disks other than ++ * /dev/hda *must* have a "DOS" type 0x51 partition in the first slot (hda1). ++ * ++ * More flexible handling of extended partitions - aeb, 950831 ++ * ++ * Check partition table on IDE disks for common CHS translations ++ * ++ * Re-organised Feb 1998 Russell King ++ */ ++ ++#include <linux/config.h> ++ ++#include "check.h" ++#include "openwrt.h" ++ ++/* ++ * Many architectures don't like unaligned accesses, while ++ * the nr_sects and start_sect partition table entries are ++ * at a 2 (mod 4) address. ++ */ ++#include <asm/unaligned.h> ++ ++#define SYS_IND(p) (get_unaligned(&p->sys_ind)) ++#define NR_SECTS(p) ({ __typeof__(p->nr_sects) __a = \ ++ get_unaligned(&p->nr_sects); \ ++ le32_to_cpu(__a); \ ++ }) ++ ++#define START_SECT(p) ({ __typeof__(p->start_sect) __a = \ ++ get_unaligned(&p->start_sect); \ ++ le32_to_cpu(__a); \ ++ }) ++ ++static inline int is_extended_partition(struct partition *p) ++{ ++ return (SYS_IND(p) == DOS_EXTENDED_PARTITION || ++ SYS_IND(p) == WIN98_EXTENDED_PARTITION || ++ SYS_IND(p) == LINUX_EXTENDED_PARTITION); ++} ++ ++#define MSDOS_LABEL_MAGIC1 0x55 ++#define MSDOS_LABEL_MAGIC2 0xAA ++ ++static inline int ++msdos_magic_present(unsigned char *p) ++{ ++ return (p[0] == MSDOS_LABEL_MAGIC1 && p[1] == MSDOS_LABEL_MAGIC2); ++} ++ ++static inline int ++openwrt_magic_present(unsigned char *p) ++{ ++ return (p[0] == 'O' && ++ p[1] == 'W' && ++ p[2] == 'R' && ++ p[3] == 'T'); ++} ++ ++/* ++ * Create devices for each logical partition in an extended partition. ++ * The logical partitions form a linked list, with each entry being ++ * a partition table with two entries. The first entry ++ * is the real data partition (with a start relative to the partition ++ * table start). The second is a pointer to the next logical partition ++ * (with a start relative to the entire extended partition). ++ * We do not create a Linux partition for the partition tables, but ++ * only for the actual data partitions. ++ */ ++ ++static void ++parse_extended(struct parsed_partitions *state, struct block_device *bdev, ++ u32 first_sector, u32 first_size) ++{ ++ struct partition *p; ++ Sector sect; ++ unsigned char *data; ++ u32 this_sector, this_size; ++ int sector_size = bdev_hardsect_size(bdev) / 512; ++ int loopct = 0; /* number of links followed ++ without finding a data partition */ ++ int i; ++ ++ this_sector = first_sector; ++ this_size = first_size; ++ ++ while (1) { ++ if (++loopct > 100) ++ return; ++ if (state->next == state->limit) ++ return; ++ data = read_dev_sector(bdev, this_sector, §); ++ if (!data) ++ return; ++ ++ if (!msdos_magic_present(data + 510)) ++ goto done; ++ ++ p = (struct partition *) (data + 0x1be); ++ ++ /* ++ * Usually, the first entry is the real data partition, ++ * the 2nd entry is the next extended partition, or empty, ++ * and the 3rd and 4th entries are unused. ++ * However, DRDOS sometimes has the extended partition as ++ * the first entry (when the data partition is empty), ++ * and OS/2 seems to use all four entries. ++ */ ++ ++ /* ++ * First process the data partition(s) ++ */ ++ for (i=0; i<4; i++, p++) { ++ u32 offs, size, next; ++ if (!NR_SECTS(p) || is_extended_partition(p)) ++ continue; ++ ++ /* Check the 3rd and 4th entries - ++ these sometimes contain random garbage */ ++ offs = START_SECT(p)*sector_size; ++ size = NR_SECTS(p)*sector_size; ++ next = this_sector + offs; ++ if (i >= 2) { ++ if (offs + size > this_size) ++ continue; ++ if (next < first_sector) ++ continue; ++ if (next + size > first_sector + first_size) ++ continue; ++ } ++ ++ put_partition(state, state->next, next, size); ++ if (SYS_IND(p) == LINUX_RAID_PARTITION) ++ state->parts[state->next].flags = 1; ++ loopct = 0; ++ if (++state->next == state->limit) ++ goto done; ++ } ++ /* ++ * Next, process the (first) extended partition, if present. ++ * (So far, there seems to be no reason to make ++ * parse_extended() recursive and allow a tree ++ * of extended partitions.) ++ * It should be a link to the next logical partition. ++ */ ++ p -= 4; ++ for (i=0; i<4; i++, p++) ++ if (NR_SECTS(p) && is_extended_partition(p)) ++ break; ++ if (i == 4) ++ goto done; /* nothing left to do */ ++ ++ this_sector = first_sector + START_SECT(p) * sector_size; ++ this_size = NR_SECTS(p) * sector_size; ++ put_dev_sector(sect); ++ } ++done: ++ put_dev_sector(sect); ++} ++ ++ ++int openwrt_partition(struct parsed_partitions *state, struct block_device *bdev) ++{ ++ int sector_size = bdev_hardsect_size(bdev) / 512; ++ Sector sect; ++ unsigned char *data; ++ struct partition *p; ++ int slot; ++ u32 last_block = 0; ++ u32 size = 0; ++ int firstfree = 5; ++ ++ data = read_dev_sector(bdev, 0, §); ++ if (!data) ++ return -1; ++ if (!openwrt_magic_present(data)) { ++ printk("No OpenWrt partition table detected\n"); ++ put_dev_sector(sect); ++ return 0; ++ } ++ ++ /* ++ * Now that the 55aa signature is present, this is probably ++ * either the boot sector of a FAT filesystem or a DOS-type ++ * partition table. Reject this in case the boot indicator ++ * is not 0 or 0x80. ++ */ ++ p = (struct partition *) (data + 0x1be); ++ for (slot = 1; slot <= 4; slot++, p++) { ++ if (p->boot_ind != 0 && p->boot_ind != 0x80) { ++ put_dev_sector(sect); ++ return 0; ++ } ++ } ++ ++ p = (struct partition *) (data + 0x1be); ++ ++ /* ++ * Look for partitions in two passes: ++ * First find the primary and DOS-type extended partitions. ++ */ ++ ++ state->next = 6; ++ for (slot = 1 ; slot <= 4 ; slot++, p++) { ++ u32 start = START_SECT(p)*sector_size; ++ size = NR_SECTS(p)*sector_size; ++ if (!size) { ++ if (firstfree > slot) ++ firstfree = slot; ++ ++ continue; ++ } ++ if (is_extended_partition(p)) { ++ /* prevent someone doing mkfs or mkswap on an ++ extended partition, but leave room for LILO */ ++ last_block = start + size; ++ put_partition(state, slot, start, size == 1 ? 1 : 2); ++ printk(" <"); ++ parse_extended(state, bdev, start, size); ++ printk(" >"); ++ continue; ++ } ++ if ((start + size) > get_capacity(bdev->bd_disk)) ++ size = get_capacity(bdev->bd_disk) - start; ++ last_block = start + size; ++ put_partition(state, slot, start, size); ++ } ++ if (last_block + 1024 < (size = get_capacity(bdev->bd_disk))) ++ put_partition(state, firstfree, last_block, size - last_block); ++ ++ printk("\n"); ++ ++ put_dev_sector(sect); ++ return 1; ++} ++ +diff -urN linux.old/fs/partitions/openwrt.h linux.dev/fs/partitions/openwrt.h +--- linux.old/fs/partitions/openwrt.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/fs/partitions/openwrt.h 2006-06-15 01:27:17.000000000 +0200 +@@ -0,0 +1,6 @@ ++/* ++ * fs/partitions/openwrt.h ++ */ ++ ++int openwrt_partition(struct parsed_partitions *state, struct block_device *bdev); ++ diff --git a/target/linux/rb532-2.6/patches/200-bridge_resource_hack.patch b/target/linux/rb532-2.6/patches/200-bridge_resource_hack.patch new file mode 100644 index 0000000000..3017f5dfcd --- /dev/null +++ b/target/linux/rb532-2.6/patches/200-bridge_resource_hack.patch @@ -0,0 +1,13 @@ +--- linux.old/arch/mips/pci/pci.c 2006-04-19 08:10:14.000000000 +0200 ++++ linux.dev/arch/mips/pci/pci.c 2006-06-14 20:23:18.000000000 +0200 +@@ -65,8 +65,10 @@ + /* + * Put everything into 0x00-0xff region modulo 0x400 + */ ++#ifndef CONFIG_MIKROTIK_RB500 + if (start & 0x300) + start = (start + 0x3ff) & ~0x3ff; ++#endif + } else if (res->flags & IORESOURCE_MEM) { + /* Make sure we start at our min on all hoses */ + if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start) diff --git a/target/linux/rb532-2.6/patches/210-pci_fixes.patch b/target/linux/rb532-2.6/patches/210-pci_fixes.patch new file mode 100644 index 0000000000..02cd2f063c --- /dev/null +++ b/target/linux/rb532-2.6/patches/210-pci_fixes.patch @@ -0,0 +1,46 @@ +diff -urN linux.old/drivers/pci/probe.c linux.dev/drivers/pci/probe.c +--- linux.old/drivers/pci/probe.c 2006-06-08 20:21:20.000000000 +0200 ++++ linux.dev/drivers/pci/probe.c 2006-06-08 20:19:40.000000000 +0200 +@@ -760,15 +760,22 @@ + u32 l; + u8 hdr_type; + int delay = 1; +- +- if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) +- return NULL; +- +- /* some broken boards return 0 or ~0 if a slot is empty: */ +- if (l == 0xffffffff || l == 0x00000000 || +- l == 0x0000ffff || l == 0xffff0000) +- return NULL; +- ++ do { ++ if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) ++ return NULL; ++ /* some broken boards return 0 or ~0 if a slot is empty: */ ++ if (l == 0xffffffff || l == 0x00000000 || ++ l == 0x0000ffff || l == 0xffff0000){ ++ if (delay > 4) ++ return NULL; ++ /* But that could also be the previous dev not settled */ ++ pr_debug("PCI: retrying scan at 0x%x, because config is 0x%x\n",devfn,l); ++ msleep(delay); ++ delay *=2; ++ l=0; ++ } ++ }while (l==0); ++ + /* Configuration request Retry Status */ + while (l == 0xffff0001) { + msleep(delay); +@@ -903,7 +910,10 @@ + + /* Go find them, Rover! */ + for (devfn = 0; devfn < 0x100; devfn += 8) ++ { ++ if (bus->number == 0 && (devfn >> 3) > 21) break; + pci_scan_slot(bus, devfn); ++ } + + /* + * After performing arch-dependent fixup of the bus, look behind diff --git a/target/linux/rb532-2.6/patches/220-serial_fix.patch b/target/linux/rb532-2.6/patches/220-serial_fix.patch new file mode 100644 index 0000000000..d36f263a33 --- /dev/null +++ b/target/linux/rb532-2.6/patches/220-serial_fix.patch @@ -0,0 +1,18 @@ +diff -urN linux.old/drivers/serial/8250.c linux.dev/drivers/serial/8250.c +--- linux.old/drivers/serial/8250.c 2006-06-08 20:21:20.000000000 +0200 ++++ linux.dev/drivers/serial/8250.c 2006-06-08 20:19:40.000000000 +0200 +@@ -351,6 +351,13 @@ + default: + outb(value, up->port.iobase + offset); + } ++ ++#if defined(CONFIG_IDT_EB434) || defined(CONFIG_MIKROTIK_RB500) ++ __SLOW_DOWN_IO; ++ __SLOW_DOWN_IO; ++ __SLOW_DOWN_IO; ++ __SLOW_DOWN_IO; ++#endif + } + + /* + diff --git a/target/linux/rb532-2.6/patches/230-dma_limit.patch b/target/linux/rb532-2.6/patches/230-dma_limit.patch new file mode 100644 index 0000000000..ca87115704 --- /dev/null +++ b/target/linux/rb532-2.6/patches/230-dma_limit.patch @@ -0,0 +1,13 @@ +diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c +--- linux.old/arch/mips/mm/init.c 2006-06-08 20:21:20.000000000 +0200 ++++ linux.dev/arch/mips/mm/init.c 2006-06-08 20:19:40.000000000 +0200 +@@ -149,7 +149,7 @@ + kmap_init(); + #endif + +- max_dma = virt_to_phys((char *)MAX_DMA_ADDRESS) >> PAGE_SHIFT; ++ max_dma = virt_to_phys((char *) (256 * 1024 * 1024)) >> PAGE_SHIFT; + low = max_low_pfn; + high = highend_pfn; + + diff --git a/target/linux/rb532-2.6/patches/240-via_rhine_performance.patch b/target/linux/rb532-2.6/patches/240-via_rhine_performance.patch new file mode 100644 index 0000000000..56c1fb559c --- /dev/null +++ b/target/linux/rb532-2.6/patches/240-via_rhine_performance.patch @@ -0,0 +1,461 @@ +diff -urN linux.old/drivers/net/via-rhine.c linux.dev/drivers/net/via-rhine.c +--- linux.old/drivers/net/via-rhine.c 2006-06-08 20:21:20.000000000 +0200 ++++ linux.dev/drivers/net/via-rhine.c 2006-06-08 20:19:40.000000000 +0200 +@@ -131,6 +131,10 @@ + - Fix Tx engine race for good + - Craig Brind: Zero padded aligned buffers for short packets. + ++ OpenWrt Version (Felix Fietkau <nbd@openwrt.org>) ++ - Performance improvements ++ - NAPI polling ++ + */ + + #define DRV_NAME "via-rhine" +@@ -142,7 +146,6 @@ + These may be modified when a driver module is loaded. */ + + static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */ +-static int max_interrupt_work = 20; + + /* Set the copy breakpoint for the copy-only-tiny-frames scheme. + Setting to > 1518 effectively disables this feature. */ +@@ -165,9 +168,9 @@ + Making the Tx ring too large decreases the effectiveness of channel + bonding and packet priority. + There are no ill effects from too-large receive rings. */ +-#define TX_RING_SIZE 16 +-#define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */ +-#define RX_RING_SIZE 16 ++#define TX_RING_SIZE 128 ++#define TX_QUEUE_LEN 120 /* Limit ring entries actually used. */ ++#define RX_RING_SIZE 128 + + + /* Operational parameters that usually are not changed. */ +@@ -201,6 +204,7 @@ + #include <asm/io.h> + #include <asm/irq.h> + #include <asm/uaccess.h> ++#include <asm/unaligned.h> + + /* These identify the driver base version and may not be removed. */ + static char version[] __devinitdata = +@@ -217,10 +221,8 @@ + MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver"); + MODULE_LICENSE("GPL"); + +-module_param(max_interrupt_work, int, 0); + module_param(debug, int, 0); + module_param(rx_copybreak, int, 0); +-MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt"); + MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)"); + MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames"); + +@@ -461,6 +463,8 @@ + struct tx_desc *tx_ring; + dma_addr_t rx_ring_dma; + dma_addr_t tx_ring_dma; ++ u32 istat; ++ u32 imask; + + /* The addresses of receive-in-place skbuffs. */ + struct sk_buff *rx_skbuff[RX_RING_SIZE]; +@@ -504,9 +508,10 @@ + static void rhine_check_media_task(struct net_device *dev); + static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev); + static irqreturn_t rhine_interrupt(int irq, void *dev_instance, struct pt_regs *regs); +-static void rhine_tx(struct net_device *dev); +-static void rhine_rx(struct net_device *dev); +-static void rhine_error(struct net_device *dev, int intr_status); ++static int rhine_poll(struct net_device *dev, int *budget); ++static int rhine_tx(struct net_device *dev); ++static int rhine_rx(struct net_device *dev); ++static void rhine_error(struct net_device *dev); + static void rhine_set_rx_mode(struct net_device *dev); + static struct net_device_stats *rhine_get_stats(struct net_device *dev); + static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); +@@ -601,6 +606,8 @@ + struct rhine_private *rp = netdev_priv(dev); + void __iomem *ioaddr = rp->base; + ++ pci_enable_device(rp->pdev); ++ + iowrite8(Cmd1Reset, ioaddr + ChipCmd1); + IOSYNC; + +@@ -622,6 +629,28 @@ + "failed" : "succeeded"); + } + ++static inline void rhine_intr_enable(struct net_device *dev) ++{ ++ struct rhine_private *rp = netdev_priv(dev); ++ void __iomem *ioaddr = rp->base; ++ ++ iowrite16(rp->imask = (IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | ++ IntrRxDropped | IntrRxNoBuf | IntrTxAborted | ++ IntrTxDone | IntrTxError | IntrTxUnderrun | ++ IntrPCIErr | IntrStatsMax | IntrLinkChange), ++ ioaddr + IntrEnable); ++} ++ ++static inline void rhine_intr_disable(struct net_device *dev) ++{ ++ struct rhine_private *rp = netdev_priv(dev); ++ void __iomem *ioaddr = rp->base; ++ ++ iowrite16(rp->imask = (IntrRxOverflow | IntrRxNoBuf | IntrTxAborted | ++ IntrTxError | IntrTxUnderrun | IntrPCIErr | IntrStatsMax | IntrLinkChange), ++ ioaddr + IntrEnable); ++} ++ + #ifdef USE_MMIO + static void enable_mmio(long pioaddr, u32 quirks) + { +@@ -664,14 +693,26 @@ + + } + +-#ifdef CONFIG_NET_POLL_CONTROLLER +-static void rhine_poll(struct net_device *dev) ++static int rhine_poll(struct net_device *dev, int *budget) + { +- disable_irq(dev->irq); +- rhine_interrupt(dev->irq, (void *)dev, NULL); +- enable_irq(dev->irq); ++ unsigned int work_done, work_to_do = min(*budget, dev->quota); ++ struct rhine_private *rp = netdev_priv(dev); ++ ++ work_done = rhine_rx(dev); ++ ++ if (rp->istat & (IntrTxErrSummary | IntrTxDone)) ++ rhine_tx(dev); ++ ++ *budget -= work_done; ++ dev->quota -= work_done; ++ ++ if (work_done < work_to_do) { ++ netif_rx_complete(dev); ++ rhine_intr_enable(dev); ++ } ++ ++ return (work_done >= work_to_do); + } +-#endif + + static void rhine_hw_init(struct net_device *dev, long pioaddr) + { +@@ -850,11 +891,10 @@ + dev->ethtool_ops = &netdev_ethtool_ops; + dev->tx_timeout = rhine_tx_timeout; + dev->watchdog_timeo = TX_TIMEOUT; +-#ifdef CONFIG_NET_POLL_CONTROLLER +- dev->poll_controller = rhine_poll; +-#endif +- if (rp->quirks & rqRhineI) +- dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM; ++ dev->poll = rhine_poll; ++ dev->weight = 64; ++ ++ dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM; + + INIT_WORK(&rp->tx_timeout_task, + (void (*)(void *))rhine_tx_timeout_task, dev); +@@ -904,6 +944,10 @@ + } + } + rp->mii_if.phy_id = phy_id; ++ ++ // shut down until somebody really needs it ++ iowrite8(0x80, ioaddr + 0xa1); ++ pci_set_power_state(rp->pdev, 3); + + return 0; + +@@ -995,7 +1039,7 @@ + + /* Fill in the Rx buffers. Handle allocation failure gracefully. */ + for (i = 0; i < RX_RING_SIZE; i++) { +- struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz); ++ struct sk_buff *skb = dev_alloc_skb(rp->rx_buf_sz + 4); + rp->rx_skbuff[i] = skb; + if (skb == NULL) + break; +@@ -1115,11 +1159,7 @@ + rhine_set_rx_mode(dev); + + /* Enable interrupts by setting the interrupt mask. */ +- iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | +- IntrRxDropped | IntrRxNoBuf | IntrTxAborted | +- IntrTxDone | IntrTxError | IntrTxUnderrun | +- IntrPCIErr | IntrStatsMax | IntrLinkChange, +- ioaddr + IntrEnable); ++ rhine_intr_enable(dev); + + iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8), + ioaddr + ChipCmd); +@@ -1230,6 +1270,7 @@ + mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); + + netif_start_queue(dev); ++ netif_poll_enable(dev); + + return 0; + } +@@ -1268,8 +1309,8 @@ + /* Reinitialize the hardware. */ + rhine_chip_reset(dev); + init_registers(dev); +- + spin_unlock(&rp->lock); ++ + enable_irq(rp->pdev->irq); + + dev->trans_start = jiffies; +@@ -1363,69 +1404,56 @@ + struct net_device *dev = dev_instance; + struct rhine_private *rp = netdev_priv(dev); + void __iomem *ioaddr = rp->base; +- u32 intr_status; +- int boguscnt = max_interrupt_work; + int handled = 0; + +- while ((intr_status = get_intr_status(dev))) { ++ if ((rp->istat = (get_intr_status(dev) & rp->imask))) { + handled = 1; + + /* Acknowledge all of the current interrupt sources ASAP. */ +- if (intr_status & IntrTxDescRace) ++ if (rp->istat & IntrTxDescRace) + iowrite8(0x08, ioaddr + IntrStatus2); +- iowrite16(intr_status & 0xffff, ioaddr + IntrStatus); ++ iowrite16(rp->istat & 0xffff, ioaddr + IntrStatus); + IOSYNC; + +- if (debug > 4) +- printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n", +- dev->name, intr_status); ++ if (likely(rp->istat & ((IntrRxDone | IntrRxErr | IntrRxDropped | ++ IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf | ++ IntrTxErrSummary | IntrTxDone)))) { ++ ++ rhine_intr_disable(dev); + +- if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped | +- IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) +- rhine_rx(dev); +- +- if (intr_status & (IntrTxErrSummary | IntrTxDone)) { +- if (intr_status & IntrTxErrSummary) { +- /* Avoid scavenging before Tx engine turned off */ +- RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn)); +- if (debug > 2 && +- ioread8(ioaddr+ChipCmd) & CmdTxOn) +- printk(KERN_WARNING "%s: " +- "rhine_interrupt() Tx engine" +- "still on.\n", dev->name); +- } +- rhine_tx(dev); ++ if (likely(netif_rx_schedule_prep(dev))) ++ __netif_rx_schedule(dev); + } + + /* Abnormal error summary/uncommon events handlers. */ +- if (intr_status & (IntrPCIErr | IntrLinkChange | ++ if (unlikely(rp->istat & (IntrPCIErr | IntrLinkChange | + IntrStatsMax | IntrTxError | IntrTxAborted | +- IntrTxUnderrun | IntrTxDescRace)) +- rhine_error(dev, intr_status); +- +- if (--boguscnt < 0) { +- printk(KERN_WARNING "%s: Too much work at interrupt, " +- "status=%#8.8x.\n", +- dev->name, intr_status); +- break; +- } ++ IntrTxUnderrun | IntrTxDescRace))) ++ rhine_error(dev); + } + +- if (debug > 3) +- printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n", +- dev->name, ioread16(ioaddr + IntrStatus)); + return IRQ_RETVAL(handled); + } + + /* This routine is logically part of the interrupt handler, but isolated + for clarity. */ +-static void rhine_tx(struct net_device *dev) ++static int rhine_tx(struct net_device *dev) + { + struct rhine_private *rp = netdev_priv(dev); + int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE; ++ void __iomem *ioaddr = rp->base; ++ int done = 0; + +- spin_lock(&rp->lock); ++ /* Avoid scavenging before Tx engine turned off */ ++ RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn)); ++ if (debug > 2 && ++ ioread8(ioaddr+ChipCmd) & CmdTxOn) ++ printk(KERN_WARNING "%s: " ++ "rhine_interrupt() Tx engine" ++ "still on.\n", dev->name); + ++ ++ spin_lock_irq(&rp->lock); + /* find and cleanup dirty tx descriptors */ + while (rp->dirty_tx != rp->cur_tx) { + txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status); +@@ -1462,6 +1490,7 @@ + txstatus & 0xF); + rp->stats.tx_bytes += rp->tx_skbuff[entry]->len; + rp->stats.tx_packets++; ++ done++; + } + /* Free the original skb. */ + if (rp->tx_skbuff_dma[entry]) { +@@ -1470,23 +1499,25 @@ + rp->tx_skbuff[entry]->len, + PCI_DMA_TODEVICE); + } +- dev_kfree_skb_irq(rp->tx_skbuff[entry]); ++ dev_kfree_skb_any(rp->tx_skbuff[entry]); + rp->tx_skbuff[entry] = NULL; + entry = (++rp->dirty_tx) % TX_RING_SIZE; + } ++ spin_unlock_irq(&rp->lock); ++ + if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4) + netif_wake_queue(dev); + +- spin_unlock(&rp->lock); ++ return done; + } + + /* This routine is logically part of the interrupt handler, but isolated + for clarity and better register allocation. */ +-static void rhine_rx(struct net_device *dev) ++static int rhine_rx(struct net_device *dev) + { + struct rhine_private *rp = netdev_priv(dev); + int entry = rp->cur_rx % RX_RING_SIZE; +- int boguscnt = rp->dirty_rx + RX_RING_SIZE - rp->cur_rx; ++ int done = 0; + + if (debug > 4) { + printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n", +@@ -1503,8 +1534,6 @@ + if (debug > 4) + printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n", + desc_status); +- if (--boguscnt < 0) +- break; + if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) { + if ((desc_status & RxWholePkt) != RxWholePkt) { + printk(KERN_WARNING "%s: Oversized Ethernet " +@@ -1528,9 +1557,7 @@ + if (desc_status & 0x0004) rp->stats.rx_frame_errors++; + if (desc_status & 0x0002) { + /* this can also be updated outside the interrupt handler */ +- spin_lock(&rp->lock); + rp->stats.rx_crc_errors++; +- spin_unlock(&rp->lock); + } + } + } else { +@@ -1558,6 +1585,7 @@ + rp->rx_buf_sz, + PCI_DMA_FROMDEVICE); + } else { ++ int i; + skb = rp->rx_skbuff[entry]; + if (skb == NULL) { + printk(KERN_ERR "%s: Inconsistent Rx " +@@ -1566,6 +1594,14 @@ + break; + } + rp->rx_skbuff[entry] = NULL; ++ ++ /* align the data to the ip header - should be faster than using rx_copybreak */ ++ for (i = pkt_len - (pkt_len % 4); i >= 0; i -= 4) { ++ put_unaligned(*((u32 *) (skb->data + i)), (u32 *) (skb->data + i + 2)); ++ } ++ skb->data += 2; ++ skb->tail += 2; ++ + skb_put(skb, pkt_len); + pci_unmap_single(rp->pdev, + rp->rx_skbuff_dma[entry], +@@ -1573,10 +1609,11 @@ + PCI_DMA_FROMDEVICE); + } + skb->protocol = eth_type_trans(skb, dev); +- netif_rx(skb); ++ netif_receive_skb(skb); + dev->last_rx = jiffies; + rp->stats.rx_bytes += pkt_len; + rp->stats.rx_packets++; ++ done++; + } + entry = (++rp->cur_rx) % RX_RING_SIZE; + rp->rx_head_desc = &rp->rx_ring[entry]; +@@ -1587,7 +1624,7 @@ + struct sk_buff *skb; + entry = rp->dirty_rx % RX_RING_SIZE; + if (rp->rx_skbuff[entry] == NULL) { +- skb = dev_alloc_skb(rp->rx_buf_sz); ++ skb = dev_alloc_skb(rp->rx_buf_sz + 4); + rp->rx_skbuff[entry] = skb; + if (skb == NULL) + break; /* Better luck next round. */ +@@ -1600,6 +1637,8 @@ + } + rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn); + } ++ ++ return done; + } + + /* +@@ -1649,11 +1688,11 @@ + + } + +-static void rhine_error(struct net_device *dev, int intr_status) ++static void rhine_error(struct net_device *dev) + { + struct rhine_private *rp = netdev_priv(dev); + void __iomem *ioaddr = rp->base; +- ++ u32 intr_status = rp->istat; + spin_lock(&rp->lock); + + if (intr_status & IntrLinkChange) +@@ -1898,6 +1937,7 @@ + + /* Disable interrupts by clearing the interrupt mask. */ + iowrite16(0x0000, ioaddr + IntrEnable); ++ rp->imask = 0; + + /* Stop the chip's Tx and Rx processes. */ + iowrite16(CmdStop, ioaddr + ChipCmd); +@@ -1912,6 +1952,9 @@ + free_tbufs(dev); + free_ring(dev); + ++ writeb(0x80, ioaddr + 0xa1); ++ pci_set_power_state(rp->pdev, 3); ++ + return 0; + } + +@@ -1941,6 +1984,7 @@ + return; /* Nothing to do for non-WOL adapters */ + + rhine_power_init(dev); ++ netif_poll_disable(dev); + + /* Make sure we use pattern 0, 1 and not 4, 5 */ + if (rp->quirks & rq6patterns) |