diff options
Diffstat (limited to 'target/linux/ramips/patches-4.14/102-mt7621-fix-cpu-clk-add-clkdev.patch')
| -rw-r--r-- | target/linux/ramips/patches-4.14/102-mt7621-fix-cpu-clk-add-clkdev.patch | 224 |
1 files changed, 0 insertions, 224 deletions
diff --git a/target/linux/ramips/patches-4.14/102-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-4.14/102-mt7621-fix-cpu-clk-add-clkdev.patch deleted file mode 100644 index e647a2f4c8..0000000000 --- a/target/linux/ramips/patches-4.14/102-mt7621-fix-cpu-clk-add-clkdev.patch +++ /dev/null @@ -1,224 +0,0 @@ ---- a/arch/mips/include/asm/mach-ralink/mt7621.h -+++ b/arch/mips/include/asm/mach-ralink/mt7621.h -@@ -19,6 +19,10 @@ - #define SYSC_REG_CHIP_REV 0x0c - #define SYSC_REG_SYSTEM_CONFIG0 0x10 - #define SYSC_REG_SYSTEM_CONFIG1 0x14 -+#define SYSC_REG_CLKCFG0 0x2c -+#define SYSC_REG_CUR_CLK_STS 0x44 -+ -+#define MEMC_REG_CPU_PLL 0x648 - - #define CHIP_REV_PKG_MASK 0x1 - #define CHIP_REV_PKG_SHIFT 16 -@@ -26,6 +30,22 @@ - #define CHIP_REV_VER_SHIFT 8 - #define CHIP_REV_ECO_MASK 0xf - -+#define XTAL_MODE_SEL_MASK 0x7 -+#define XTAL_MODE_SEL_SHIFT 6 -+ -+#define CPU_CLK_SEL_MASK 0x3 -+#define CPU_CLK_SEL_SHIFT 30 -+ -+#define CUR_CPU_FDIV_MASK 0x1f -+#define CUR_CPU_FDIV_SHIFT 8 -+#define CUR_CPU_FFRAC_MASK 0x1f -+#define CUR_CPU_FFRAC_SHIFT 0 -+ -+#define CPU_PLL_PREDIV_MASK 0x3 -+#define CPU_PLL_PREDIV_SHIFT 12 -+#define CPU_PLL_FBDIV_MASK 0x7f -+#define CPU_PLL_FBDIV_SHIFT 4 -+ - #define MT7621_DRAM_BASE 0x0 - #define MT7621_DDR2_SIZE_MIN 32 - #define MT7621_DDR2_SIZE_MAX 256 ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -10,6 +10,10 @@ - #include <linux/kernel.h> - #include <linux/init.h> - #include <linux/jiffies.h> -+#include <linux/clk.h> -+#include <linux/clkdev.h> -+#include <linux/clk-provider.h> -+#include <dt-bindings/clock/mt7621-clk.h> - - #include <asm/mipsregs.h> - #include <asm/smp-ops.h> -@@ -18,16 +22,12 @@ - #include <asm/mach-ralink/mt7621.h> - #include <asm/mips-boards/launch.h> - #include <asm/delay.h> -+#include <asm/time.h> - - #include <pinmux.h> - - #include "common.h" - --#define SYSC_REG_SYSCFG 0x10 --#define SYSC_REG_CPLL_CLKCFG0 0x2c --#define SYSC_REG_CUR_CLK_STS 0x44 --#define CPU_CLK_SEL (BIT(30) | BIT(31)) -- - #define MT7621_GPIO_MODE_UART1 1 - #define MT7621_GPIO_MODE_I2C 2 - #define MT7621_GPIO_MODE_UART3_MASK 0x3 -@@ -113,49 +113,89 @@ static struct rt2880_pmx_group mt7621_pi - { 0 } - }; - -+static struct clk *clks[MT7621_CLK_MAX]; -+static struct clk_onecell_data clk_data = { -+ .clks = clks, -+ .clk_num = ARRAY_SIZE(clks), -+}; -+ - phys_addr_t mips_cpc_default_phys_base(void) - { - panic("Cannot detect cpc address"); - } - --void __init ralink_clk_init(void) -+static struct clk *__init mt7621_add_sys_clkdev( -+ const char *id, unsigned long rate) - { -- int cpu_fdiv = 0; -- int cpu_ffrac = 0; -- int fbdiv = 0; -- u32 clk_sts, syscfg; -- u8 clk_sel = 0, xtal_mode; -- u32 cpu_clk; -+ struct clk *clk; -+ int err; -+ -+ clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate); -+ if (IS_ERR(clk)) -+ panic("failed to allocate %s clock structure", id); -+ -+ err = clk_register_clkdev(clk, id, NULL); -+ if (err) -+ panic("unable to register %s clock device", id); - -- if ((rt_sysc_r32(SYSC_REG_CPLL_CLKCFG0) & CPU_CLK_SEL) != 0) -- clk_sel = 1; -+ return clk; -+} -+ -+void __init ralink_clk_init(void) -+{ -+ u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; -+ u32 pll, prediv, fbdiv; -+ u32 xtal_clk, cpu_clk, bus_clk; -+ const static u32 prediv_tbl[] = {0, 1, 2, 2}; -+ -+ syscfg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0); -+ xtal_sel = (syscfg >> XTAL_MODE_SEL_SHIFT) & XTAL_MODE_SEL_MASK; -+ -+ clkcfg = rt_sysc_r32(SYSC_REG_CLKCFG0); -+ clk_sel = (clkcfg >> CPU_CLK_SEL_SHIFT) & CPU_CLK_SEL_MASK; -+ -+ curclk = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); -+ ffiv = (curclk >> CUR_CPU_FDIV_SHIFT) & CUR_CPU_FDIV_MASK; -+ ffrac = (curclk >> CUR_CPU_FFRAC_SHIFT) & CUR_CPU_FFRAC_MASK; -+ -+ if (xtal_sel <= 2) -+ xtal_clk = 20 * 1000 * 1000; -+ else if (xtal_sel <= 5) -+ xtal_clk = 40 * 1000 * 1000; -+ else -+ xtal_clk = 25 * 1000 * 1000; - - switch (clk_sel) { - case 0: -- clk_sts = rt_sysc_r32(SYSC_REG_CUR_CLK_STS); -- cpu_fdiv = ((clk_sts >> 8) & 0x1F); -- cpu_ffrac = (clk_sts & 0x1F); -- cpu_clk = (500 * cpu_ffrac / cpu_fdiv) * 1000 * 1000; -+ cpu_clk = 500 * 1000 * 1000; - break; -- - case 1: -- fbdiv = ((rt_sysc_r32(0x648) >> 4) & 0x7F) + 1; -- syscfg = rt_sysc_r32(SYSC_REG_SYSCFG); -- xtal_mode = (syscfg >> 6) & 0x7; -- if (xtal_mode >= 6) { -- /* 25Mhz Xtal */ -- cpu_clk = 25 * fbdiv * 1000 * 1000; -- } else if (xtal_mode >= 3) { -- /* 40Mhz Xtal */ -- cpu_clk = 40 * fbdiv * 1000 * 1000; -- } else { -- /* 20Mhz Xtal */ -- cpu_clk = 20 * fbdiv * 1000 * 1000; -- } -+ pll = rt_memc_r32(MEMC_REG_CPU_PLL); -+ fbdiv = (pll >> CPU_PLL_FBDIV_SHIFT) & CPU_PLL_FBDIV_MASK; -+ prediv = (pll >> CPU_PLL_PREDIV_SHIFT) & CPU_PLL_PREDIV_MASK; -+ cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; - break; -+ default: -+ cpu_clk = xtal_clk; - } -+ -+ cpu_clk = cpu_clk / ffiv * ffrac; -+ bus_clk = cpu_clk / 4; -+ -+ clks[MT7621_CLK_CPU] = mt7621_add_sys_clkdev("cpu", cpu_clk); -+ clks[MT7621_CLK_BUS] = mt7621_add_sys_clkdev("bus", bus_clk); -+ -+ pr_info("CPU Clock: %dMHz\n", cpu_clk / 1000000); -+ mips_hpt_frequency = cpu_clk / 2; - } - -+static void __init mt7621_clocks_init_dt(struct device_node *np) -+{ -+ of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); -+} -+ -+CLK_OF_DECLARE(ar7100, "mediatek,mt7621-pll", mt7621_clocks_init_dt); -+ - void __init ralink_of_remap(void) - { - rt_sysc_membase = plat_of_remap_node("mtk,mt7621-sysc"); ---- a/arch/mips/ralink/timer-gic.c -+++ b/arch/mips/ralink/timer-gic.c -@@ -11,14 +11,14 @@ - - #include <linux/of.h> - #include <linux/clk-provider.h> --#include <linux/clocksource.h> -+#include <asm/time.h> - - #include "common.h" - - void __init plat_time_init(void) - { - ralink_of_remap(); -- -+ ralink_clk_init(); - of_clk_init(NULL); - timer_probe(); - } ---- /dev/null -+++ b/include/dt-bindings/clock/mt7621-clk.h -@@ -0,0 +1,18 @@ -+/* -+ * Copyright (C) 2018 Weijie Gao <hackpascal@gmail.com> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __DT_BINDINGS_MT7621_CLK_H -+#define __DT_BINDINGS_MT7621_CLK_H -+ -+#define MT7621_CLK_CPU 0 -+#define MT7621_CLK_BUS 1 -+ -+#define MT7621_CLK_MAX 2 -+ -+#endif /* __DT_BINDINGS_MT7621_CLK_H */ |