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-rw-r--r--target/linux/ramips/patches-3.8/0102-MIPS-ralink-add-RT3352-register-defines.patch35
1 files changed, 35 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.8/0102-MIPS-ralink-add-RT3352-register-defines.patch b/target/linux/ramips/patches-3.8/0102-MIPS-ralink-add-RT3352-register-defines.patch
new file mode 100644
index 0000000000..2d296db665
--- /dev/null
+++ b/target/linux/ramips/patches-3.8/0102-MIPS-ralink-add-RT3352-register-defines.patch
@@ -0,0 +1,35 @@
+From e6bcdad6f0811daedc2a448f5d7fb98c116a5241 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 21 Mar 2013 19:01:49 +0100
+Subject: [PATCH 102/137] MIPS: ralink: add RT3352 register defines
+
+Add a few missing defines that are needed to make USB and clock detection work
+on the RT3352.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+Acked-by: Gabor Juhos <juhosg@openwrt.org>
+Patchwork: http://patchwork.linux-mips.org/patch/5166/
+---
+ arch/mips/include/asm/mach-ralink/rt305x.h | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/mips/include/asm/mach-ralink/rt305x.h
++++ b/arch/mips/include/asm/mach-ralink/rt305x.h
+@@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void)
+ #define RT305X_GPIO_MODE_SDRAM BIT(8)
+ #define RT305X_GPIO_MODE_RGMII BIT(9)
+
++#define RT3352_SYSC_REG_SYSCFG0 0x010
++#define RT3352_SYSC_REG_SYSCFG1 0x014
++#define RT3352_SYSC_REG_CLKCFG1 0x030
++#define RT3352_SYSC_REG_RSTCTRL 0x034
++#define RT3352_SYSC_REG_USB_PS 0x05c
++
++#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
++#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
++#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
++#define RT3352_RSTCTRL_UHST BIT(22)
++#define RT3352_RSTCTRL_UDEV BIT(25)
++#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
++
+ #endif