aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch')
-rw-r--r--target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch40
1 files changed, 0 insertions, 40 deletions
diff --git a/target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch b/target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch
deleted file mode 100644
index 1a8950fcd6..0000000000
--- a/target/linux/ramips/patches-3.8/0018-MIPS-ralink-add-RT3352-register-defines.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From 8667d984d1b4f3be1c5da71788762b9945a25c90 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 21 Mar 2013 19:01:49 +0100
-Subject: [PATCH 18/79] MIPS: ralink: add RT3352 register defines
-
-Add a few missing defines that are needed to make USB and clock detection work
-on the RT3352.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Acked-by: Gabor Juhos <juhosg@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/5166/
----
- arch/mips/include/asm/mach-ralink/rt305x.h | 13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
-diff --git a/arch/mips/include/asm/mach-ralink/rt305x.h b/arch/mips/include/asm/mach-ralink/rt305x.h
-index 7d344f2..e36c3c5 100644
---- a/arch/mips/include/asm/mach-ralink/rt305x.h
-+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
-@@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void)
- #define RT305X_GPIO_MODE_SDRAM BIT(8)
- #define RT305X_GPIO_MODE_RGMII BIT(9)
-
-+#define RT3352_SYSC_REG_SYSCFG0 0x010
-+#define RT3352_SYSC_REG_SYSCFG1 0x014
-+#define RT3352_SYSC_REG_CLKCFG1 0x030
-+#define RT3352_SYSC_REG_RSTCTRL 0x034
-+#define RT3352_SYSC_REG_USB_PS 0x05c
-+
-+#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
-+#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
-+#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
-+#define RT3352_RSTCTRL_UHST BIT(22)
-+#define RT3352_RSTCTRL_UDEV BIT(25)
-+#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
-+
- #endif
---
-1.7.10.4
-