diff options
Diffstat (limited to 'target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch')
-rw-r--r-- | target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch b/target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch deleted file mode 100644 index e358e622b2..0000000000 --- a/target/linux/ramips/patches-3.10/0200-MIPS-Fix-TLBR-use-hazards-for-R2-cores-in-the-TLB-re.patch +++ /dev/null @@ -1,60 +0,0 @@ -From f281fdccbb3e762d293e6eef7f291a33b84e0f6a Mon Sep 17 00:00:00 2001 -From: Ralf Baechle <ralf@linux-mips.org> -Date: Thu, 20 Jun 2013 14:56:17 +0200 -Subject: [PATCH 200/215] MIPS: Fix TLBR-use hazards for R2 cores in the TLB - reload handlers - -MIPS R2 documents state that an execution hazard barrier is needed -after a TLBR before reading EntryLo. - -Original patch by Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>. - -Signed-off-by: Ralf Baechle <ralf@linux-mips.org> -Patchwork: https://patchwork.linux-mips.org/patch/5526/ -(cherry picked from commit 73acc7df534ff458a81435178dab3ea037ed6d78) ---- - arch/mips/mm/tlbex.c | 26 ++++++++++++++++++++++++++ - 1 file changed, 26 insertions(+) - ---- a/arch/mips/mm/tlbex.c -+++ b/arch/mips/mm/tlbex.c -@@ -1935,6 +1935,19 @@ static void __cpuinit build_r4000_tlb_lo - uasm_i_nop(&p); - - uasm_i_tlbr(&p); -+ -+ switch (current_cpu_type()) { -+ default: -+ if (cpu_has_mips_r2) { -+ uasm_i_ehb(&p); -+ -+ case CPU_CAVIUM_OCTEON: -+ case CPU_CAVIUM_OCTEON_PLUS: -+ case CPU_CAVIUM_OCTEON2: -+ break; -+ } -+ } -+ - /* Examine entrylo 0 or 1 based on ptr. */ - if (use_bbit_insns()) { - uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); -@@ -1989,6 +2002,19 @@ static void __cpuinit build_r4000_tlb_lo - uasm_i_nop(&p); - - uasm_i_tlbr(&p); -+ -+ switch (current_cpu_type()) { -+ default: -+ if (cpu_has_mips_r2) { -+ uasm_i_ehb(&p); -+ -+ case CPU_CAVIUM_OCTEON: -+ case CPU_CAVIUM_OCTEON_PLUS: -+ case CPU_CAVIUM_OCTEON2: -+ break; -+ } -+ } -+ - /* Examine entrylo 0 or 1 based on ptr. */ - if (use_bbit_insns()) { - uasm_i_bbit0(&p, wr.r2, ilog2(sizeof(pte_t)), 8); |