diff options
Diffstat (limited to 'target/linux/ramips/dts/mt7621_firefly_firewrt.dts')
-rw-r--r-- | target/linux/ramips/dts/mt7621_firefly_firewrt.dts | 130 |
1 files changed, 130 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7621_firefly_firewrt.dts b/target/linux/ramips/dts/mt7621_firefly_firewrt.dts new file mode 100644 index 0000000000..2abc01b2af --- /dev/null +++ b/target/linux/ramips/dts/mt7621_firefly_firewrt.dts @@ -0,0 +1,130 @@ +/dts-v1/; + +#include "mt7621.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + compatible = "firefly,firewrt", "mediatek,mt7621-soc"; + model = "Firefly FireWRT"; + + aliases { + led-boot = &led_power; + led-failsafe = &led_power; + led-running = &led_power; + led-upgrade = &led_power; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x1c000000>, <0x20000000 0x4000000>; + }; + + chosen { + bootargs = "console=ttyS0,57600"; + }; + + leds { + compatible = "gpio-leds"; + + led_power: power { + label = "firewrt:green:power"; + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + }; + }; + + keys { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + wps { + label = "wps"; + gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WPS_BUTTON>; + }; + + power { + label = "power"; + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + }; + }; +}; + +&sdhci { + status = "okay"; +}; + +&spi0 { + status = "okay"; + + m25p80@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "u-boot-env"; + reg = <0x30000 0x10000>; + read-only; + }; + + factory: partition@40000 { + label = "factory"; + reg = <0x40000 0x10000>; + read-only; + }; + + partition@50000 { + compatible = "denx,uimage"; + label = "firmware"; + reg = <0x50000 0xfb0000>; + }; + }; + }; +}; + +&pcie { + status = "okay"; +}; + +&pcie0 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x8000>; + ieee80211-freq-limit = <5000000 6000000>; + }; +}; + +&pcie1 { + mt76@0,0 { + reg = <0x0000 0 0 0 0>; + mediatek,mtd-eeprom = <&factory 0x0000>; + ieee80211-freq-limit = <2400000 2500000>; + }; +}; + +ðernet { + mtd-mac-address = <&factory 0xe000>; +}; + +&pinctrl { + state_default: pinctrl0 { + gpio { + ralink,group = "wdt", "rgmii2"; + ralink,function = "gpio"; + }; + }; +}; |