diff options
Diffstat (limited to 'target/linux/ramips/dts/mt7621.dtsi')
| -rw-r--r-- | target/linux/ramips/dts/mt7621.dtsi | 60 |
1 files changed, 0 insertions, 60 deletions
diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 0f513f313c..3e076741a9 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -41,15 +41,6 @@ bootargs = "console=ttyS0,57600"; }; -#ifdef DTS_LEGACY - pll: pll { - compatible = "mediatek,mt7621-pll", "syscon"; - - #clock-cells = <1>; - clock-output-names = "cpu", "bus"; - }; -#endif - sysclock: sysclock { #clock-cells = <0>; compatible = "fixed-clock"; @@ -67,16 +58,12 @@ #size-cells = <1>; sysc: syscon@0 { -#ifdef DTS_LEGACY - compatible = "mtk,mt7621-sysc", "syscon"; -#else compatible = "mediatek,mt7621-sysc", "syscon"; #clock-cells = <1>; ralink,memctl = <&memc>; clock-output-names = "xtal", "cpu", "bus", "50m", "125m", "150m", "250m", "270m"; -#endif reg = <0x0 0x100>; }; @@ -149,11 +136,7 @@ }; memc: syscon@5000 { -#ifdef DTS_LEGACY - compatible = "mtk,mt7621-memc", "syscon"; -#else compatible = "mediatek,mt7621-memc", "syscon"; -#endif reg = <0x5000 0x1000>; }; @@ -213,11 +196,7 @@ compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; -#ifdef DTS_LEGACY - clocks = <&pll MT7621_CLK_BUS>; -#else clocks = <&sysc MT7621_CLK_BUS>; -#endif resets = <&rstctrl 18>; reset-names = "spi"; @@ -425,11 +404,7 @@ timer { compatible = "mti,gic-timer"; interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; -#ifdef DTS_LEGACY - clocks = <&pll MT7621_CLK_CPU>; -#else clocks = <&sysc MT7621_CLK_CPU>; -#endif }; }; @@ -466,14 +441,9 @@ compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; -#ifdef DTS_LEGACY - clocks = <&sysclock>; - clock-names = "ethif"; -#else clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; clock-names = "fe", "ethif"; -#endif #address-cells = <1>; #size-cells = <0>; @@ -586,36 +556,16 @@ device_type = "pci"; -#ifdef DTS_LEGACY - ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */ - <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ -#else ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ -#endif status = "disabled"; -#ifdef DTS_LEGACY - interrupt-parent = <&gic>; - interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH - GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH - GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; - - - resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>; - reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>; - clock-names = "pcie0", "pcie1", "pcie2"; - phys = <&pcie0_phy 1>, <&pcie2_phy 0>; - phy-names = "pcie-phy0", "pcie-phy2"; -#else #interrupt-cells = <1>; interrupt-map-mask = <0xF800 0 0 0>; interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; -#endif reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; @@ -625,7 +575,6 @@ #size-cells = <2>; device_type = "pci"; ranges; -#ifndef DTS_LEGACY #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; @@ -633,7 +582,6 @@ clocks = <&sysc MT7621_CLK_PCIE0>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy0"; -#endif }; pcie1: pcie@1,0 { @@ -642,7 +590,6 @@ #size-cells = <2>; device_type = "pci"; ranges; -#ifndef DTS_LEGACY #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; @@ -650,7 +597,6 @@ clocks = <&sysc MT7621_CLK_PCIE1>; phys = <&pcie0_phy 1>; phy-names = "pcie-phy1"; -#endif }; pcie2: pcie@2,0 { @@ -659,7 +605,6 @@ #size-cells = <2>; device_type = "pci"; ranges; -#ifndef DTS_LEGACY #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; @@ -667,25 +612,20 @@ clocks = <&sysc MT7621_CLK_PCIE2>; phys = <&pcie2_phy 0>; phy-names = "pcie-phy2"; -#endif }; }; pcie0_phy: pcie-phy@1e149000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e149000 0x0700>; -#ifndef DTS_LEGACY clocks = <&sysc MT7621_CLK_XTAL>; -#endif #phy-cells = <1>; }; pcie2_phy: pcie-phy@1e14a000 { compatible = "mediatek,mt7621-pci-phy"; reg = <0x1e14a000 0x0700>; -#ifndef DTS_LEGACY clocks = <&sysc MT7621_CLK_XTAL>; -#endif #phy-cells = <1>; }; }; |