1 files changed, 114 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts b/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts
new file mode 100644
index 0000000000..6f76a64039
--- /dev/null
+++ b/target/linux/ramips/dts/mt7620n_dlink_dwr-116-a1.dts
@@ -0,0 +1,114 @@
+/dts-v1/;
+
+#include "mt7620n.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	compatible = "dlink,dwr-116-a1", "ralink,mt7620n-soc";
+	model = "D-Link DWR-116 A1/A2";
+
+	aliases {
+		led-boot = &led_status;
+		led-failsafe = &led_status;
+		led-running = &led_status;
+		led-upgrade = &led_status;
+	};
+
+	keys {
+		compatible = "gpio-keys-polled";
+		poll-interval = <20>;
+
+		wps {
+			label = "wps";
+			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_WPS_BUTTON>;
+		};
+
+		reset {
+			label = "reset";
+			gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+			linux,code = <KEY_RESTART>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_status: status {
+			label = "dwr-116-a1:green:status";
+			gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		wifi {
+			label = "dwr-116-a1:green:wifi";
+			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "jboot";
+				reg = <0x0 0x10000>;
+				read-only;
+			};
+
+			partition@10000 {
+				compatible = "amit,jimage";
+				label = "firmware";
+				reg = <0x10000 0x7e0000>;
+			};
+
+			config: partition@7f0000 {
+				label = "config";
+				reg = <0x7f0000 0x10000>;
+				read-only;
+			};
+		};
+	};
+};
+
+&ehci {
+	status = "okay";
+};
+
+&ohci {
+	status = "okay";
+};
+
+&pinctrl {
+	state_default: pinctrl0 {
+		default {
+			ralink,group = "i2c", "wled";
+			ralink,function = "gpio";
+		};
+	};
+};
+
+&ethernet {
+	mediatek,portmap = "llllw";
+	pinctrl-names = "default";
+	pinctrl-0 = <&ephy_pins>;
+};