diff options
Diffstat (limited to 'target/linux/octeontx/patches-5.4')
4 files changed, 312 insertions, 0 deletions
diff --git a/target/linux/octeontx/patches-5.4/0001-net-thunderx-use-proper-interface-type-for-RGMII.patch b/target/linux/octeontx/patches-5.4/0001-net-thunderx-use-proper-interface-type-for-RGMII.patch new file mode 100644 index 0000000000..0369e6ff67 --- /dev/null +++ b/target/linux/octeontx/patches-5.4/0001-net-thunderx-use-proper-interface-type-for-RGMII.patch @@ -0,0 +1,47 @@ +From 2d3da16317086ba6048c601ee88cdc96f19fd741 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Fri, 7 Feb 2020 12:40:26 -0800 +Subject: [PATCH 01/12] net: thunderx: use proper interface type for RGMII + +The configuration of the OCTEONTX XCV_DLL_CTL register via +xcv_init_hw() is such that the RGMII RX delay is bypassed +leaving the RGMII TX delay enabled in the MAC: + + /* Configure DLL - enable or bypass + * TX no bypass, RX bypass + */ + cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL); + cfg &= ~0xFF03; + cfg |= CLKRX_BYP; + writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL); + +This would coorespond to a interface type of PHY_INTERFACE_MODE_RGMII_RXID +and not PHY_INTERFACE_MODE_RGMII. + +Fixing this allows RGMII PHY drivers to do the right thing (enable +RX delay in the PHY) instead of erroneously enabling both delays in the +PHY. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +Reviewed-by: Andrew Lunn <andrew@lunn.ch> +Signed-off-by: David S. Miller <davem@davemloft.net> +--- + drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +index 8ae28f8..5f2db9c 100644 +--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c ++++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +@@ -1042,7 +1042,7 @@ static int phy_interface_mode(u8 lmac_type) + if (lmac_type == BGX_MODE_QSGMII) + return PHY_INTERFACE_MODE_QSGMII; + if (lmac_type == BGX_MODE_RGMII) +- return PHY_INTERFACE_MODE_RGMII; ++ return PHY_INTERFACE_MODE_RGMII_RXID; + + return PHY_INTERFACE_MODE_SGMII; + } +-- +2.7.4 + diff --git a/target/linux/octeontx/patches-5.4/0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch b/target/linux/octeontx/patches-5.4/0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch new file mode 100644 index 0000000000..597dd9da74 --- /dev/null +++ b/target/linux/octeontx/patches-5.4/0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch @@ -0,0 +1,150 @@ +From 585ddca487c827178cf697f8bc2e87346061d155 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Wed, 19 Feb 2020 15:19:36 -0800 +Subject: [PATCH 02/12] net: thunderx: workaround BGX TX Underflow issue + +While it is not yet understood why a TX underflow can easily occur +for SGMII interfaces resulting in a TX wedge. It has been found that +disabling/re-enabling the LMAC resolves the issue. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +Reviewed-by: Robert Jones <rjones@gateworks.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +--- + drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 62 +++++++++++++++++++++-- + drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 9 ++++ + 2 files changed, 68 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +index 5f2db9c..ade414a 100644 +--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c ++++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +@@ -413,10 +413,19 @@ void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable) + lmac = &bgx->lmac[lmacid]; + + cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); +- if (enable) ++ if (enable) { + cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN; +- else ++ ++ /* enable TX FIFO Underflow interrupt */ ++ bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1S, ++ GMI_TXX_INT_UNDFLW); ++ } else { + cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN); ++ ++ /* Disable TX FIFO Underflow interrupt */ ++ bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1C, ++ GMI_TXX_INT_UNDFLW); ++ } + bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); + + if (bgx->is_rgx) +@@ -1544,6 +1553,48 @@ static int bgx_init_phy(struct bgx *bgx) + return bgx_init_of_phy(bgx); + } + ++static irqreturn_t bgx_intr_handler(int irq, void *data) ++{ ++ struct bgx *bgx = (struct bgx *)data; ++ u64 status, val; ++ int lmac; ++ ++ for (lmac = 0; lmac < bgx->lmac_count; lmac++) { ++ status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT); ++ if (status & GMI_TXX_INT_UNDFLW) { ++ pci_err(bgx->pdev, "BGX%d lmac%d UNDFLW\n", ++ bgx->bgx_id, lmac); ++ val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG); ++ val &= ~CMR_EN; ++ bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val); ++ val |= CMR_EN; ++ bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val); ++ } ++ /* clear interrupts */ ++ bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void bgx_register_intr(struct pci_dev *pdev) ++{ ++ struct bgx *bgx = pci_get_drvdata(pdev); ++ int ret; ++ ++ ret = pci_alloc_irq_vectors(pdev, BGX_LMAC_VEC_OFFSET, ++ BGX_LMAC_VEC_OFFSET, PCI_IRQ_ALL_TYPES); ++ if (ret < 0) { ++ pci_err(pdev, "Req for #%d msix vectors failed\n", ++ BGX_LMAC_VEC_OFFSET); ++ return; ++ } ++ ret = pci_request_irq(pdev, GMPX_GMI_TX_INT, bgx_intr_handler, NULL, ++ bgx, "BGX%d", bgx->bgx_id); ++ if (ret) ++ pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx); ++} ++ + static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + { + int err; +@@ -1559,7 +1610,7 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + + pci_set_drvdata(pdev, bgx); + +- err = pci_enable_device(pdev); ++ err = pcim_enable_device(pdev); + if (err) { + dev_err(dev, "Failed to enable PCI device\n"); + pci_set_drvdata(pdev, NULL); +@@ -1613,6 +1664,8 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + + bgx_init_hw(bgx); + ++ bgx_register_intr(pdev); ++ + /* Enable all LMACs */ + for (lmac = 0; lmac < bgx->lmac_count; lmac++) { + err = bgx_lmac_enable(bgx, lmac); +@@ -1629,6 +1682,7 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + + err_enable: + bgx_vnic[bgx->bgx_id] = NULL; ++ pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx); + err_release_regions: + pci_release_regions(pdev); + err_disable_device: +@@ -1646,6 +1700,8 @@ static void bgx_remove(struct pci_dev *pdev) + for (lmac = 0; lmac < bgx->lmac_count; lmac++) + bgx_lmac_disable(bgx, lmac); + ++ pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx); ++ + bgx_vnic[bgx->bgx_id] = NULL; + pci_release_regions(pdev); + pci_disable_device(pdev); +diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h +index cbdd20b..ac0c89c 100644 +--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h ++++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h +@@ -183,6 +183,15 @@ + #define BGX_GMP_GMI_TXX_BURST 0x38228 + #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 + #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 ++#define BGX_GMP_GMI_TXX_INT 0x38500 ++#define BGX_GMP_GMI_TXX_INT_W1S 0x38508 ++#define BGX_GMP_GMI_TXX_INT_ENA_W1C 0x38510 ++#define BGX_GMP_GMI_TXX_INT_ENA_W1S 0x38518 ++#define GMI_TXX_INT_PTP_LOST BIT_ULL(4) ++#define GMI_TXX_INT_LATE_COL BIT_ULL(3) ++#define GMI_TXX_INT_XSDEF BIT_ULL(2) ++#define GMI_TXX_INT_XSCOL BIT_ULL(1) ++#define GMI_TXX_INT_UNDFLW BIT_ULL(0) + + #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ + #define BGX_MSIX_VEC_0_29_CTL 0x400008 +-- +2.7.4 + diff --git a/target/linux/octeontx/patches-5.4/0003-can-mcp251x-convert-to-half-duplex-SPI.patch b/target/linux/octeontx/patches-5.4/0003-can-mcp251x-convert-to-half-duplex-SPI.patch new file mode 100644 index 0000000000..aabf1b9b1e --- /dev/null +++ b/target/linux/octeontx/patches-5.4/0003-can-mcp251x-convert-to-half-duplex-SPI.patch @@ -0,0 +1,51 @@ +From 6edfb172ff1dd3cfc84c19790c245a4005474bb7 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Tue, 25 Feb 2020 12:01:36 -0800 +Subject: [PATCH 03/12] can: mcp251x: convert to half-duplex SPI + +Some SPI host controllers such as the Cavium Thunder do not support +full-duplex SPI. Using half-duplex transfers allows the driver to work +with those host controllers. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +--- + drivers/net/can/spi/mcp251x.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +diff --git a/drivers/net/can/spi/mcp251x.c b/drivers/net/can/spi/mcp251x.c +index 0b0dd3f0..c655b29 100644 +--- a/drivers/net/can/spi/mcp251x.c ++++ b/drivers/net/can/spi/mcp251x.c +@@ -345,8 +345,7 @@ static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) + priv->spi_tx_buf[0] = INSTRUCTION_READ; + priv->spi_tx_buf[1] = reg; + +- mcp251x_spi_trans(spi, 3); +- val = priv->spi_rx_buf[2]; ++ spi_write_then_read(spi, priv->spi_tx_buf, 2, &val, 1); + + return val; + } +@@ -354,15 +353,16 @@ static u8 mcp251x_read_reg(struct spi_device *spi, uint8_t reg) + static void mcp251x_read_2regs(struct spi_device *spi, uint8_t reg, + uint8_t *v1, uint8_t *v2) + { ++ u8 val[4] = {0}; + struct mcp251x_priv *priv = spi_get_drvdata(spi); + + priv->spi_tx_buf[0] = INSTRUCTION_READ; + priv->spi_tx_buf[1] = reg; + +- mcp251x_spi_trans(spi, 4); ++ spi_write_then_read(spi, priv->spi_tx_buf, 2, val, 2); + +- *v1 = priv->spi_rx_buf[2]; +- *v2 = priv->spi_rx_buf[3]; ++ *v1 = val[0]; ++ *v2 = val[1]; + } + + static void mcp251x_write_reg(struct spi_device *spi, u8 reg, uint8_t val) +-- +2.7.4 + diff --git a/target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch b/target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch new file mode 100644 index 0000000000..f7bc97c035 --- /dev/null +++ b/target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch @@ -0,0 +1,64 @@ +From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Wed, 10 Apr 2019 08:00:47 -0700 +Subject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with + GPIO PERST# + +Gateworks boards use PLX PEX860x switches where downstream ports +have their PERST# driven from the PEX GPIO. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +--- + drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++ + 1 file changed, 32 insertions(+) + +diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c +index 419dda6..40e2ddb 100644 +--- a/drivers/pci/quirks.c ++++ b/drivers/pci/quirks.c +@@ -26,6 +26,7 @@ + #include <linux/ktime.h> + #include <linux/mm.h> + #include <linux/nvme.h> ++#include <linux/of.h> + #include <linux/platform_data/x86/apple.h> + #include <linux/pm_runtime.h> + #include <linux/switchtec.h> +@@ -5216,3 +5217,34 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) + DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, + PCI_CLASS_DISPLAY_VGA, 8, + quirk_reset_lenovo_thinkpad_p50_nvgpu); ++ ++#ifdef CONFIG_PCI_HOST_THUNDER_PEM ++/* ++ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High ++ * as they are used for slots1-7 PERST# ++ */ ++static void newport_pciesw_early_fixup(struct pci_dev *dev) ++{ ++ u32 dw; ++ ++ if (!of_machine_is_compatible("gw,newport")) ++ return; ++ ++ if (dev->devfn != 0) ++ return; ++ ++ dev_info(&dev->dev, "de-asserting PERST#\n"); ++ pci_read_config_dword(dev, 0x62c, &dw); ++ dw |= 0xaaa8; /* GPIO1-7 outputs */ ++ pci_write_config_dword(dev, 0x62c, dw); ++ ++ pci_read_config_dword(dev, 0x644, &dw); ++ dw |= 0xfe; /* GPIO1-7 output high */ ++ pci_write_config_dword(dev, 0x644, dw); ++ ++ msleep(100); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup); ++#endif /* CONFIG_PCI_HOST_THUNDER_PEM */ +-- +2.7.4 + |