diff options
Diffstat (limited to 'target/linux/octeontx/patches-5.4/0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch')
| -rw-r--r-- | target/linux/octeontx/patches-5.4/0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch | 150 |
1 files changed, 150 insertions, 0 deletions
diff --git a/target/linux/octeontx/patches-5.4/0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch b/target/linux/octeontx/patches-5.4/0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch new file mode 100644 index 0000000000..597dd9da74 --- /dev/null +++ b/target/linux/octeontx/patches-5.4/0002-net-thunderx-workaround-BGX-TX-Underflow-issue.patch @@ -0,0 +1,150 @@ +From 585ddca487c827178cf697f8bc2e87346061d155 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Wed, 19 Feb 2020 15:19:36 -0800 +Subject: [PATCH 02/12] net: thunderx: workaround BGX TX Underflow issue + +While it is not yet understood why a TX underflow can easily occur +for SGMII interfaces resulting in a TX wedge. It has been found that +disabling/re-enabling the LMAC resolves the issue. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +Reviewed-by: Robert Jones <rjones@gateworks.com> +Signed-off-by: David S. Miller <davem@davemloft.net> +--- + drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 62 +++++++++++++++++++++-- + drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 9 ++++ + 2 files changed, 68 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +index 5f2db9c..ade414a 100644 +--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c ++++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +@@ -413,10 +413,19 @@ void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable) + lmac = &bgx->lmac[lmacid]; + + cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG); +- if (enable) ++ if (enable) { + cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN; +- else ++ ++ /* enable TX FIFO Underflow interrupt */ ++ bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1S, ++ GMI_TXX_INT_UNDFLW); ++ } else { + cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN); ++ ++ /* Disable TX FIFO Underflow interrupt */ ++ bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_INT_ENA_W1C, ++ GMI_TXX_INT_UNDFLW); ++ } + bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg); + + if (bgx->is_rgx) +@@ -1544,6 +1553,48 @@ static int bgx_init_phy(struct bgx *bgx) + return bgx_init_of_phy(bgx); + } + ++static irqreturn_t bgx_intr_handler(int irq, void *data) ++{ ++ struct bgx *bgx = (struct bgx *)data; ++ u64 status, val; ++ int lmac; ++ ++ for (lmac = 0; lmac < bgx->lmac_count; lmac++) { ++ status = bgx_reg_read(bgx, lmac, BGX_GMP_GMI_TXX_INT); ++ if (status & GMI_TXX_INT_UNDFLW) { ++ pci_err(bgx->pdev, "BGX%d lmac%d UNDFLW\n", ++ bgx->bgx_id, lmac); ++ val = bgx_reg_read(bgx, lmac, BGX_CMRX_CFG); ++ val &= ~CMR_EN; ++ bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val); ++ val |= CMR_EN; ++ bgx_reg_write(bgx, lmac, BGX_CMRX_CFG, val); ++ } ++ /* clear interrupts */ ++ bgx_reg_write(bgx, lmac, BGX_GMP_GMI_TXX_INT, status); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static void bgx_register_intr(struct pci_dev *pdev) ++{ ++ struct bgx *bgx = pci_get_drvdata(pdev); ++ int ret; ++ ++ ret = pci_alloc_irq_vectors(pdev, BGX_LMAC_VEC_OFFSET, ++ BGX_LMAC_VEC_OFFSET, PCI_IRQ_ALL_TYPES); ++ if (ret < 0) { ++ pci_err(pdev, "Req for #%d msix vectors failed\n", ++ BGX_LMAC_VEC_OFFSET); ++ return; ++ } ++ ret = pci_request_irq(pdev, GMPX_GMI_TX_INT, bgx_intr_handler, NULL, ++ bgx, "BGX%d", bgx->bgx_id); ++ if (ret) ++ pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx); ++} ++ + static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + { + int err; +@@ -1559,7 +1610,7 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + + pci_set_drvdata(pdev, bgx); + +- err = pci_enable_device(pdev); ++ err = pcim_enable_device(pdev); + if (err) { + dev_err(dev, "Failed to enable PCI device\n"); + pci_set_drvdata(pdev, NULL); +@@ -1613,6 +1664,8 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + + bgx_init_hw(bgx); + ++ bgx_register_intr(pdev); ++ + /* Enable all LMACs */ + for (lmac = 0; lmac < bgx->lmac_count; lmac++) { + err = bgx_lmac_enable(bgx, lmac); +@@ -1629,6 +1682,7 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) + + err_enable: + bgx_vnic[bgx->bgx_id] = NULL; ++ pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx); + err_release_regions: + pci_release_regions(pdev); + err_disable_device: +@@ -1646,6 +1700,8 @@ static void bgx_remove(struct pci_dev *pdev) + for (lmac = 0; lmac < bgx->lmac_count; lmac++) + bgx_lmac_disable(bgx, lmac); + ++ pci_free_irq(pdev, GMPX_GMI_TX_INT, bgx); ++ + bgx_vnic[bgx->bgx_id] = NULL; + pci_release_regions(pdev); + pci_disable_device(pdev); +diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h +index cbdd20b..ac0c89c 100644 +--- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h ++++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h +@@ -183,6 +183,15 @@ + #define BGX_GMP_GMI_TXX_BURST 0x38228 + #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 + #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 ++#define BGX_GMP_GMI_TXX_INT 0x38500 ++#define BGX_GMP_GMI_TXX_INT_W1S 0x38508 ++#define BGX_GMP_GMI_TXX_INT_ENA_W1C 0x38510 ++#define BGX_GMP_GMI_TXX_INT_ENA_W1S 0x38518 ++#define GMI_TXX_INT_PTP_LOST BIT_ULL(4) ++#define GMI_TXX_INT_LATE_COL BIT_ULL(3) ++#define GMI_TXX_INT_XSDEF BIT_ULL(2) ++#define GMI_TXX_INT_XSCOL BIT_ULL(1) ++#define GMI_TXX_INT_UNDFLW BIT_ULL(0) + + #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ + #define BGX_MSIX_VEC_0_29_CTL 0x400008 +-- +2.7.4 + |