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Diffstat (limited to 'target/linux/octeon/patches-3.10/130-gpio.patch')
-rw-r--r--target/linux/octeon/patches-3.10/130-gpio.patch214
1 files changed, 0 insertions, 214 deletions
diff --git a/target/linux/octeon/patches-3.10/130-gpio.patch b/target/linux/octeon/patches-3.10/130-gpio.patch
deleted file mode 100644
index 9312f33f88..0000000000
--- a/target/linux/octeon/patches-3.10/130-gpio.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-Index: linux-3.10.49/drivers/gpio/Kconfig
-===================================================================
---- linux-3.10.49.orig/drivers/gpio/Kconfig 2014-07-18 00:58:15.000000000 +0200
-+++ linux-3.10.49/drivers/gpio/Kconfig 2014-08-07 11:41:16.517169817 +0200
-@@ -171,6 +171,14 @@
- Qualcomm MSM chips. Most of the pins on the MSM can be
- selected for GPIO, and are controlled by this driver.
-
-+config GPIO_OCTEON
-+ tristate "Cavium OCTEON GPIO"
-+ depends on GPIOLIB && CPU_CAVIUM_OCTEON
-+ default y
-+ help
-+ Say yes here to support the on-chip GPIO lines on the OCTEON
-+ family of SOCs.
-+
- config GPIO_MVEBU
- def_bool y
- depends on PLAT_ORION
-Index: linux-3.10.49/drivers/gpio/Makefile
-===================================================================
---- linux-3.10.49.orig/drivers/gpio/Makefile 2014-07-18 00:58:15.000000000 +0200
-+++ linux-3.10.49/drivers/gpio/Makefile 2014-08-07 11:41:16.517169817 +0200
-@@ -10,6 +10,7 @@
- # Device drivers. Generally keep list sorted alphabetically
- obj-$(CONFIG_GPIO_GENERIC) += gpio-generic.o
-
-+obj-$(CONFIG_GPIO_OCTEON) += gpio-octeon.o
- obj-$(CONFIG_GPIO_74X164) += gpio-74x164.o
- obj-$(CONFIG_GPIO_ADNP) += gpio-adnp.o
- obj-$(CONFIG_GPIO_ADP5520) += gpio-adp5520.o
-Index: linux-3.10.49/drivers/gpio/gpio-octeon.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ linux-3.10.49/drivers/gpio/gpio-octeon.c 2014-08-07 11:53:14.733161106 +0200
-@@ -0,0 +1,166 @@
-+/*
-+ * This file is subject to the terms and conditions of the GNU General Public
-+ * License. See the file "COPYING" in the main directory of this archive
-+ * for more details.
-+ *
-+ * Copyright (C) 2011,2012 Cavium Inc.
-+ */
-+
-+#include <linux/platform_device.h>
-+#include <linux/kernel.h>
-+#include <linux/module.h>
-+#include <linux/gpio.h>
-+#include <linux/io.h>
-+
-+#include <asm/octeon/octeon.h>
-+#include <asm/octeon/cvmx-gpio-defs.h>
-+
-+#define DRV_VERSION "1.0"
-+#define DRV_DESCRIPTION "Cavium Inc. OCTEON GPIO Driver"
-+
-+#define RX_DAT 0x80
-+#define TX_SET 0x88
-+#define TX_CLEAR 0x90
-+
-+int gpio_to_irq(unsigned gpio)
-+{
-+ return -EINVAL;
-+}
-+EXPORT_SYMBOL(gpio_to_irq);
-+
-+/*
-+ * The address offset of the GPIO configuration register for a given
-+ * line.
-+ */
-+static unsigned int bit_cfg_reg(unsigned int gpio)
-+{
-+ if (gpio < 16)
-+ return 8 * gpio;
-+ else
-+ return 8 * (gpio - 16) + 0x100;
-+}
-+
-+struct octeon_gpio {
-+ struct gpio_chip chip;
-+ u64 register_base;
-+};
-+
-+static int octeon_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
-+
-+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), 0);
-+ return 0;
-+}
-+
-+static void octeon_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-+{
-+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
-+ u64 mask = 1ull << offset;
-+ u64 reg = gpio->register_base + (value ? TX_SET : TX_CLEAR);
-+ cvmx_write_csr(reg, mask);
-+}
-+
-+static int octeon_gpio_dir_out(struct gpio_chip *chip, unsigned offset,
-+ int value)
-+{
-+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
-+ union cvmx_gpio_bit_cfgx cfgx;
-+
-+
-+ octeon_gpio_set(chip, offset, value);
-+
-+ cfgx.u64 = 0;
-+ cfgx.s.tx_oe = 1;
-+
-+ cvmx_write_csr(gpio->register_base + bit_cfg_reg(offset), cfgx.u64);
-+ return 0;
-+}
-+
-+static int octeon_gpio_get(struct gpio_chip *chip, unsigned offset)
-+{
-+ struct octeon_gpio *gpio = container_of(chip, struct octeon_gpio, chip);
-+ u64 read_bits = cvmx_read_csr(gpio->register_base + RX_DAT);
-+
-+ return ((1ull << offset) & read_bits) != 0;
-+}
-+
-+static int octeon_gpio_probe(struct platform_device *pdev)
-+{
-+ struct octeon_gpio *gpio;
-+ struct gpio_chip *chip;
-+ struct resource *res_mem;
-+ int err = 0;
-+
-+ gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
-+ if (!gpio)
-+ return -ENOMEM;
-+ chip = &gpio->chip;
-+
-+ res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (res_mem == NULL) {
-+ dev_err(&pdev->dev, "found no memory resource\n");
-+ err = -ENXIO;
-+ goto out;
-+ }
-+ if (!devm_request_mem_region(&pdev->dev, res_mem->start,
-+ resource_size(res_mem),
-+ res_mem->name)) {
-+ dev_err(&pdev->dev, "request_mem_region failed\n");
-+ err = -ENXIO;
-+ goto out;
-+ }
-+ gpio->register_base = (u64)devm_ioremap(&pdev->dev, res_mem->start,
-+ resource_size(res_mem));
-+
-+
-+ pdev->dev.platform_data = chip;
-+ chip->label = "octeon-gpio";
-+ chip->dev = &pdev->dev;
-+ chip->owner = THIS_MODULE;
-+ chip->base = 0;
-+ chip->can_sleep = 0;
-+ chip->ngpio = 20;
-+ chip->direction_input = octeon_gpio_dir_in;
-+ chip->get = octeon_gpio_get;
-+ chip->direction_output = octeon_gpio_dir_out;
-+ chip->set = octeon_gpio_set;
-+ err = gpiochip_add(chip);
-+ if (err)
-+ goto out;
-+
-+ dev_info(&pdev->dev, "version: " DRV_VERSION "\n");
-+out:
-+ return err;
-+}
-+
-+static int octeon_gpio_remove(struct platform_device *pdev)
-+{
-+ struct gpio_chip *chip = pdev->dev.platform_data;
-+ return gpiochip_remove(chip);
-+}
-+
-+static struct of_device_id octeon_gpio_match[] = {
-+ {
-+ .compatible = "cavium,octeon-3860-gpio",
-+ },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, octeon_gpio_match);
-+
-+static struct platform_driver octeon_gpio_driver = {
-+ .probe = octeon_gpio_probe,
-+ .remove = octeon_gpio_remove,
-+ .driver = {
-+ .name = "octeon_gpio",
-+ .owner = THIS_MODULE,
-+ .of_match_table = octeon_gpio_match,
-+ },
-+};
-+
-+module_platform_driver(octeon_gpio_driver);
-+
-+MODULE_DESCRIPTION(DRV_DESCRIPTION);
-+MODULE_AUTHOR("David Daney");
-+MODULE_LICENSE("GPL");
-+MODULE_VERSION(DRV_VERSION);
-Index: linux-3.10.49/arch/mips/Kconfig
-===================================================================
---- linux-3.10.49.orig/arch/mips/Kconfig 2014-08-07 11:41:14.809169838 +0200
-+++ linux-3.10.49/arch/mips/Kconfig 2014-08-07 11:41:16.521169817 +0200
-@@ -769,6 +769,7 @@
- select USB_ARCH_HAS_OHCI
- select USB_ARCH_HAS_EHCI
- select HOLES_IN_ZONE
-+ select ARCH_REQUIRE_GPIOLIB
- help
- This option supports all of the Octeon reference boards from Cavium
- Networks. It builds a kernel that dynamically determines the Octeon