diff options
Diffstat (limited to 'target/linux/mvebu')
8 files changed, 10 insertions, 544 deletions
diff --git a/target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch b/target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch deleted file mode 100644 index ca10ecf6b2..0000000000 --- a/target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch +++ /dev/null @@ -1,50 +0,0 @@ -From f4c7d053d7f77cd5c1a1ba7c7ce085ddba13d1d7 Mon Sep 17 00:00:00 2001 -From: Remi Pommarel <repk@triplefau.lt> -Date: Wed, 22 May 2019 23:33:50 +0200 -Subject: [PATCH] PCI: aardvark: Wait for endpoint to be ready before training - link - -When configuring pcie reset pin from gpio (e.g. initially set by -u-boot) to pcie function this pin goes low for a brief moment -asserting the PERST# signal. Thus connected device enters fundamental -reset process and link configuration can only begin after a minimal -100ms delay (see [1]). - -Because the pin configuration comes from the "default" pinctrl it is -implicitly configured before the probe callback is called: - -driver_probe_device() - really_probe() - ... - pinctrl_bind_pins() /* Here pin goes from gpio to PCIE reset - function and PERST# is asserted */ - ... - drv->probe() - -[1] "PCI Express Base Specification", REV. 4.0 - PCI Express, February 19 2014, 6.6.1 Conventional Reset - -Signed-off-by: Remi Pommarel <repk@triplefau.lt> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> ---- - drivers/pci/controller/pci-aardvark.c | 8 ++++++++ - 1 file changed, 8 insertions(+) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -353,6 +353,14 @@ static void advk_pcie_setup_hw(struct ad - reg |= PIO_CTRL_ADDR_WIN_DISABLE; - advk_writel(pcie, reg, PIO_CTRL); - -+ /* -+ * PERST# signal could have been asserted by pinctrl subsystem before -+ * probe() callback has been called, making the endpoint going into -+ * fundamental reset. As required by PCI Express spec a delay for at -+ * least 100ms after such a reset before link training is needed. -+ */ -+ msleep(PCI_PM_D3COLD_WAIT); -+ - /* Start link training */ - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); - reg |= PCIE_CORE_LINK_TRAINING; diff --git a/target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch b/target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch deleted file mode 100644 index d1bfd70d30..0000000000 --- a/target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch +++ /dev/null @@ -1,60 +0,0 @@ -From 6964494582f56a3882c2c53b0edbfe99eb32b2e1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> -Date: Thu, 30 Apr 2020 10:06:14 +0200 -Subject: [PATCH] PCI: aardvark: Train link immediately after enabling training -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Adding even 100ms (PCI_PM_D3COLD_WAIT) delay between enabling link -training and starting link training causes detection issues with some -buggy cards (such as Compex WLE900VX). - -Move the code which enables link training immediately before the one -which starts link traning. - -This fixes detection issues of Compex WLE900VX card on Turris MOX after -cold boot. - -Link: https://lore.kernel.org/r/20200430080625.26070-2-pali@kernel.org -Fixes: f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready...") -Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> -Signed-off-by: Pali Rohár <pali@kernel.org> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Acked-by: Rob Herring <robh@kernel.org> -Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> ---- - drivers/pci/controller/pci-aardvark.c | 15 +++++++++------ - 1 file changed, 9 insertions(+), 6 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -315,11 +315,6 @@ static void advk_pcie_setup_hw(struct ad - reg |= LANE_COUNT_1; - advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); - -- /* Enable link training */ -- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -- reg |= LINK_TRAINING_EN; -- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); -- - /* Enable MSI */ - reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); - reg |= PCIE_CORE_CTRL2_MSI_ENABLE; -@@ -361,7 +356,15 @@ static void advk_pcie_setup_hw(struct ad - */ - msleep(PCI_PM_D3COLD_WAIT); - -- /* Start link training */ -+ /* Enable link training */ -+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -+ reg |= LINK_TRAINING_EN; -+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); -+ -+ /* -+ * Start link training immediately after enabling it. -+ * This solves problems for some buggy cards. -+ */ - reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); - reg |= PCIE_CORE_LINK_TRAINING; - advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); diff --git a/target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch b/target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch deleted file mode 100644 index 85ae9cabe2..0000000000 --- a/target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch +++ /dev/null @@ -1,208 +0,0 @@ -From 43fc679ced18006b12d918d7a8a4af392b7fbfe7 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz> -Date: Thu, 30 Apr 2020 10:06:17 +0200 -Subject: [PATCH] PCI: aardvark: Improve link training -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Currently the aardvark driver trains link in PCIe gen2 mode. This may -cause some buggy gen1 cards (such as Compex WLE900VX) to be unstable or -even not detected. Moreover when ASPM code tries to retrain link second -time, these cards may stop responding and link goes down. If gen1 is -used this does not happen. - -Unconditionally forcing gen1 is not a good solution since it may have -performance impact on gen2 cards. - -To overcome this, read 'max-link-speed' property (as defined in PCI -device tree bindings) and use this as max gen mode. Then iteratively try -link training at this mode or lower until successful. After successful -link training choose final controller gen based on Negotiated Link Speed -from Link Status register, which should match card speed. - -Link: https://lore.kernel.org/r/20200430080625.26070-5-pali@kernel.org -Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> -Signed-off-by: Pali Rohár <pali@kernel.org> -Signed-off-by: Marek Behún <marek.behun@nic.cz> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> ---- - drivers/pci/controller/pci-aardvark.c | 114 ++++++++++++++++++++------ - 1 file changed, 89 insertions(+), 25 deletions(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -39,6 +39,7 @@ - #define PCIE_CORE_LINK_CTRL_STAT_REG 0xd0 - #define PCIE_CORE_LINK_L0S_ENTRY BIT(0) - #define PCIE_CORE_LINK_TRAINING BIT(5) -+#define PCIE_CORE_LINK_SPEED_SHIFT 16 - #define PCIE_CORE_LINK_WIDTH_SHIFT 20 - #define PCIE_CORE_ERR_CAPCTL_REG 0x118 - #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) -@@ -206,6 +207,7 @@ struct advk_pcie { - struct mutex msi_used_lock; - u16 msi_msg; - int root_bus_nr; -+ int link_gen; - struct pci_bridge_emul bridge; - }; - -@@ -230,20 +232,16 @@ static int advk_pcie_link_up(struct advk - - static int advk_pcie_wait_for_link(struct advk_pcie *pcie) - { -- struct device *dev = &pcie->pdev->dev; - int retries; - - /* check if the link is up or not */ - for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { -- if (advk_pcie_link_up(pcie)) { -- dev_info(dev, "link up\n"); -+ if (advk_pcie_link_up(pcie)) - return 0; -- } - - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); - } - -- dev_err(dev, "link never came up\n"); - return -ETIMEDOUT; - } - -@@ -258,6 +256,85 @@ static void advk_pcie_wait_for_retrain(s - } - } - -+static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen) -+{ -+ int ret, neg_gen; -+ u32 reg; -+ -+ /* Setup link speed */ -+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -+ reg &= ~PCIE_GEN_SEL_MSK; -+ if (gen == 3) -+ reg |= SPEED_GEN_3; -+ else if (gen == 2) -+ reg |= SPEED_GEN_2; -+ else -+ reg |= SPEED_GEN_1; -+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); -+ -+ /* -+ * Enable link training. This is not needed in every call to this -+ * function, just once suffices, but it does not break anything either. -+ */ -+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -+ reg |= LINK_TRAINING_EN; -+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); -+ -+ /* -+ * Start link training immediately after enabling it. -+ * This solves problems for some buggy cards. -+ */ -+ reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); -+ reg |= PCIE_CORE_LINK_TRAINING; -+ advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); -+ -+ ret = advk_pcie_wait_for_link(pcie); -+ if (ret) -+ return ret; -+ -+ reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); -+ neg_gen = (reg >> PCIE_CORE_LINK_SPEED_SHIFT) & 0xf; -+ -+ return neg_gen; -+} -+ -+static void advk_pcie_train_link(struct advk_pcie *pcie) -+{ -+ struct device *dev = &pcie->pdev->dev; -+ int neg_gen = -1, gen; -+ -+ /* -+ * Try link training at link gen specified by device tree property -+ * 'max-link-speed'. If this fails, iteratively train at lower gen. -+ */ -+ for (gen = pcie->link_gen; gen > 0; --gen) { -+ neg_gen = advk_pcie_train_at_gen(pcie, gen); -+ if (neg_gen > 0) -+ break; -+ } -+ -+ if (neg_gen < 0) -+ goto err; -+ -+ /* -+ * After successful training if negotiated gen is lower than requested, -+ * train again on negotiated gen. This solves some stability issues for -+ * some buggy gen1 cards. -+ */ -+ if (neg_gen < gen) { -+ gen = neg_gen; -+ neg_gen = advk_pcie_train_at_gen(pcie, gen); -+ } -+ -+ if (neg_gen == gen) { -+ dev_info(dev, "link up at gen %i\n", gen); -+ return; -+ } -+ -+err: -+ dev_err(dev, "link never came up\n"); -+} -+ - static void advk_pcie_setup_hw(struct advk_pcie *pcie) - { - u32 reg; -@@ -303,12 +380,6 @@ static void advk_pcie_setup_hw(struct ad - PCIE_CORE_CTRL2_TD_ENABLE; - advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); - -- /* Set GEN2 */ -- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -- reg &= ~PCIE_GEN_SEL_MSK; -- reg |= SPEED_GEN_2; -- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); -- - /* Set lane X1 */ - reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); - reg &= ~LANE_CNT_MSK; -@@ -356,20 +427,7 @@ static void advk_pcie_setup_hw(struct ad - */ - msleep(PCI_PM_D3COLD_WAIT); - -- /* Enable link training */ -- reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -- reg |= LINK_TRAINING_EN; -- advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); -- -- /* -- * Start link training immediately after enabling it. -- * This solves problems for some buggy cards. -- */ -- reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); -- reg |= PCIE_CORE_LINK_TRAINING; -- advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); -- -- advk_pcie_wait_for_link(pcie); -+ advk_pcie_train_link(pcie); - - reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); - reg |= PCIE_CORE_CMD_MEM_ACCESS_EN | -@@ -1193,6 +1251,12 @@ static int advk_pcie_probe(struct platfo - return ret; - } - -+ ret = of_pci_get_max_link_speed(dev->of_node); -+ if (ret <= 0 || ret > 3) -+ pcie->link_gen = 3; -+ else -+ pcie->link_gen = ret; -+ - advk_pcie_setup_hw(pcie); - - ret = advk_sw_pci_bridge_init(pcie); diff --git a/target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch b/target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch deleted file mode 100644 index 7db1c3efa5..0000000000 --- a/target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch +++ /dev/null @@ -1,123 +0,0 @@ -From 5169a9851daaa2782a7bd2bb83d5b1bd224b2879 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org> -Date: Thu, 30 Apr 2020 10:06:18 +0200 -Subject: [PATCH] PCI: aardvark: Issue PERST via GPIO -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add support for issuing PERST via GPIO specified in 'reset-gpios' -property (as described in PCI device tree bindings). - -Some buggy cards (e.g. Compex WLE900VX or WLE1216) are not detected -after reboot when PERST is not issued during driver initialization. - -If bootloader already enabled link training then issuing PERST has no -effect for some buggy cards (e.g. Compex WLE900VX) and these cards are -not detected. We therefore clear the LINK_TRAINING_EN register before. - -It was observed that Compex WLE900VX card needs to be in PERST reset -for at least 10ms if bootloader enabled link training. - -Tested on Turris MOX. - -Link: https://lore.kernel.org/r/20200430080625.26070-6-pali@kernel.org -Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> -Signed-off-by: Pali Rohár <pali@kernel.org> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> ---- - drivers/pci/controller/pci-aardvark.c | 43 ++++++++++++++++++++++++++- - 1 file changed, 42 insertions(+), 1 deletion(-) - ---- a/drivers/pci/controller/pci-aardvark.c -+++ b/drivers/pci/controller/pci-aardvark.c -@@ -9,6 +9,7 @@ - */ - - #include <linux/delay.h> -+#include <linux/gpio.h> - #include <linux/interrupt.h> - #include <linux/irq.h> - #include <linux/irqdomain.h> -@@ -17,6 +18,7 @@ - #include <linux/init.h> - #include <linux/platform_device.h> - #include <linux/of_address.h> -+#include <linux/of_gpio.h> - #include <linux/of_pci.h> - - #include "../pci.h" -@@ -209,6 +211,7 @@ struct advk_pcie { - int root_bus_nr; - int link_gen; - struct pci_bridge_emul bridge; -+ struct gpio_desc *reset_gpio; - }; - - static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) -@@ -335,10 +338,31 @@ err: - dev_err(dev, "link never came up\n"); - } - -+static void advk_pcie_issue_perst(struct advk_pcie *pcie) -+{ -+ u32 reg; -+ -+ if (!pcie->reset_gpio) -+ return; -+ -+ /* PERST does not work for some cards when link training is enabled */ -+ reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); -+ reg &= ~LINK_TRAINING_EN; -+ advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); -+ -+ /* 10ms delay is needed for some cards */ -+ dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); -+ gpiod_set_value_cansleep(pcie->reset_gpio, 1); -+ usleep_range(10000, 11000); -+ gpiod_set_value_cansleep(pcie->reset_gpio, 0); -+} -+ - static void advk_pcie_setup_hw(struct advk_pcie *pcie) - { - u32 reg; - -+ advk_pcie_issue_perst(pcie); -+ - /* Set to Direct mode */ - reg = advk_readl(pcie, CTRL_CONFIG_REG); - reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); -@@ -421,7 +445,8 @@ static void advk_pcie_setup_hw(struct ad - - /* - * PERST# signal could have been asserted by pinctrl subsystem before -- * probe() callback has been called, making the endpoint going into -+ * probe() callback has been called or issued explicitly by reset gpio -+ * function advk_pcie_issue_perst(), making the endpoint going into - * fundamental reset. As required by PCI Express spec a delay for at - * least 100ms after such a reset before link training is needed. - */ -@@ -1251,6 +1276,22 @@ static int advk_pcie_probe(struct platfo - return ret; - } - -+ pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, -+ "reset-gpios", 0, -+ GPIOD_OUT_LOW, -+ "pcie1-reset"); -+ ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); -+ if (ret) { -+ if (ret == -ENOENT) { -+ pcie->reset_gpio = NULL; -+ } else { -+ if (ret != -EPROBE_DEFER) -+ dev_err(dev, "Failed to get reset-gpio: %i\n", -+ ret); -+ return ret; -+ } -+ } -+ - ret = of_pci_get_max_link_speed(dev->of_node); - if (ret <= 0 || ret > 3) - pcie->link_gen = 3; diff --git a/target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch b/target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch index 0c8357d717..525d9ec794 100644 --- a/target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch +++ b/target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch @@ -47,7 +47,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com> #include <linux/platform_device.h> #include <linux/of_address.h> #include <linux/of_gpio.h> -@@ -104,6 +105,8 @@ +@@ -90,6 +91,8 @@ #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5) #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6) #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10) @@ -56,7 +56,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com> #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30) #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40) #define PCIE_MSG_PM_PME_MASK BIT(7) -@@ -212,6 +215,7 @@ struct advk_pcie { +@@ -288,6 +291,7 @@ struct advk_pcie { int link_gen; struct pci_bridge_emul bridge; struct gpio_desc *reset_gpio; @@ -64,9 +64,9 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com> }; static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) -@@ -363,6 +367,11 @@ static void advk_pcie_setup_hw(struct ad - - advk_pcie_issue_perst(pcie); +@@ -481,6 +485,11 @@ static void advk_pcie_setup_hw(struct ad + u32 reg; + int i; + /* Enable TX */ + reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); @@ -76,7 +76,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com> /* Set to Direct mode */ reg = advk_readl(pcie, CTRL_CONFIG_REG); reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT); -@@ -1241,6 +1250,62 @@ out_release_res: +@@ -1493,6 +1502,62 @@ out_release_res: return err; } @@ -139,7 +139,7 @@ Cc: Miquèl Raynal <miquel.raynal@bootlin.com> static int advk_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; -@@ -1298,6 +1363,10 @@ static int advk_pcie_probe(struct platfo +@@ -1625,6 +1690,10 @@ static int advk_pcie_probe(struct platfo else pcie->link_gen = ret; diff --git a/target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch b/target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch deleted file mode 100644 index dd75470b4d..0000000000 --- a/target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch +++ /dev/null @@ -1,93 +0,0 @@ -From 715878016984b2617f6c1f177c50039e12e7bd5b Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Marek=20Beh=C3=BAn?= <marek.behun@nic.cz> -Date: Thu, 30 Apr 2020 10:06:23 +0200 -Subject: [PATCH] arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio - function -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -We found out that we are unable to control the PERST# signal via the -default pin dedicated to be PERST# pin (GPIO2[3] pin) on A3700 SOC when -this pin is in EP_PCIE1_Resetn mode. There is a register in the PCIe -register space called PERSTN_GPIO_EN (D0088004[3]), but changing the -value of this register does not change the pin output when measuring -with voltmeter. - -We do not know if this is a bug in the SOC, or if it works only when -PCIe controller is in a certain state. - -Commit f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready -before training link") says that when this pin changes pinctrl mode -from EP_PCIE1_Resetn to GPIO, the PERST# signal is asserted for a brief -moment. - -So currently the situation is that on A3700 boards the PERST# signal is -asserted in U-Boot (because the code in U-Boot issues reset via this pin -via GPIO mode), and then in Linux by the obscure and undocumented -mechanism described by the above mentioned commit. - -We want to issue PERST# signal in a known way, therefore this patch -changes the pcie_reset_pin function from "pcie" to "gpio" and adds the -reset-gpios property to the PCIe node in device tree files of -EspressoBin and Armada 3720 Dev Board (Turris Mox device tree already -has this property and uDPU does not have a PCIe port). - -Signed-off-by: Marek Behún <marek.behun@nic.cz> -Cc: Remi Pommarel <repk@triplefau.lt> -Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> -Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> -Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> ---- - arch/arm64/boot/dts/marvell/armada-3720-db.dts | 3 +++ - arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 1 + - arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 4 ---- - arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- - 4 files changed, 5 insertions(+), 5 deletions(-) - ---- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts -@@ -128,6 +128,9 @@ - - /* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ - &pcie0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; -+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - status = "okay"; - }; - ---- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts -@@ -59,6 +59,7 @@ - phys = <&comphy1 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; -+ reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; - }; - - /* J6 */ ---- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts -+++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts -@@ -127,10 +127,6 @@ - }; - }; - --&pcie_reset_pins { -- function = "gpio"; --}; -- - &pcie0 { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; ---- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi -@@ -318,7 +318,7 @@ - - pcie_reset_pins: pcie-reset-pins { - groups = "pcie1"; -- function = "pcie"; -+ function = "gpio"; - }; - - pcie_clkreq_pins: pcie-clkreq-pins { diff --git a/target/linux/mvebu/patches-5.4/024-PCI-aardvark-Don-t-touch-PCIe-registers-if-no-card-c.patch b/target/linux/mvebu/patches-5.4/024-PCI-aardvark-Don-t-touch-PCIe-registers-if-no-card-c.patch index f38b6b56bb..7a8c50634f 100644 --- a/target/linux/mvebu/patches-5.4/024-PCI-aardvark-Don-t-touch-PCIe-registers-if-no-card-c.patch +++ b/target/linux/mvebu/patches-5.4/024-PCI-aardvark-Don-t-touch-PCIe-registers-if-no-card-c.patch @@ -34,8 +34,8 @@ Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c -@@ -725,6 +725,13 @@ static bool advk_pcie_valid_device(struc - if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0) +@@ -976,6 +976,13 @@ static bool advk_pcie_valid_device(struc + if (bus->number != pcie->root_bus_nr && !advk_pcie_link_up(pcie)) return false; + /* diff --git a/target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch b/target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch index 117f9b3576..bcf63ab8ec 100644 --- a/target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch +++ b/target/linux/mvebu/patches-5.4/026-PCI-aardvark-Fix-initialization-with-old-Marvell-s-A.patch @@ -31,7 +31,7 @@ Cc: <stable@vger.kernel.org> # 5.8+: ea17a0f153af: phy: marvell: comphy: Convert --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c -@@ -1281,7 +1281,9 @@ static int advk_pcie_enable_phy(struct a +@@ -1533,7 +1533,9 @@ static int advk_pcie_enable_phy(struct a } ret = phy_power_on(pcie->phy); |