diff options
Diffstat (limited to 'target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch')
| -rw-r--r-- | target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch b/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch deleted file mode 100644 index 0f4d14188d..0000000000 --- a/target/linux/mvebu/patches-5.4/000-v5.5-arm64-dts-marvell-Add-support-for-Marvell-CN9130-SoC.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 6b8970bd8d7a17a648e31f3996d9b21336b4a2cf Mon Sep 17 00:00:00 2001 -From: Miquel Raynal <miquel.raynal@bootlin.com> -Date: Fri, 4 Oct 2019 16:27:35 +0200 -Subject: [PATCH] arm64: dts: marvell: Add support for Marvell CN9130 SoC - support - -A CN9130 SoC has one AP807 and one internal CP115. - -Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> -Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> ---- - arch/arm64/boot/dts/marvell/cn9130.dtsi | 37 +++++++++++++++++++++++++ - 1 file changed, 37 insertions(+) - create mode 100644 arch/arm64/boot/dts/marvell/cn9130.dtsi - ---- /dev/null -+++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi -@@ -0,0 +1,37 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (C) 2019 Marvell International Ltd. -+ * -+ * Device tree for the CN9130 SoC. -+ */ -+ -+#include "armada-ap807-quad.dtsi" -+ -+/ { -+ model = "Marvell Armada CN9130 SoC"; -+ compatible = "marvell,cn9130", "marvell,armada-ap807-quad", -+ "marvell,armada-ap807"; -+}; -+ -+/* -+ * Instantiate the internal CP115 -+ */ -+ -+#define CP11X_NAME cp0 -+#define CP11X_BASE f2000000 -+#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \ -+ 0xe0000000 + ((iface - 1) * 0x1000000)) -+#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000) -+#define CP11X_PCIE0_BASE f2600000 -+#define CP11X_PCIE1_BASE f2620000 -+#define CP11X_PCIE2_BASE f2640000 -+ -+#include "armada-cp115.dtsi" -+ -+#undef CP11X_NAME -+#undef CP11X_BASE -+#undef CP11X_PCIEx_MEM_BASE -+#undef CP11X_PCIEx_MEM_SIZE -+#undef CP11X_PCIE0_BASE -+#undef CP11X_PCIE1_BASE -+#undef CP11X_PCIE2_BASE |