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-rw-r--r--target/linux/mvebu/patches-4.9/472-armada-solidrun-microsom-backport-improvements.patch185
1 files changed, 185 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-4.9/472-armada-solidrun-microsom-backport-improvements.patch b/target/linux/mvebu/patches-4.9/472-armada-solidrun-microsom-backport-improvements.patch
new file mode 100644
index 0000000000..9195d4e793
--- /dev/null
+++ b/target/linux/mvebu/patches-4.9/472-armada-solidrun-microsom-backport-improvements.patch
@@ -0,0 +1,185 @@
+From fc5783a00be9251196091be6b9cdd54fe196630b Mon Sep 17 00:00:00 2001
+From: Marko Ratkaj <marko.ratkaj@sartura.hr>
+Date: Fri, 7 Apr 2017 11:24:19 +0200
+Subject: [PATCH] armada-38x-solidrun-microsom backport improvements from
+ upstream
+
+Signed-off-by: Marko Ratkaj <marko.ratkaj@sartura.hr>
+---
+ .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 130 ++++++++++++---------
+ 1 file changed, 74 insertions(+), 56 deletions(-)
+
+--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
++++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+@@ -17,17 +17,17 @@
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+- * This file is distributed in the hope that it will be useful
++ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+- * Or, alternatively
++ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+- * restriction, including without limitation the rights to use
++ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+@@ -36,11 +36,11 @@
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+@@ -62,45 +62,6 @@
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ internal-regs {
+- ethernet@70000 {
+- pinctrl-0 = <&ge0_rgmii_pins>;
+- pinctrl-names = "default";
+- phy = <&phy_dedicated>;
+- phy-mode = "rgmii-id";
+- buffer-manager = <&bm>;
+- bm,pool-long = <0>;
+- bm,pool-short = <1>;
+- status = "okay";
+- };
+-
+- mdio@72004 {
+- /*
+- * Add the phy clock here, so the phy can be
+- * accessed to read its IDs prior to binding
+- * with the driver.
+- */
+- pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
+- pinctrl-names = "default";
+-
+- phy_dedicated: ethernet-phy@0 {
+- /*
+- * Annoyingly, the marvell phy driver
+- * configures the LED register, rather
+- * than preserving reset-loaded setting.
+- * We undo that rubbish here.
+- */
+- marvell,reg-init = <3 16 0 0x101e>;
+- reg = <0>;
+- };
+- };
+-
+- pinctrl@18000 {
+- microsom_phy_clk_pins: microsom-phy-clk-pins {
+- marvell,pins = "mpp45";
+- marvell,function = "ref";
+- };
+- };
+-
+ rtc@a3800 {
+ /*
+ * If the rtc doesn't work, run "date reset"
+@@ -108,21 +69,78 @@
+ */
+ status = "okay";
+ };
++ };
++ };
++};
+
+- serial@12000 {
+- pinctrl-0 = <&uart0_pins>;
+- pinctrl-names = "default";
+- status = "okay";
+- };
++&bm {
++ status = "okay";
++};
+
+- bm@c8000 {
+- status = "okay";
+- };
+- };
++&bm_bppi {
++ status = "okay";
++};
+
+- bm-bppi {
+- status = "okay";
+- };
++&eth0 {
++ /* ethernet@70000 */
++ pinctrl-0 = <&ge0_rgmii_pins>;
++ pinctrl-names = "default";
++ phy = <&phy_dedicated>;
++ phy-mode = "rgmii-id";
++ buffer-manager = <&bm>;
++ bm,pool-long = <0>;
++ bm,pool-short = <1>;
++ status = "okay";
++};
+
++&mdio {
++ /*
++ * Add the phy clock here, so the phy can be accessed to read its
++ * IDs prior to binding with the driver.
++ */
++ pinctrl-0 = <&mdio_pins &microsom_phy_clk_pins>;
++ pinctrl-names = "default";
++
++ phy_dedicated: ethernet-phy@0 {
++ /*
++ * Annoyingly, the marvell phy driver configures the LED
++ * register, rather than preserving reset-loaded setting.
++ * We undo that rubbish here.
++ */
++ marvell,reg-init = <3 16 0 0x101e>;
++ reg = <0>;
+ };
+ };
++
++&pinctrl {
++ microsom_phy_clk_pins: microsom-phy-clk-pins {
++ marvell,pins = "mpp45";
++ marvell,function = "ref";
++ };
++ /* Optional eMMC */
++ microsom_sdhci_pins: microsom-sdhci-pins {
++ marvell,pins = "mpp21", "mpp28", "mpp37",
++ "mpp38", "mpp39", "mpp40";
++ marvell,function = "sd0";
++ };
++};
++
++&spi1 {
++ /* The microsom has an optional W25Q32 on board, connected to CS0 */
++ pinctrl-0 = <&spi1_pins>;
++
++ w25q32: spi-flash@0 {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ compatible = "w25q32", "jedec,spi-nor";
++ reg = <0>; /* Chip select 0 */
++ spi-max-frequency = <3000000>;
++ status = "disabled";
++ };
++};
++
++&uart0 {
++ pinctrl-0 = <&uart0_pins>;
++ pinctrl-names = "default";
++ status = "okay";
++};