diff options
Diffstat (limited to 'target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch')
| -rw-r--r-- | target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch b/target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch deleted file mode 100644 index 4b319e26a7..0000000000 --- a/target/linux/mvebu/patches-4.4/049-net-mvneta-replace-MVNETA_CPU_D_CACHE_LINE_SIZE-with.patch +++ /dev/null @@ -1,56 +0,0 @@ -From: Jisheng Zhang <jszhang@marvell.com> -Date: Wed, 30 Mar 2016 19:55:21 +0800 -Subject: [PATCH] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with - L1_CACHE_BYTES - -The mvneta is also used in some Marvell berlin family SoCs which may -have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE -usage with L1_CACHE_BYTES. - -And since dma_alloc_coherent() is always cacheline size aligned, so -remove the align checks. - -Signed-off-by: Jisheng Zhang <jszhang@marvell.com> -Signed-off-by: David S. Miller <davem@davemloft.net> ---- - ---- a/drivers/net/ethernet/marvell/mvneta.c -+++ b/drivers/net/ethernet/marvell/mvneta.c -@@ -260,7 +260,6 @@ - - #define MVNETA_VLAN_TAG_LEN 4 - --#define MVNETA_CPU_D_CACHE_LINE_SIZE 32 - #define MVNETA_TX_CSUM_DEF_SIZE 1600 - #define MVNETA_TX_CSUM_MAX_SIZE 9800 - #define MVNETA_ACC_MODE_EXT1 1 -@@ -300,7 +299,7 @@ - #define MVNETA_RX_PKT_SIZE(mtu) \ - ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ - ETH_HLEN + ETH_FCS_LEN, \ -- MVNETA_CPU_D_CACHE_LINE_SIZE) -+ L1_CACHE_BYTES) - - #define IS_TSO_HEADER(txq, addr) \ - ((addr >= txq->tso_hdrs_phys) && \ -@@ -2766,9 +2765,6 @@ static int mvneta_rxq_init(struct mvneta - if (rxq->descs == NULL) - return -ENOMEM; - -- BUG_ON(rxq->descs != -- PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); -- - rxq->last_desc = rxq->size - 1; - - /* Set Rx descriptors queue starting address */ -@@ -2839,10 +2835,6 @@ static int mvneta_txq_init(struct mvneta - if (txq->descs == NULL) - return -ENOMEM; - -- /* Make sure descriptor address is cache line size aligned */ -- BUG_ON(txq->descs != -- PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); -- - txq->last_desc = txq->size - 1; - - /* Set maximum bandwidth for enabled TXQs */ |