diff options
Diffstat (limited to 'target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch')
| -rw-r--r-- | target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch b/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch new file mode 100644 index 0000000000..7dbcf2fcda --- /dev/null +++ b/target/linux/mediatek/patches-5.15/120-10-v5.18-mtd-nand-fix-ecc-parameters-for-mt7622.patch @@ -0,0 +1,93 @@ +From 41825166744c6e5664281611f5e6d9a2e9333c2b Mon Sep 17 00:00:00 2001 +From: Chuanhong Guo <gch981213@gmail.com> +Date: Sat, 2 Apr 2022 22:31:20 +0800 +Subject: [PATCH 10/15] mtd: nand: fix ecc parameters for mt7622 + +According to the datasheet, mt7622 only has 5 ECC capabilities instead +of 7, and the decoding error register is arranged as follows: ++------+---------+---------+---------+---------+ +| Bits | 19:15 | 14:10 | 9:5 | 4:0 | ++------+---------+---------+---------+---------+ +| Name | ERRNUM3 | ERRNUM2 | ERRNUM1 | ERRNUM0 | ++------+---------+---------+---------+---------+ +This means err_mask should be 0x1f instead of 0x3f and the number of +bits shifted in mtk_ecc_get_stats should be 5 instead of 8. + +This commit introduces err_shift for the difference in this register +and fix other existing parameters. + +Public MT7622 reference manual can be found on [0] and the info this +commit is based on is from page 656 and page 660. + +[0]: https://wiki.banana-pi.org/Banana_Pi_BPI-R64#Documents + +Fixes: 98dea8d71931 ("mtd: nand: mtk: Support MT7622 NAND flash controller.") +Signed-off-by: Chuanhong Guo <gch981213@gmail.com> +(cherry picked from commit 088b769abd1bd21753002b17b696ae1778b16e8c) +--- + drivers/mtd/nand/raw/mtk_ecc.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/drivers/mtd/nand/raw/mtk_ecc.c b/drivers/mtd/nand/raw/mtk_ecc.c +index c437d97debb8..ec9d1fb07006 100644 +--- a/drivers/mtd/nand/raw/mtk_ecc.c ++++ b/drivers/mtd/nand/raw/mtk_ecc.c +@@ -43,6 +43,7 @@ + + struct mtk_ecc_caps { + u32 err_mask; ++ u32 err_shift; + const u8 *ecc_strength; + const u32 *ecc_regs; + u8 num_ecc_strength; +@@ -76,7 +77,7 @@ static const u8 ecc_strength_mt2712[] = { + }; + + static const u8 ecc_strength_mt7622[] = { +- 4, 6, 8, 10, 12, 14, 16 ++ 4, 6, 8, 10, 12 + }; + + enum mtk_ecc_regs { +@@ -221,7 +222,7 @@ void mtk_ecc_get_stats(struct mtk_ecc *ecc, struct mtk_ecc_stats *stats, + for (i = 0; i < sectors; i++) { + offset = (i >> 2) << 2; + err = readl(ecc->regs + ECC_DECENUM0 + offset); +- err = err >> ((i % 4) * 8); ++ err = err >> ((i % 4) * ecc->caps->err_shift); + err &= ecc->caps->err_mask; + if (err == ecc->caps->err_mask) { + /* uncorrectable errors */ +@@ -449,6 +450,7 @@ EXPORT_SYMBOL(mtk_ecc_get_parity_bits); + + static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { + .err_mask = 0x3f, ++ .err_shift = 8, + .ecc_strength = ecc_strength_mt2701, + .ecc_regs = mt2701_ecc_regs, + .num_ecc_strength = 20, +@@ -459,6 +461,7 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2701 = { + + static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { + .err_mask = 0x7f, ++ .err_shift = 8, + .ecc_strength = ecc_strength_mt2712, + .ecc_regs = mt2712_ecc_regs, + .num_ecc_strength = 23, +@@ -468,10 +471,11 @@ static const struct mtk_ecc_caps mtk_ecc_caps_mt2712 = { + }; + + static const struct mtk_ecc_caps mtk_ecc_caps_mt7622 = { +- .err_mask = 0x3f, ++ .err_mask = 0x1f, ++ .err_shift = 5, + .ecc_strength = ecc_strength_mt7622, + .ecc_regs = mt7622_ecc_regs, +- .num_ecc_strength = 7, ++ .num_ecc_strength = 5, + .ecc_mode_shift = 4, + .parity_bits = 13, + .pg_irq_sel = 0, +-- +2.35.1 + |