1 files changed, 0 insertions, 87 deletions
diff --git a/target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch b/target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch
deleted file mode 100644
index 18f3e63ac5..0000000000
--- a/target/linux/mediatek/patches-4.14/0220-arm64-dts-mt7622-add-SATA-device-nodes.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 0c8d249a70818f4f8e0d5543dc7157dfd8a5265e Mon Sep 17 00:00:00 2001
-From: Ryder Lee <ryder.lee@mediatek.com>
-Date: Wed, 20 Dec 2017 16:04:24 +0800
-Subject: [PATCH 220/224] arm64: dts: mt7622: add SATA device nodes
-
-This patch adds SATA support fot MT7622.
-
-Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
-Signed-off-by: Sean Wang <sean.wang@mediatek.com>
----
- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts |  8 ++++++
- arch/arm64/boot/dts/mediatek/mt7622.dtsi     | 40 ++++++++++++++++++++++++++++
- 2 files changed, 48 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
-@@ -323,6 +323,14 @@
- 	status = "okay";
- };
- 
-+&sata {
-+	status = "okay";
-+};
-+
-+&sata_phy {
-+	status = "okay";
-+};
-+
- &spi0 {
- 	pinctrl-names = "default";
- 	pinctrl-0 = <&spic0_pins>;
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -9,6 +9,7 @@
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/mt7622-clk.h>
-+#include <dt-bindings/phy/phy.h>
- #include <dt-bindings/power/mt7622-power.h>
- #include <dt-bindings/reset/mt7622-reset.h>
- #include <dt-bindings/thermal/thermal.h>
-@@ -616,6 +617,45 @@
- 		};
- 	};
- 
-+	sata: sata@1a200000 {
-+		compatible = "mediatek,mt7622-ahci",
-+			     "mediatek,mtk-ahci";
-+		reg = <0 0x1a200000 0 0x1100>;
-+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
-+		interrupt-names = "hostc";
-+		clocks = <&pciesys CLK_SATA_AHB_EN>,
-+			 <&pciesys CLK_SATA_AXI_EN>,
-+			 <&pciesys CLK_SATA_ASIC_EN>,
-+			 <&pciesys CLK_SATA_RBC_EN>,
-+			 <&pciesys CLK_SATA_PM_EN>;
-+		clock-names = "ahb", "axi", "asic", "rbc", "pm";
-+		phys = <&sata_port PHY_TYPE_SATA>;
-+		phy-names = "sata-phy";
-+		ports-implemented = <0x1>;
-+		power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
-+		resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
-+			 <&pciesys MT7622_SATA_PHY_SW_RST>,
-+			 <&pciesys MT7622_SATA_PHY_REG_RST>;
-+		reset-names = "axi", "sw", "reg";
-+		mediatek,phy-mode = <&pciesys>;
-+		status = "disabled";
-+	};
-+
-+	sata_phy: sata-phy@1a243000 {
-+		compatible = "mediatek,generic-tphy-v1";
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+		status = "disabled";
-+
-+		sata_port: sata-phy@1a243000 {
-+			reg = <0 0x1a243000 0 0x0100>;
-+			clocks = <&topckgen CLK_TOP_ETH_500M>;
-+			clock-names = "ref";
-+			#phy-cells = <1>;
-+		};
-+	};
-+
- 	ethsys: syscon@1b000000 {
- 		compatible = "mediatek,mt7622-ethsys",
- 			     "syscon";